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qm: improve list of Intel/AMD CPU types in QEMU section
Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
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Fiona Ebner
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qm.adoc
95
qm.adoc
@ -388,77 +388,83 @@ cluster, choose the lowest compatible virtual QEMU CPU type.
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NOTE: Live migrations between Intel and AMD host CPUs have no guarantee to work.
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Intel CPU Types since 2007
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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Intel CPU Types Since 2007 as Defined in QEMU
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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https://en.wikipedia.org/wiki/List_of_Intel_Xeon_processors[Intel Processors]
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https://en.wikipedia.org/wiki/List_of_Intel_Xeon_processors[Intel processors]
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* 'Nahelem' : https://fr.wikipedia.org/wiki/Nehalem[1th generation of the Intel Core Processor]
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* 'Nahelem' : https://en.wikipedia.org/wiki/Nehalem_(microarchitecture)[1st generation of the Intel Core processor]
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+
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* 'Nahelem-IBRS (v2)' : add spectre (+spec-ctrl)
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* 'Nahelem-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
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+
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* 'Westmere' : https://en.wikipedia.org/wiki/Westmere_(microarchitecture)[1th generation of the Intel Core Processor (Xeon E7-)]
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* 'Westmere' : https://en.wikipedia.org/wiki/Westmere_(microarchitecture)[1st generation of the Intel Core processor (Xeon E7-)]
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+
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* 'Westmere-IBRS (v2)' : add spectre (+spec-ctrl)
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* 'Westmere-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
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+
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* 'SandyBridge' : https://fr.wikipedia.org/wiki/Sandy_Bridge[2th generation of the Intel Core Processor]
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* 'SandyBridge' : https://en.wikipedia.org/wiki/Sandy_Bridge[2nd generation of the Intel Core processor]
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+
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* 'SandyBridge-IBRS (v2)' : add spectre v1 protection (+spec-ctrl)
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* 'SandyBridge-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
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+
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* 'IvyBridge' : https://en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)[3th generation of the Intel Core Processor]
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* 'IvyBridge' : https://en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)[3rd generation of the Intel Core processor]
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+
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* 'IvyBridge-IBRS (v2)': add spectre v1 protection (+spec-ctrl)
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* 'IvyBridge-IBRS (v2)': add Spectre v1 protection ('+spec-ctrl')
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+
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* 'Haswell' : https://fr.wikipedia.org/wiki/Haswell_(microarchitecture)[4th generation of the Intel Core Processor]
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* 'Haswell' : https://en.wikipedia.org/wiki/Haswell_(microarchitecture)[4th generation of the Intel Core processor]
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+
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* 'Haswell-noTSX (v2)' : disable TSX (-hle,-rtm)
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* 'Haswell-noTSX (v2)' : disable TSX ('-hle', '-rtm')
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+
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* 'Haswell-IBRS (v3)' : readd TSX, add spectre (+hle,+rtm, +spec-ctrl)
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* 'Haswell-IBRS (v3)' : re-add TSX, add Spectre v1 protection ('+hle', '+rtm',
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'+spec-ctrl')
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+
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* 'Harwell-noTSX-IBRS (v4)' : disable TSX (-hle,-rtm)
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* 'Haswell-noTSX-IBRS (v4)' : disable TSX ('-hle', '-rtm')
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+
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* 'Broadwell': https://en.wikipedia.org/wiki/Broadwell_(microarchitecture)[5th generation of the Intel Core Processor]
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* 'Broadwell': https://en.wikipedia.org/wiki/Broadwell_(microarchitecture)[5th generation of the Intel Core processor]
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+
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* 'Skylake': https://en.wikipedia.org/wiki/Skylake_(microarchitecture)[1st generation Xeon Scalable server processors]
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+
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* 'Skylake-IBRS (v2)' : add +spec-ctrl,-clflushopt
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* 'Skylake-IBRS (v2)' : add Spectre v1 protection, disable CLFLUSHOPT
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('+spec-ctrl', '-clflushopt')
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+
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* 'Skylake-noTSX-IBRS (v3)' : disable TSX (-hle, -rtm)
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* 'Skylake-noTSX-IBRS (v3)' : disable TSX ('-hle', '-rtm')
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+
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* 'Skylake-v4': add EPT switching (+vmx-eptp-switching)
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* 'Skylake-v4': add EPT switching ('+vmx-eptp-switching')
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+
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* 'Cascadelake': https://en.wikipedia.org/wiki/Cascade_Lake_(microprocessor)[2nd generation Xeon scalable processor]
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* 'Cascadelake': https://en.wikipedia.org/wiki/Cascade_Lake_(microprocessor)[2nd generation Xeon Scalable processor]
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+
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* 'Cascadelake-v2' : add arch_capabilities msr (+arch-capabilities,+rdctl-no,+ibrs-all,+skip-l1dfl-vmentry,+mds-no)
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* 'Cascadelake-v2' : add arch_capabilities msr ('+arch-capabilities',
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'+rdctl-no', '+ibrs-all', '+skip-l1dfl-vmentry', '+mds-no')
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+
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* 'Cascadelake-v3' : disable TSX (-hle, -rtm)
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* 'Cascadelake-v3' : disable TSX ('-hle', '-rtm')
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+
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* 'Cascadelake-v4' : add EPT switching (+vmx-eptp-switching)
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* 'Cascadelake-v4' : add EPT switching ('+vmx-eptp-switching')
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+
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* 'Cascadelake-v5' : add XSAVES (+xsaves,+vmx-xsaves)
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* 'Cascadelake-v5' : add XSAVES ('+xsaves', '+vmx-xsaves')
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+
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* 'CooperLake' : https://en.wikipedia.org/wiki/Cooper_Lake_(microprocessor)[3rd generation Xeon scalable processors for 4 & 8 sockets servers]
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* 'Cooperlake' : https://en.wikipedia.org/wiki/Cooper_Lake_(microprocessor)[3rd generation Xeon Scalable processors for 4 & 8 sockets servers]
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+
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* 'CooperLake-v2' : add XSAVES (+xsaves,+vmx-xsaves)
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* 'Cooperlake-v2' : add XSAVES ('+xsaves', '+vmx-xsaves')
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+
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* 'IceLake': https://en.wikipedia.org/wiki/Ice_Lake_(microprocessor)[3rd generation Xeon Scalable server processors]
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* 'Icelake': https://en.wikipedia.org/wiki/Ice_Lake_(microprocessor)[3rd generation Xeon Scalable server processors]
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+
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* 'Icelake-v2' : disable TSX(-hle,-rtm)
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* 'Icelake-v2' : disable TSX ('-hle', '-rtm')
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+
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* 'Icelake-v3' : add arch_capabilities msr (+arch-capabilities, +rdctl-no, +ibrs-all, +skip-l1dfl-vmentry,+mds-no,+pschange-mc-no,+taa-no)
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* 'Icelake-v3' : add arch_capabilities msr ('+arch-capabilities', '+rdctl-no',
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'+ibrs-all', '+skip-l1dfl-vmentry', '+mds-no', '+pschange-mc-no', '+taa-no')
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+
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* 'Icelake-v4' : add missing flags (+sha-ni,+avx512ifma,+rdpid,+fsrm,+vmx-rdseed-exit,+vmx-pml,+vmx-eptp-switching)
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* 'Icelake-v4' : add missing flags ('+sha-ni', '+avx512ifma', '+rdpid', '+fsrm',
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'+vmx-rdseed-exit', '+vmx-pml', '+vmx-eptp-switching')
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+
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* 'Icelake-v5' : add XSAVES (+xsaves,+vmx-xsaves)
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* 'Icelake-v5' : add XSAVES ('+xsaves', '+vmx-xsaves')
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+
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* 'Icelake-v6' : add "5-level EPT" (+vmx-page-walk-5)
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* 'Icelake-v6' : add "5-level EPT" ('+vmx-page-walk-5')
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+
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* 'Sapphire Rapids' : https://en.wikipedia.org/wiki/Sapphire_Rapids[4th generation Xeon Scalable server processors]
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* 'SapphireRapids' : https://en.wikipedia.org/wiki/Sapphire_Rapids[4th generation Xeon Scalable server processors]
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AMD CPU Types since 2007
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^^^^^^^^^^^^^^^^^^^^^^^^
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https://en.wikipedia.org/wiki/List_of_AMD_processors[AMD Processors]
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AMD CPU Types Since 2007 as Defined in QEMU
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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https://en.wikipedia.org/wiki/List_of_AMD_processors[AMD processors]
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* 'Opteron_G3' : https://en.wikipedia.org/wiki/AMD_10h[K10]
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+
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@ -466,19 +472,22 @@ https://en.wikipedia.org/wiki/List_of_AMD_processors[AMD Processors]
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+
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* 'Opteron_G5' : https://en.wikipedia.org/wiki/Piledriver_(microarchitecture)[Piledriver]
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+
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* 'EPYC' : https://en.wikipedia.org/wiki/Zen_(first_generation)[1st Generation of Zen Processors]
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* 'EPYC' : https://en.wikipedia.org/wiki/Zen_(first_generation)[1st generation of Zen processors]
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+
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* 'EPYC-IBPB (v2)' : add spectre v1 protection (+ibpb)
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* 'EPYC-IBPB (v2)' : add Spectre v1 protection ('+ibpb')
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+
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* 'EPYC-v3' : add missing flags (+perfctr-core,+clzero,+xsaveerptr,+xsaves)
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* 'EPYC-v3' : add missing flags ('+perfctr-core', '+clzero', '+xsaveerptr',
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'+xsaves')
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+
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* 'EPYC-Rome' : https://en.wikipedia.org/wiki/Zen_2[2nd Generation of Zen Processors]
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* 'EPYC-Rome' : https://en.wikipedia.org/wiki/Zen_2[2nd generation of Zen processors]
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+
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* 'EPYC-Rome-v2' : add spectre v2,v4 protection (+ibrs,+amd-ssbd)
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* 'EPYC-Rome-v2' : add Spectre v2, v4 protection ('+ibrs', '+amd-ssbd')
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+
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* 'EPYC-Milan' : https://en.wikipedia.org/wiki/Zen_3[3th Generation of Zen Processors]
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* 'EPYC-Milan' : https://en.wikipedia.org/wiki/Zen_3[3rd generation of Zen processors]
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+
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* 'EPYC-Milan-v2' : add missing flags (+vaes,+vpclmulqdq,+stibp-always-on,+amd-psfd,+no-nested-data-bp,+lfence-always-serializing,+null-sel-clr-base
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* 'EPYC-Milan-v2' : add missing flags ('+vaes', '+vpclmulqdq',
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'+stibp-always-on', '+amd-psfd', '+no-nested-data-bp',
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'+lfence-always-serializing', '+null-sel-clr-base')
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QEMU CPU Types
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^^^^^^^^^^^^^^
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