strace/linux/riscv/syscallent.h

/*
 * Copyright (c) 2016-2018 The strace developers.
 * All rights reserved.
 *
 * SPDX-License-Identifier: LGPL-2.1-or-later
 */

#include "64/syscallent.h"

/* #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) */
[259] = { 3,	TM,		SEN(riscv_flush_icache),	"riscv_flush_icache"	},
Add copyright headers to some files that lack them We do our best to keep copyright headers up to date, yet git history provides better information on this subject and is more accurate than copyright headers. 2018-12-24 23:46:43 +00:00			`/*`
			`* Copyright (c) 2016-2018 The strace developers.`
			`* All rights reserved.`
			`*`
			`* SPDX-License-Identifier: LGPL-2.1-or-later`
			`*/`

Add RISC-V architecture support The original port of strace was done by Palmer Dabbelt (eecs.berkeley.edu), based on strace 4.9. * configure.ac: Define RISCV for riscv. clone.c [RISCV]: Define ARG_* macros as for OR1K. * defs.h [RISCV] (SUPPORTED_PERSONALITIES): Define to 2. [RISCV] (NEED_UID16_PARSERS): Define to 1. * linux/riscv/arch_regs.c: New file. * linux/riscv/errnoent1.h: Likewise. * linux/riscv/get_error.c: Likewise. * linux/riscv/get_scno.c: Likewise. * linux/riscv/get_syscall_args.c: Likewise. * linux/riscv/ioctls_arch0.h: Likewise. * linux/riscv/ioctls_arch1.h: Likewise. * linux/riscv/ioctls_inc0.h: Likewise. * linux/riscv/ioctls_inc1.h: Likewise. * linux/riscv/signalent1.h: Likewise. * linux/riscv/stat32.h: Likewise. * linux/riscv/syscallent.h: Likewise. * linux/riscv/syscallent1.h: Likewise. * Makefile.am (EXTRA_DIST): Add them. Signed-off-by: Richard W.M. Jones <rjones@redhat.com> 2016-08-19 14:16:41 +01:00			`#include "64/syscallent.h"`
Implement decoding of riscv_flush_icache syscall * linux/riscv/syscallent.h ([259]): Add riscv_flush_icache entry. * riscv.c: New file. * Makefile.am (strace_SOURCES): Add it. * xlat/riscv_flush_icache_flags.in: New file. * NEWS: Mention it. 2018-01-22 10:23:07 +01:00
			`/* #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) */`
			`[259] = { 3, TM, SEN(riscv_flush_icache), "riscv_flush_icache" },`