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linux/drivers/clk/mediatek/clk-mt8195-vdo1.c

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clk: mediatek: Add MT8195 vdosys1 clock support Add MT8195 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-19-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 10:16:27 +08:00
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vdo1_0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs vdo1_1_cg_regs = {
.set_ofs = 0x124,
.clr_ofs = 0x128,
.sta_ofs = 0x120,
};
static const struct mtk_gate_regs vdo1_2_cg_regs = {
.set_ofs = 0x134,
.clr_ofs = 0x138,
.sta_ofs = 0x130,
};
static const struct mtk_gate_regs vdo1_3_cg_regs = {
.set_ofs = 0x144,
.clr_ofs = 0x148,
.sta_ofs = 0x140,
};
#define GATE_VDO1_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate vdo1_clks[] = {
/* VDO1_0 */
GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
GATE_VDO1_0(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "top_vpp", 1),
GATE_VDO1_0(CLK_VDO1_GALS, "vdo1_gals", "top_vpp", 2),
GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "top_vpp", 3),
GATE_VDO1_0(CLK_VDO1_FAKE_ENG, "vdo1_fake_eng", "top_vpp", 4),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "top_vpp", 5),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "top_vpp", 6),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "top_vpp", 7),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "top_vpp", 8),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "top_vpp", 9),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "top_vpp", 10),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "top_vpp", 11),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "top_vpp", 12),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "top_vpp", 13),
GATE_VDO1_0(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 14),
GATE_VDO1_0(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "top_vpp", 15),
GATE_VDO1_0(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "top_vpp", 16),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "top_vpp", 17),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "top_vpp", 18),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "top_vpp", 19),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "top_vpp", 20),
GATE_VDO1_0(CLK_VDO1_DP_INTF0_MM, "vdo1_dp_intf0_mm", "top_vpp", 21),
GATE_VDO1_0(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm", "top_vpp", 22),
GATE_VDO1_0(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm", "top_vpp", 23),
GATE_VDO1_0(CLK_VDO1_DISP_MONITOR, "vdo1_disp_monitor", "top_vpp", 24),
GATE_VDO1_0(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "top_vpp", 25),
GATE_VDO1_0(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "top_vpp", 26),
GATE_VDO1_0(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "top_vpp", 27),
GATE_VDO1_0(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "top_vpp", 28),
GATE_VDO1_0(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "top_vpp", 29),
GATE_VDO1_0(CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC, "vdo1_vdo0_dsc_to_vdo1_dl_async",
"top_vpp", 30),
GATE_VDO1_0(CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC, "vdo1_vdo0_merge_to_vdo1_dl_async",
"top_vpp", 31),
/* VDO1_1 */
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "top_vpp", 0),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "top_vpp", 1),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "top_vpp", 2),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "top_vpp", 16),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "top_vpp", 17),
GATE_VDO1_1(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "top_vpp", 18),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "top_vpp", 19),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "top_vpp", 20),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "top_vpp", 21),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "top_vpp", 22),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "top_vpp", 23),
/* VDO1_2 */
GATE_VDO1_2(CLK_VDO1_DPI0, "vdo1_dpi0", "top_vpp", 0),
GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0", "top_vpp", 1),
GATE_VDO1_2(CLK_VDO1_DPI1, "vdo1_dpi1", "top_vpp", 8),
GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1", "top_vpp", 9),
GATE_VDO1_2(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_vpp", 16),
GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "top_vpp", 17),
/* VDO1_3 */
GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8),
};
static int clk_mt8195_vdo1_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_VDO1_NR_CLK);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_gates(node, vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
if (r)
goto free_vdo1_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
clk: mediatek: mt8195: Implement error handling in probe functions Until now the mediatek clk driver library did not have any way to unregister clks, and so all drivers did not do proper cleanup in their error paths. Now that the library does have APIs to unregister clks, use them in the error path of the probe functions for the mt8195 clk drivers to do proper cleanup. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220208124034.414635-30-wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-02-08 20:40:32 +08:00
goto unregister_gates;
clk: mediatek: Add MT8195 vdosys1 clock support Add MT8195 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-19-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 10:16:27 +08:00
clk: mediatek: mt8195: Implement remove functions Until now the mediatek clk driver library did not have any way to unregister clks, and so none of the drivers implemented remove functions. Now that the library does have APIs to unregister clks, use them to implement remove functions for the mt8195 clk drivers. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220208124034.414635-31-wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-02-08 20:40:33 +08:00
platform_set_drvdata(pdev, clk_data);
clk: mediatek: Add MT8195 vdosys1 clock support Add MT8195 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-19-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 10:16:27 +08:00
return r;
clk: mediatek: mt8195: Implement error handling in probe functions Until now the mediatek clk driver library did not have any way to unregister clks, and so all drivers did not do proper cleanup in their error paths. Now that the library does have APIs to unregister clks, use them in the error path of the probe functions for the mt8195 clk drivers to do proper cleanup. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220208124034.414635-30-wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-02-08 20:40:32 +08:00
unregister_gates:
mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
clk: mediatek: Add MT8195 vdosys1 clock support Add MT8195 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-19-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 10:16:27 +08:00
free_vdo1_data:
mtk_free_clk_data(clk_data);
return r;
}
clk: mediatek: mt8195: Implement remove functions Until now the mediatek clk driver library did not have any way to unregister clks, and so none of the drivers implemented remove functions. Now that the library does have APIs to unregister clks, use them to implement remove functions for the mt8195 clk drivers. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220208124034.414635-31-wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-02-08 20:40:33 +08:00
static int clk_mt8195_vdo1_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
mtk_free_clk_data(clk_data);
return 0;
}
clk: mediatek: Add MT8195 vdosys1 clock support Add MT8195 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-19-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 10:16:27 +08:00
static struct platform_driver clk_mt8195_vdo1_drv = {
.probe = clk_mt8195_vdo1_probe,
clk: mediatek: mt8195: Implement remove functions Until now the mediatek clk driver library did not have any way to unregister clks, and so none of the drivers implemented remove functions. Now that the library does have APIs to unregister clks, use them to implement remove functions for the mt8195 clk drivers. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220208124034.414635-31-wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-02-08 20:40:33 +08:00
.remove = clk_mt8195_vdo1_remove,
clk: mediatek: Add MT8195 vdosys1 clock support Add MT8195 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-19-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 10:16:27 +08:00
.driver = {
.name = "clk-mt8195-vdo1",
},
};
builtin_platform_driver(clk_mt8195_vdo1_drv);
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