linux/drivers/memory/tegra/Kconfig

# SPDX-License-Identifier: GPL-2.0-only
config TEGRA_MC
	bool "NVIDIA Tegra Memory Controller support"
	default y
	depends on ARCH_TEGRA
	help
	  This driver supports the Memory Controller (MC) hardware found on
	  NVIDIA Tegra SoCs.

config TEGRA20_EMC
	bool "NVIDIA Tegra20 External Memory Controller driver"
	default y
	depends on ARCH_TEGRA_2x_SOC
	help
	  This driver is for the External Memory Controller (EMC) found on
	  Tegra20 chips. The EMC controls the external DRAM on the board.
	  This driver is required to change memory timings / clock rate for
	  external memory.

config TEGRA124_EMC
	bool "NVIDIA Tegra124 External Memory Controller driver"
	default y
	depends on TEGRA_MC && ARCH_TEGRA_124_SOC
	help
	  This driver is for the External Memory Controller (EMC) found on
	  Tegra124 chips. The EMC controls the external DRAM on the board.
	  This driver is required to change memory timings / clock rate for
	  external memory.
treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-19 15:07:45 +03:00			`# SPDX-License-Identifier: GPL-2.0-only`
memory: Add NVIDIA Tegra memory controller support The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com> 2014-04-16 11:24:44 +04:00			`config TEGRA_MC`
			`bool "NVIDIA Tegra Memory Controller support"`
			`default y`
			`depends on ARCH_TEGRA`
			`help`
			`This driver supports the Memory Controller (MC) hardware found on`
			`NVIDIA Tegra SoCs.`
memory: tegra: Add EMC (external memory controller) driver Implements functionality needed to change the rate of the memory bus clock. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-03-12 17:48:03 +03:00
memory: tegra: Introduce Tegra20 EMC driver Introduce driver for the External Memory Controller (EMC) found on Tegra20 chips, which controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2018-10-21 21:30:52 +03:00			`config TEGRA20_EMC`
			`bool "NVIDIA Tegra20 External Memory Controller driver"`
			`default y`
			`depends on ARCH_TEGRA_2x_SOC`
			`help`
			`This driver is for the External Memory Controller (EMC) found on`
			`Tegra20 chips. The EMC controls the external DRAM on the board.`
			`This driver is required to change memory timings / clock rate for`
			`external memory.`

memory: tegra: Add EMC (external memory controller) driver Implements functionality needed to change the rate of the memory bus clock. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-03-12 17:48:03 +03:00			`config TEGRA124_EMC`
			`bool "NVIDIA Tegra124 External Memory Controller driver"`
			`default y`
			`depends on TEGRA_MC && ARCH_TEGRA_124_SOC`
			`help`
			`This driver is for the External Memory Controller (EMC) found on`
			`Tegra124 chips. The EMC controls the external DRAM on the board.`
			`This driver is required to change memory timings / clock rate for`
			`external memory.`