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/ *
* linux/ a r c h / a r m / m m / p r o c - v7 . S
*
* Copyright ( C ) 2 0 0 1 D e e p B l u e S o l u t i o n s L t d .
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify
* it u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e v e r s i o n 2 a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n .
*
* This i s t h e " s h e l l " o f t h e A R M v7 p r o c e s s o r s u p p o r t .
* /
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# include < l i n u x / i n i t . h >
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# include < l i n u x / l i n k a g e . h >
# include < a s m / a s s e m b l e r . h >
# include < a s m / a s m - o f f s e t s . h >
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# include < a s m / h w c a p . h >
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# include < a s m / p g t a b l e - h w d e f . h >
# include < a s m / p g t a b l e . h >
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# include < a s m / m e m o r y . h >
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# include " p r o c - m a c r o s . S "
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# ifdef C O N F I G _ A R M _ L P A E
# include " p r o c - v7 - 3 l e v e l . S "
# else
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# include " p r o c - v7 - 2 l e v e l . S "
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# endif
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ENTRY( c p u _ v7 _ p r o c _ i n i t )
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ret l r
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ENDPROC( c p u _ v7 _ p r o c _ i n i t )
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ENTRY( c p u _ v7 _ p r o c _ f i n )
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mrc p15 , 0 , r0 , c1 , c0 , 0 @ ctrl register
bic r0 , r0 , #0x1000 @ ...i............
bic r0 , r0 , #0x0006 @ .............ca.
mcr p15 , 0 , r0 , c1 , c0 , 0 @ disable caches
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ret l r
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ENDPROC( c p u _ v7 _ p r o c _ f i n )
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/ *
* cpu_ v7 _ r e s e t ( l o c )
*
* Perform a s o f t r e s e t o f t h e s y s t e m . P u t t h e C P U i n t o t h e
* same s t a t e a s i t w o u l d b e i f i t h a d b e e n r e s e t , a n d b r a n c h
* to w h a t w o u l d b e t h e r e s e t v e c t o r .
*
* - loc - l o c a t i o n t o j u m p t o f o r s o f t r e s e t
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*
* This c o d e m u s t b e e x e c u t e d u s i n g a f l a t i d e n t i t y m a p p i n g w i t h
* caches d i s a b l e d .
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* /
.align 5
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.pushsection .idmap .text , " ax"
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ENTRY( c p u _ v7 _ r e s e t )
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mrc p15 , 0 , r1 , c1 , c0 , 0 @ ctrl register
bic r1 , r1 , #0x1 @ ...............m
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THUMB( b i c r1 , r1 , #1 < < 3 0 ) @ SCTLR.TE (Thumb exceptions)
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mcr p15 , 0 , r1 , c1 , c0 , 0 @ disable MMU
isb
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bx r0
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ENDPROC( c p u _ v7 _ r e s e t )
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.popsection
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/ *
* cpu_ v7 _ d o _ i d l e ( )
*
* Idle t h e p r o c e s s o r ( e g , w a i t f o r i n t e r r u p t ) .
*
* IRQs a r e a l r e a d y d i s a b l e d .
* /
ENTRY( c p u _ v7 _ d o _ i d l e )
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dsb @ WFI may enter a low-power mode
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wfi
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ret l r
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ENDPROC( c p u _ v7 _ d o _ i d l e )
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ENTRY( c p u _ v7 _ d c a c h e _ c l e a n _ a r e a )
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ALT_ S M P ( W ( n o p ) ) @ MP extensions imply L1 PTW
ALT_ U P _ B ( 1 f )
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ret l r
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1 : dcache_ l i n e _ s i z e r2 , r3
2 : mcr p15 , 0 , r0 , c7 , c10 , 1 @ clean D entry
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add r0 , r0 , r2
subs r1 , r1 , r2
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bhi 2 b
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dsb i s h s t
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ret l r
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ENDPROC( c p u _ v7 _ d c a c h e _ c l e a n _ a r e a )
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string c p u _ v7 _ n a m e , " A R M v7 P r o c e s s o r "
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.align
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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl cpu_v7_suspend_size
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.equ _ v7 _ s u s p e n d _ s i z e , 4 * 9
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# ifdef C O N F I G _ A R M _ C P U _ S U S P E N D
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ENTRY( c p u _ v7 _ d o _ s u s p e n d )
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stmfd s p ! , { r4 - r11 , l r }
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mrc p15 , 0 , r4 , c13 , c0 , 0 @ FCSE/PID
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mrc p15 , 0 , r5 , c13 , c0 , 3 @ User r/o thread ID
stmia r0 ! , { r4 - r5 }
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# ifdef C O N F I G _ M M U
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mrc p15 , 0 , r6 , c3 , c0 , 0 @ Domain ID
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# ifdef C O N F I G _ A R M _ L P A E
mrrc p15 , 1 , r5 , r7 , c2 @ TTB 1
# else
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mrc p15 , 0 , r7 , c2 , c0 , 1 @ TTB 1
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# endif
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mrc p15 , 0 , r11 , c2 , c0 , 2 @ TTB control register
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# endif
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mrc p15 , 0 , r8 , c1 , c0 , 0 @ Control register
mrc p15 , 0 , r9 , c1 , c0 , 1 @ Auxiliary control register
mrc p15 , 0 , r10 , c1 , c0 , 2 @ Co-processor access control
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stmia r0 , { r5 - r11 }
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ldmfd s p ! , { r4 - r11 , p c }
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ENDPROC( c p u _ v7 _ d o _ s u s p e n d )
ENTRY( c p u _ v7 _ d o _ r e s u m e )
mov i p , #0
mcr p15 , 0 , i p , c7 , c5 , 0 @ invalidate I cache
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mcr p15 , 0 , i p , c13 , c0 , 1 @ set reserved context ID
ldmia r0 ! , { r4 - r5 }
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mcr p15 , 0 , r4 , c13 , c0 , 0 @ FCSE/PID
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mcr p15 , 0 , r5 , c13 , c0 , 3 @ User r/o thread ID
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ldmia r0 , { r5 - r11 }
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# ifdef C O N F I G _ M M U
mcr p15 , 0 , i p , c8 , c7 , 0 @ invalidate TLBs
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mcr p15 , 0 , r6 , c3 , c0 , 0 @ Domain ID
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# ifdef C O N F I G _ A R M _ L P A E
mcrr p15 , 0 , r1 , i p , c2 @ TTB 0
mcrr p15 , 1 , r5 , r7 , c2 @ TTB 1
# else
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ALT_ S M P ( o r r r1 , r1 , #T T B _ F L A G S _ S M P )
ALT_ U P ( o r r r1 , r1 , #T T B _ F L A G S _ U P )
mcr p15 , 0 , r1 , c2 , c0 , 0 @ TTB 0
mcr p15 , 0 , r7 , c2 , c0 , 1 @ TTB 1
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# endif
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mcr p15 , 0 , r11 , c2 , c0 , 2 @ TTB control register
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ldr r4 , =PRRR @ PRRR
ldr r5 , =NMRR @ NMRR
mcr p15 , 0 , r4 , c10 , c2 , 0 @ write PRRR
mcr p15 , 0 , r5 , c10 , c2 , 1 @ write NMRR
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# endif / * C O N F I G _ M M U * /
mrc p15 , 0 , r4 , c1 , c0 , 1 @ Read Auxiliary control register
teq r4 , r9 @ Is it already set?
mcrne p15 , 0 , r9 , c1 , c0 , 1 @ No, so write it
mcr p15 , 0 , r10 , c1 , c0 , 2 @ Co-processor access control
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isb
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dsb
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mov r0 , r8 @ control register
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b c p u _ r e s u m e _ m m u
ENDPROC( c p u _ v7 _ d o _ r e s u m e )
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# endif
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/ *
* Cortex- A 8
* /
globl_ e q u c p u _ c a8 _ p r o c _ i n i t , c p u _ v7 _ p r o c _ i n i t
globl_ e q u c p u _ c a8 _ p r o c _ f i n , c p u _ v7 _ p r o c _ f i n
globl_ e q u c p u _ c a8 _ r e s e t , c p u _ v7 _ r e s e t
globl_ e q u c p u _ c a8 _ d o _ i d l e , c p u _ v7 _ d o _ i d l e
globl_ e q u c p u _ c a8 _ d c a c h e _ c l e a n _ a r e a , c p u _ v7 _ d c a c h e _ c l e a n _ a r e a
globl_ e q u c p u _ c a8 _ s e t _ p t e _ e x t , c p u _ v7 _ s e t _ p t e _ e x t
globl_ e q u c p u _ c a8 _ s u s p e n d _ s i z e , c p u _ v7 _ s u s p e n d _ s i z e
# ifdef C O N F I G _ A R M _ C P U _ S U S P E N D
globl_ e q u c p u _ c a8 _ d o _ s u s p e n d , c p u _ v7 _ d o _ s u s p e n d
globl_ e q u c p u _ c a8 _ d o _ r e s u m e , c p u _ v7 _ d o _ r e s u m e
# endif
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/ *
* Cortex- A 9 p r o c e s s o r f u n c t i o n s
* /
globl_ e q u c p u _ c a9 m p _ p r o c _ i n i t , c p u _ v7 _ p r o c _ i n i t
globl_ e q u c p u _ c a9 m p _ p r o c _ f i n , c p u _ v7 _ p r o c _ f i n
globl_ e q u c p u _ c a9 m p _ r e s e t , c p u _ v7 _ r e s e t
globl_ e q u c p u _ c a9 m p _ d o _ i d l e , c p u _ v7 _ d o _ i d l e
globl_ e q u c p u _ c a9 m p _ d c a c h e _ c l e a n _ a r e a , c p u _ v7 _ d c a c h e _ c l e a n _ a r e a
globl_ e q u c p u _ c a9 m p _ s w i t c h _ m m , c p u _ v7 _ s w i t c h _ m m
globl_ e q u c p u _ c a9 m p _ s e t _ p t e _ e x t , c p u _ v7 _ s e t _ p t e _ e x t
.globl cpu_ca9mp_suspend_size
.equ _ c a9 m p _ s u s p e n d _ s i z e , c p u _ v7 _ s u s p e n d _ s i z e + 4 * 2
# ifdef C O N F I G _ A R M _ C P U _ S U S P E N D
ENTRY( c p u _ c a9 m p _ d o _ s u s p e n d )
stmfd s p ! , { r4 - r5 }
mrc p15 , 0 , r4 , c15 , c0 , 1 @ Diagnostic register
mrc p15 , 0 , r5 , c15 , c0 , 0 @ Power register
stmia r0 ! , { r4 - r5 }
ldmfd s p ! , { r4 - r5 }
b c p u _ v7 _ d o _ s u s p e n d
ENDPROC( c p u _ c a9 m p _ d o _ s u s p e n d )
ENTRY( c p u _ c a9 m p _ d o _ r e s u m e )
ldmia r0 ! , { r4 - r5 }
mrc p15 , 0 , r10 , c15 , c0 , 1 @ Read Diagnostic register
teq r4 , r10 @ Already restored?
mcrne p15 , 0 , r4 , c15 , c0 , 1 @ No, so restore it
mrc p15 , 0 , r10 , c15 , c0 , 0 @ Read Power register
teq r5 , r10 @ Already restored?
mcrne p15 , 0 , r5 , c15 , c0 , 0 @ No, so restore it
b c p u _ v7 _ d o _ r e s u m e
ENDPROC( c p u _ c a9 m p _ d o _ r e s u m e )
# endif
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# ifdef C O N F I G _ C P U _ P J 4 B
globl_ e q u c p u _ p j 4 b _ s w i t c h _ m m , c p u _ v7 _ s w i t c h _ m m
globl_ e q u c p u _ p j 4 b _ s e t _ p t e _ e x t , c p u _ v7 _ s e t _ p t e _ e x t
globl_ e q u c p u _ p j 4 b _ p r o c _ i n i t , c p u _ v7 _ p r o c _ i n i t
globl_ e q u c p u _ p j 4 b _ p r o c _ f i n , c p u _ v7 _ p r o c _ f i n
globl_ e q u c p u _ p j 4 b _ r e s e t , c p u _ v7 _ r e s e t
# ifdef C O N F I G _ P J 4 B _ E R R A T A _ 4 7 4 2
ENTRY( c p u _ p j 4 b _ d o _ i d l e )
dsb @ WFI may enter a low-power mode
wfi
dsb @barrier
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ret l r
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ENDPROC( c p u _ p j 4 b _ d o _ i d l e )
# else
globl_ e q u c p u _ p j 4 b _ d o _ i d l e , c p u _ v7 _ d o _ i d l e
# endif
globl_ e q u c p u _ p j 4 b _ d c a c h e _ c l e a n _ a r e a , c p u _ v7 _ d c a c h e _ c l e a n _ a r e a
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# ifdef C O N F I G _ A R M _ C P U _ S U S P E N D
ENTRY( c p u _ p j 4 b _ d o _ s u s p e n d )
stmfd s p ! , { r6 - r10 }
mrc p15 , 1 , r6 , c15 , c1 , 0 @ save CP15 - extra features
mrc p15 , 1 , r7 , c15 , c2 , 0 @ save CP15 - Aux Func Modes Ctrl 0
mrc p15 , 1 , r8 , c15 , c1 , 2 @ save CP15 - Aux Debug Modes Ctrl 2
mrc p15 , 1 , r9 , c15 , c1 , 1 @ save CP15 - Aux Debug Modes Ctrl 1
mrc p15 , 0 , r10 , c9 , c14 , 0 @ save CP15 - PMC
stmia r0 ! , { r6 - r10 }
ldmfd s p ! , { r6 - r10 }
b c p u _ v7 _ d o _ s u s p e n d
ENDPROC( c p u _ p j 4 b _ d o _ s u s p e n d )
ENTRY( c p u _ p j 4 b _ d o _ r e s u m e )
ldmia r0 ! , { r6 - r10 }
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mcr p15 , 1 , r6 , c15 , c1 , 0 @ restore CP15 - extra features
mcr p15 , 1 , r7 , c15 , c2 , 0 @ restore CP15 - Aux Func Modes Ctrl 0
mcr p15 , 1 , r8 , c15 , c1 , 2 @ restore CP15 - Aux Debug Modes Ctrl 2
mcr p15 , 1 , r9 , c15 , c1 , 1 @ restore CP15 - Aux Debug Modes Ctrl 1
mcr p15 , 0 , r10 , c9 , c14 , 0 @ restore CP15 - PMC
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b c p u _ v7 _ d o _ r e s u m e
ENDPROC( c p u _ p j 4 b _ d o _ r e s u m e )
# endif
.globl cpu_pj4b_suspend_size
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.equ _ p j 4 b _ s u s p e n d _ s i z e , c p u _ v7 _ s u s p e n d _ s i z e + 4 * 5
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# endif
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/ *
* _ _ v7 _ s e t u p
*
* Initialise T L B , C a c h e s , a n d M M U s t a t e r e a d y t o s w i t c h t h e M M U
* on. R e t u r n i n r0 t h e n e w C P 1 5 C 1 c o n t r o l r e g i s t e r s e t t i n g .
*
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* r1 , r2 , r4 , r5 , r9 , r13 m u s t b e p r e s e r v e d - r13 i s n o t a s t a c k
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
* r4 : TTBR0 ( l o w w o r d )
* r5 : TTBR0 ( h i g h w o r d i f L P A E )
* r8 : TTBR1
* r9 : Main I D r e g i s t e r
*
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* This s h o u l d b e a b l e t o c o v e r a l l A R M v7 c o r e s .
*
* It i s a s s u m e d t h a t :
* - cache t y p e r e g i s t e r i s i m p l e m e n t e d
* /
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__v7_ca5mp_setup :
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__v7_ca9mp_setup :
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__v7_cr7mp_setup :
mov r10 , #( 1 < < 0 ) @ Cache/TLB ops broadcasting
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b 1 f
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__v7_ca7mp_setup :
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__v7_ca12mp_setup :
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__v7_ca15mp_setup :
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__v7_b15mp_setup :
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__v7_ca17mp_setup :
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mov r10 , #0
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1 : adr r0 , _ _ v7 _ s e t u p _ s t a c k _ p t r
ldr r12 , [ r0 ]
add r12 , r12 , r0 @ the local stack
stmia r12 , { r1 - r6 , l r } @ v7_invalidate_l1 touches r0-r6
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bl v7 _ i n v a l i d a t e _ l 1
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ldmia r12 , { r1 - r6 , l r }
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# ifdef C O N F I G _ S M P
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orr r10 , r10 , #( 1 < < 6 ) @ Enable SMP/nAMP mode
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ALT_ S M P ( m r c p15 , 0 , r0 , c1 , c0 , 1 )
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ALT_ U P ( m o v r0 , r10 ) @ fake it for UP
orr r10 , r10 , r0 @ Set required bits
teq r10 , r0 @ Were they already set?
mcrne p15 , 0 , r10 , c1 , c0 , 1 @ No, update register
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# endif
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b _ _ v7 _ s e t u p _ c o n t
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2015-04-04 21:46:35 +01:00
/ *
* Errata :
* r0 , r10 a v a i l a b l e f o r u s e
* r1 , r2 , r4 , r5 , r9 , r13 : m u s t b e p r e s e r v e d
* r3 : contains M I D R r X n u m b e r i n b i t s 2 3 - 2 0
* r6 : contains M I D R r X p Y a s 8 - b i t X Y n u m b e r
* r9 : MIDR
* /
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
__ca8_errata :
# if d e f i n e d ( C O N F I G _ A R M _ E R R A T A _ 4 3 0 9 7 3 ) & & ! d e f i n e d ( C O N F I G _ A R C H _ M U L T I P L A T F O R M )
teq r3 , #0x00100000 @ only present in r1p*
2015-04-04 21:46:35 +01:00
mrceq p15 , 0 , r0 , c1 , c0 , 1 @ read aux control register
orreq r0 , r0 , #( 1 < < 6 ) @ set IBE to 1
mcreq p15 , 0 , r0 , c1 , c0 , 1 @ write aux control register
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
# endif
# ifdef C O N F I G _ A R M _ E R R A T A _ 4 5 8 6 9 3
teq r6 , #0x20 @ only present in r2p0
2015-04-04 21:46:35 +01:00
mrceq p15 , 0 , r0 , c1 , c0 , 1 @ read aux control register
orreq r0 , r0 , #( 1 < < 5 ) @ set L1NEON to 1
orreq r0 , r0 , #( 1 < < 9 ) @ set PLDNOP to 1
mcreq p15 , 0 , r0 , c1 , c0 , 1 @ write aux control register
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
# endif
# ifdef C O N F I G _ A R M _ E R R A T A _ 4 6 0 0 7 5
teq r6 , #0x20 @ only present in r2p0
2015-04-04 21:46:35 +01:00
mrceq p15 , 1 , r0 , c9 , c0 , 2 @ read L2 cache aux ctrl register
tsteq r0 , #1 < < 2 2
orreq r0 , r0 , #( 1 < < 2 2 ) @ set the Write Allocate disable bit
mcreq p15 , 1 , r0 , c9 , c0 , 2 @ write the L2 cache aux ctrl register
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
# endif
b _ _ e r r a t a _ f i n i s h
__ca9_errata :
# ifdef C O N F I G _ A R M _ E R R A T A _ 7 4 2 2 3 0
cmp r6 , #0x22 @ only present up to r2p2
2015-04-04 21:46:35 +01:00
mrcle p15 , 0 , r0 , c15 , c0 , 1 @ read diagnostic register
orrle r0 , r0 , #1 < < 4 @ set bit #4
mcrle p15 , 0 , r0 , c15 , c0 , 1 @ write diagnostic register
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
# endif
# ifdef C O N F I G _ A R M _ E R R A T A _ 7 4 2 2 3 1
teq r6 , #0x20 @ present in r2p0
teqne r6 , #0x21 @ present in r2p1
teqne r6 , #0x22 @ present in r2p2
2015-04-04 21:46:35 +01:00
mrceq p15 , 0 , r0 , c15 , c0 , 1 @ read diagnostic register
orreq r0 , r0 , #1 < < 1 2 @ set bit #12
orreq r0 , r0 , #1 < < 2 2 @ set bit #22
mcreq p15 , 0 , r0 , c15 , c0 , 1 @ write diagnostic register
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
# endif
# ifdef C O N F I G _ A R M _ E R R A T A _ 7 4 3 6 2 2
teq r3 , #0x00200000 @ only present in r2p*
2015-04-04 21:46:35 +01:00
mrceq p15 , 0 , r0 , c15 , c0 , 1 @ read diagnostic register
orreq r0 , r0 , #1 < < 6 @ set bit #6
mcreq p15 , 0 , r0 , c15 , c0 , 1 @ write diagnostic register
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
# endif
# if d e f i n e d ( C O N F I G _ A R M _ E R R A T A _ 7 5 1 4 7 2 ) & & d e f i n e d ( C O N F I G _ S M P )
ALT_ S M P ( c m p r6 , #0x30 ) @ present prior to r3p0
ALT_ U P _ B ( 1 f )
2015-04-04 21:46:35 +01:00
mrclt p15 , 0 , r0 , c15 , c0 , 1 @ read diagnostic register
orrlt r0 , r0 , #1 < < 1 1 @ set bit #11
mcrlt p15 , 0 , r0 , c15 , c0 , 1 @ write diagnostic register
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
1 :
# endif
b _ _ e r r a t a _ f i n i s h
__ca15_errata :
# ifdef C O N F I G _ A R M _ E R R A T A _ 7 7 3 0 2 2
cmp r6 , #0x4 @ only present up to r0p4
2015-04-04 21:46:35 +01:00
mrcle p15 , 0 , r0 , c1 , c0 , 1 @ read aux control register
orrle r0 , r0 , #1 < < 1 @ disable loop buffer
mcrle p15 , 0 , r0 , c1 , c0 , 1 @ write aux control register
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
# endif
b _ _ e r r a t a _ f i n i s h
2016-04-07 00:25:00 +01:00
__ca12_errata :
# ifdef C O N F I G _ A R M _ E R R A T A _ 8 1 8 3 2 5 _ 8 5 2 4 2 2
mrc p15 , 0 , r10 , c15 , c0 , 1 @ read diagnostic register
orr r10 , r10 , #1 < < 1 2 @ set bit #12
mcr p15 , 0 , r10 , c15 , c0 , 1 @ write diagnostic register
2016-04-07 00:26:05 +01:00
# endif
# ifdef C O N F I G _ A R M _ E R R A T A _ 8 2 1 4 2 0
mrc p15 , 0 , r10 , c15 , c0 , 2 @ read internal feature reg
orr r10 , r10 , #1 < < 1 @ set bit #1
mcr p15 , 0 , r10 , c15 , c0 , 2 @ write internal feature reg
2016-04-07 00:27:26 +01:00
# endif
# ifdef C O N F I G _ A R M _ E R R A T A _ 8 2 5 6 1 9
mrc p15 , 0 , r10 , c15 , c0 , 1 @ read diagnostic register
orr r10 , r10 , #1 < < 2 4 @ set bit #24
mcr p15 , 0 , r10 , c15 , c0 , 1 @ write diagnostic register
2016-04-07 00:25:00 +01:00
# endif
b _ _ e r r a t a _ f i n i s h
__ca17_errata :
2016-04-07 00:27:26 +01:00
# ifdef C O N F I G _ A R M _ E R R A T A _ 8 5 2 4 2 1
cmp r6 , #0x12 @ only present up to r1p2
mrcle p15 , 0 , r10 , c15 , c0 , 1 @ read diagnostic register
orrle r10 , r10 , #1 < < 2 4 @ set bit #24
mcrle p15 , 0 , r10 , c15 , c0 , 1 @ write diagnostic register
# endif
2016-04-07 00:25:00 +01:00
# ifdef C O N F I G _ A R M _ E R R A T A _ 8 5 2 4 2 3
cmp r6 , #0x12 @ only present up to r1p2
mrcle p15 , 0 , r10 , c15 , c0 , 1 @ read diagnostic register
orrle r10 , r10 , #1 < < 1 2 @ set bit #12
mcrle p15 , 0 , r10 , c15 , c0 , 1 @ write diagnostic register
# endif
b _ _ e r r a t a _ f i n i s h
2012-10-03 11:58:07 +02:00
__v7_pj4b_setup :
# ifdef C O N F I G _ C P U _ P J 4 B
/* Auxiliary Debug Modes Control 1 Register */
# define P J 4 B _ S T A T I C _ B P ( 1 < < 2 ) / * E n a b l e S t a t i c B P * /
# define P J 4 B _ I N T E R _ P A R I T Y ( 1 < < 8 ) / * D i s a b l e I n t e r n a l P a r i t y H a n d l i n g * /
# define P J 4 B _ C L E A N _ L I N E ( 1 < < 1 6 ) / * D i s a b l e d a t a t r a n s f e r f o r c l e a n l i n e * /
/* Auxiliary Debug Modes Control 2 Register */
# define P J 4 B _ F A S T _ L D R ( 1 < < 2 3 ) / * D i s a b l e f a s t L D R * /
# define P J 4 B _ S N O O P _ D A T A ( 1 < < 2 5 ) / * D o n o t i n t e r l e a v e w r i t e a n d s n o o p d a t a * /
# define P J 4 B _ C W F ( 1 < < 2 7 ) / * D i s a b l e C r i t i c a l W o r d F i r s t f e a t u r e * /
# define P J 4 B _ O U T S D N G _ N C ( 1 < < 2 9 ) / * D i s a b l e o u t s t a n d i n g n o n c a c h e a b l e r q s t * /
# define P J 4 B _ L 1 _ R E P _ R R ( 1 < < 3 0 ) / * L 1 r e p l a c e m e n t - S t r i c t r o u n d r o b i n * /
# define P J 4 B _ A U X _ D B G _ C T R L 2 ( P J 4 B _ S N O O P _ D A T A | P J 4 B _ C W F | \
PJ4 B _ O U T S D N G _ N C | P J 4 B _ L 1 _ R E P _ R R )
/* Auxiliary Functional Modes Control Register 0 */
# define P J 4 B _ S M P _ C F B ( 1 < < 1 ) / * S e t S M P m o d e . J o i n t h e c o h e r e n c y f a b r i c * /
# define P J 4 B _ L 1 _ P A R _ C H K ( 1 < < 2 ) / * S u p p o r t L 1 p a r i t y c h e c k i n g * /
# define P J 4 B _ B R O A D C A S T _ C A C H E ( 1 < < 8 ) / * B r o a d c a s t C a c h e a n d T L B m a i n t e n a n c e * /
/* Auxiliary Debug Modes Control 0 Register */
# define P J 4 B _ W F I _ W F E ( 1 < < 2 2 ) / * W F I / W F E - s e r v e t h e D V M a n d b a c k t o i d l e * /
/* Auxiliary Debug Modes Control 1 Register */
mrc p15 , 1 , r0 , c15 , c1 , 1
orr r0 , r0 , #P J 4 B _ C L E A N _ L I N E
orr r0 , r0 , #P J 4 B _ I N T E R _ P A R I T Y
bic r0 , r0 , #P J 4 B _ S T A T I C _ B P
mcr p15 , 1 , r0 , c15 , c1 , 1
/* Auxiliary Debug Modes Control 2 Register */
mrc p15 , 1 , r0 , c15 , c1 , 2
bic r0 , r0 , #P J 4 B _ F A S T _ L D R
orr r0 , r0 , #P J 4 B _ A U X _ D B G _ C T R L 2
mcr p15 , 1 , r0 , c15 , c1 , 2
/* Auxiliary Functional Modes Control Register 0 */
mrc p15 , 1 , r0 , c15 , c2 , 0
# ifdef C O N F I G _ S M P
orr r0 , r0 , #P J 4 B _ S M P _ C F B
# endif
orr r0 , r0 , #P J 4 B _ L 1 _ P A R _ C H K
orr r0 , r0 , #P J 4 B _ B R O A D C A S T _ C A C H E
mcr p15 , 1 , r0 , c15 , c2 , 0
/* Auxiliary Debug Modes Control 0 Register */
mrc p15 , 1 , r0 , c15 , c1 , 0
orr r0 , r0 , #P J 4 B _ W F I _ W F E
mcr p15 , 1 , r0 , c15 , c1 , 0
# endif / * C O N F I G _ C P U _ P J 4 B * /
2010-09-17 16:42:10 +01:00
__v7_setup :
2015-12-04 21:36:40 +01:00
adr r0 , _ _ v7 _ s e t u p _ s t a c k _ p t r
ldr r12 , [ r0 ]
add r12 , r12 , r0 @ the local stack
stmia r12 , { r1 - r6 , l r } @ v7_invalidate_l1 touches r0-r6
2015-05-19 17:06:44 +01:00
bl v7 _ i n v a l i d a t e _ l 1
2015-12-04 21:36:40 +01:00
ldmia r12 , { r1 - r6 , l r }
2009-06-01 12:50:33 +01:00
2015-07-09 00:30:24 +01:00
__v7_setup_cont :
2015-04-04 21:46:35 +01:00
and r0 , r9 , #0xff000000 @ ARM?
teq r0 , #0x41000000
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
bne _ _ e r r a t a _ f i n i s h
2015-04-04 21:36:35 +01:00
and r3 , r9 , #0x00f00000 @ variant
and r6 , r9 , #0x0000000f @ revision
2015-04-04 20:09:46 +01:00
orr r6 , r6 , r3 , l s r #20 - 4 @ combine variant and revision
2015-04-04 21:36:35 +01:00
ubfx r0 , r9 , #4 , #12 @ primary part number
2009-06-01 12:50:33 +01:00
2010-09-14 09:50:03 +01:00
/* Cortex-A8 Errata */
ldr r10 , =0x00000c08 @ Cortex-A8 primary part number
teq r0 , r10
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
beq _ _ c a8 _ e r r a t a
2010-09-14 09:51:43 +01:00
/* Cortex-A9 Errata */
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
ldr r10 , =0x00000c09 @ Cortex-A9 primary part number
2010-09-14 09:51:43 +01:00
teq r0 , r10
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
beq _ _ c a9 _ e r r a t a
2009-06-01 12:50:33 +01:00
2016-04-07 00:25:00 +01:00
/* Cortex-A12 Errata */
ldr r10 , =0x00000c0d @ Cortex-A12 primary part number
teq r0 , r10
beq _ _ c a12 _ e r r a t a
/* Cortex-A17 Errata */
ldr r10 , =0x00000c0e @ Cortex-A17 primary part number
teq r0 , r10
beq _ _ c a17 _ e r r a t a
2013-08-20 17:29:55 +01:00
/* Cortex-A15 Errata */
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
ldr r10 , =0x00000c0f @ Cortex-A15 primary part number
2013-08-20 17:29:55 +01:00
teq r0 , r10
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
beq _ _ c a15 _ e r r a t a
2013-08-20 17:29:55 +01:00
ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard
to maintain properly, move the CPU errata out of line.
While doing this, it was discovered that the Cortex-A15 errata had been
incorrectly added:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
/* Cortex-A8 errata */
b 3f
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
/* Cortex-A9 errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
/* Cortex-A15 errata */
4:
This results in the Cortex-A15 test always being executed after the
Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended.
The 'b 3f' labels should have been updated to 'b 4f'. The new structure
of:
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
beq __ca8_errata
/* Cortex-A9 Errata */
ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
beq __ca9_errata
/* Cortex-A15 Errata */
ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
beq __ca15_errata
__errata_finish:
is much cleaner and easier to see that this kind of thing doesn't
happen.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 21:34:33 +01:00
__errata_finish :
mov r10 , #0
2007-05-08 22:27:46 +01:00
mcr p15 , 0 , r10 , c7 , c5 , 0 @ I+BTB cache invalidate
2007-07-20 11:43:02 +01:00
# ifdef C O N F I G _ M M U
2007-05-08 22:27:46 +01:00
mcr p15 , 0 , r10 , c8 , c7 , 0 @ invalidate I + D TLBs
2015-04-04 20:09:46 +01:00
v7 _ t t b _ s e t u p r10 , r4 , r5 , r8 , r3 @ TTBCR, TTBRx setup
ldr r3 , =PRRR @ PRRR
2011-02-06 15:48:39 +00:00
ldr r6 , =NMRR @ NMRR
2015-04-04 20:09:46 +01:00
mcr p15 , 0 , r3 , c10 , c2 , 0 @ write PRRR
2008-09-15 17:23:10 +01:00
mcr p15 , 0 , r6 , c10 , c2 , 1 @ write NMRR
2012-04-12 17:45:25 +01:00
# endif
2014-02-07 19:12:20 +01:00
dsb @ Complete invalidations
2012-04-12 17:45:25 +01:00
# ifndef C O N F I G _ A R M _ T H U M B E E
mrc p15 , 0 , r0 , c0 , c1 , 0 @ read ID_PFR0 for ThumbEE
and r0 , r0 , #( 0xf < < 1 2 ) @ ThumbEE enabled field
teq r0 , #( 1 < < 1 2 ) @ check if ThumbEE is present
bne 1 f
2015-04-04 20:09:46 +01:00
mov r3 , #0
mcr p14 , 6 , r3 , c1 , c0 , 0 @ Initialize TEEHBR to 0
2012-04-12 17:45:25 +01:00
mrc p14 , 6 , r0 , c0 , c0 , 0 @ load TEECR
orr r0 , r0 , #1 @ set the 1st bit in order to
mcr p14 , 6 , r0 , c0 , c0 , 0 @ stop userspace TEEHBR access
1 :
2009-07-24 12:35:06 +01:00
# endif
2015-04-04 20:09:46 +01:00
adr r3 , v7 _ c r v a l
ldmia r3 , { r3 , r6 }
2013-02-12 18:59:57 +00:00
ARM_ B E 8 ( o r r r6 , r6 , #1 < < 2 5 ) @ big-endian page tables
2010-09-16 18:00:47 +01:00
# ifdef C O N F I G _ S W P _ E M U L A T E
2015-04-04 20:09:46 +01:00
orr r3 , r3 , #( 1 < < 1 0 ) @ set SW bit in "clear"
2010-09-16 18:00:47 +01:00
bic r6 , r6 , #( 1 < < 1 0 ) @ clear it in "mmuset"
2009-05-30 14:00:18 +01:00
# endif
2007-07-20 11:43:02 +01:00
mrc p15 , 0 , r0 , c1 , c0 , 0 @ read control register
2015-04-04 20:09:46 +01:00
bic r0 , r0 , r3 @ clear bits them
2007-07-20 11:43:02 +01:00
orr r0 , r0 , r6 @ set them
2009-07-24 12:32:56 +01:00
THUMB( o r r r0 , r0 , #1 < < 3 0 ) @ Thumb exceptions
2014-06-30 16:29:12 +01:00
ret l r @ return to head.S:__ret
2015-12-04 21:36:40 +01:00
.align 2
__v7_setup_stack_ptr :
2016-02-16 17:33:56 +00:00
.word _ R E L A T I V E ( _ _ v7 _ s e t u p _ s t a c k , . )
2008-08-28 11:22:32 +01:00
ENDPROC( _ _ v7 _ s e t u p )
2007-05-08 22:27:46 +01:00
2015-12-04 21:36:40 +01:00
.bss
2011-11-22 17:30:28 +00:00
.align 2
2007-05-08 22:27:46 +01:00
__v7_setup_stack :
2015-12-04 21:36:40 +01:00
.space 4 * 7 @ 7 registers
2007-05-08 22:27:46 +01:00
2010-10-01 15:37:05 +01:00
_ _ INITDATA
2011-06-23 17:26:19 +01:00
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
define_ p r o c e s s o r _ f u n c t i o n s v7 , d a b o r t =v7_early_abort , p a b o r t =v7_pabort , s u s p e n d =1
2015-04-07 15:35:24 +01:00
# ifndef C O N F I G _ A R M _ L P A E
define_ p r o c e s s o r _ f u n c t i o n s c a8 , d a b o r t =v7_early_abort , p a b o r t =v7_pabort , s u s p e n d =1
2014-07-16 07:40:53 +01:00
define_ p r o c e s s o r _ f u n c t i o n s c a9 m p , d a b o r t =v7_early_abort , p a b o r t =v7_pabort , s u s p e n d =1
2015-04-07 15:35:24 +01:00
# endif
2013-06-23 10:17:11 +01:00
# ifdef C O N F I G _ C P U _ P J 4 B
define_ p r o c e s s o r _ f u n c t i o n s p j 4 b , d a b o r t =v7_early_abort , p a b o r t =v7_pabort , s u s p e n d =1
# endif
2007-05-08 22:27:46 +01:00
2010-10-01 15:37:05 +01:00
.section " .rodata "
2011-06-23 17:26:19 +01:00
string c p u _ a r c h _ n a m e , " a r m v7 "
string c p u _ e l f _ n a m e , " v7 "
2007-05-08 22:27:46 +01:00
.align
2015-03-18 07:29:32 +01:00
.section " .proc .info .init " , # alloc
2007-05-08 22:27:46 +01:00
2011-05-20 14:39:28 +01:00
/ *
* Standard v7 p r o c i n f o c o n t e n t
* /
2015-03-18 07:29:32 +01:00
.macro __v7_proc name, i n i t f u n c , m m _ m m u f l a g s = 0 , i o _ m m u f l a g s = 0 , h w c a p s = 0 , p r o c _ f n s = v7 _ p r o c e s s o r _ f u n c t i o n s
2011-05-20 14:39:28 +01:00
ALT_ S M P ( . l o n g P M D _ T Y P E _ S E C T | P M D _ S E C T _ A P _ W R I T E | P M D _ S E C T _ A P _ R E A D | \
2011-11-22 17:30:29 +00:00
PMD_ S E C T _ A F | P M D _ F L A G S _ S M P | \ m m _ m m u f l a g s )
2011-05-20 14:39:28 +01:00
ALT_ U P ( . l o n g P M D _ T Y P E _ S E C T | P M D _ S E C T _ A P _ W R I T E | P M D _ S E C T _ A P _ R E A D | \
2011-11-22 17:30:29 +00:00
PMD_ S E C T _ A F | P M D _ F L A G S _ U P | \ m m _ m m u f l a g s )
.long PMD_TYPE_SECT | PMD_ S E C T _ A P _ W R I T E | \
PMD_ S E C T _ A P _ R E A D | P M D _ S E C T _ A F | \ i o _ m m u f l a g s
2015-03-18 07:29:32 +01:00
initfn \ i n i t f u n c , \ n a m e
2010-09-17 16:42:10 +01:00
.long cpu_arch_name
.long cpu_elf_name
2011-05-20 14:39:28 +01:00
.long HWCAP_SWP | HWCAP_ H A L F | H W C A P _ T H U M B | H W C A P _ F A S T _ M U L T | \
HWCAP_ E D S P | H W C A P _ T L S | \ h w c a p s
2010-09-17 16:42:10 +01:00
.long cpu_v7_name
2013-06-23 10:17:11 +01:00
.long \ proc_ f n s
2010-09-17 16:42:10 +01:00
.long v7wbi_tlb_fns
.long v6_user_fns
.long v7_cache_fns
2011-05-20 14:39:28 +01:00
.endm
2011-11-22 17:30:29 +00:00
# ifndef C O N F I G _ A R M _ L P A E
2011-05-20 14:39:29 +01:00
/ *
* ARM L t d . C o r t e x A 5 p r o c e s s o r .
* /
.type _ _ v7 _ c a5 m p _ p r o c _ i n f o , #o b j e c t
__v7_ca5mp_proc_info :
.long 0x410fc050
.long 0xff0ffff0
2015-03-18 07:29:32 +01:00
_ _ v7 _ p r o c _ _ v7 _ c a5 m p _ p r o c _ i n f o , _ _ v7 _ c a5 m p _ s e t u p
2011-05-20 14:39:29 +01:00
.size _ _ v7 _ c a5 m p _ p r o c _ i n f o , . - _ _ v7 _ c a5 m p _ p r o c _ i n f o
2011-05-20 14:39:28 +01:00
/ *
* ARM L t d . C o r t e x A 9 p r o c e s s o r .
* /
.type _ _ v7 _ c a9 m p _ p r o c _ i n f o , #o b j e c t
__v7_ca9mp_proc_info :
.long 0x410fc090
.long 0xff0ffff0
2015-03-18 07:29:32 +01:00
_ _ v7 _ p r o c _ _ v7 _ c a9 m p _ p r o c _ i n f o , _ _ v7 _ c a9 m p _ s e t u p , p r o c _ f n s = c a9 m p _ p r o c e s s o r _ f u n c t i o n s
2010-09-17 16:42:10 +01:00
.size _ _ v7 _ c a9 m p _ p r o c _ i n f o , . - _ _ v7 _ c a9 m p _ p r o c _ i n f o
2012-10-03 11:58:07 +02:00
2015-04-07 15:35:24 +01:00
/ *
* ARM L t d . C o r t e x A 8 p r o c e s s o r .
* /
.type _ _ v7 _ c a8 _ p r o c _ i n f o , #o b j e c t
__v7_ca8_proc_info :
.long 0x410fc080
.long 0xff0ffff0
_ _ v7 _ p r o c _ _ v7 _ c a8 _ p r o c _ i n f o , _ _ v7 _ s e t u p , p r o c _ f n s = c a8 _ p r o c e s s o r _ f u n c t i o n s
.size _ _ v7 _ c a8 _ p r o c _ i n f o , . - _ _ v7 _ c a8 _ p r o c _ i n f o
2013-04-09 13:37:20 +01:00
# endif / * C O N F I G _ A R M _ L P A E * /
2012-10-03 11:58:07 +02:00
/ *
* Marvell P J 4 B p r o c e s s o r .
* /
2013-06-23 10:17:11 +01:00
# ifdef C O N F I G _ C P U _ P J 4 B
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.type _ _ v7 _ p j 4 b _ p r o c _ i n f o , #o b j e c t
__v7_pj4b_proc_info :
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.long 0x560f5800
.long 0xff0fff00
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_ _ v7 _ p r o c _ _ v7 _ p j 4 b _ p r o c _ i n f o , _ _ v7 _ p j 4 b _ s e t u p , p r o c _ f n s = p j 4 b _ p r o c e s s o r _ f u n c t i o n s
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.size _ _ v7 _ p j 4 b _ p r o c _ i n f o , . - _ _ v7 _ p j 4 b _ p r o c _ i n f o
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# endif
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/ *
* ARM L t d . C o r t e x R 7 p r o c e s s o r .
* /
.type _ _ v7 _ c r7 m p _ p r o c _ i n f o , #o b j e c t
__v7_cr7mp_proc_info :
.long 0x410fc170
.long 0xff0ffff0
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_ _ v7 _ p r o c _ _ v7 _ c r7 m p _ p r o c _ i n f o , _ _ v7 _ c r7 m p _ s e t u p
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.size _ _ v7 _ c r7 m p _ p r o c _ i n f o , . - _ _ v7 _ c r7 m p _ p r o c _ i n f o
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/ *
* ARM L t d . C o r t e x A 7 p r o c e s s o r .
* /
.type _ _ v7 _ c a7 m p _ p r o c _ i n f o , #o b j e c t
__v7_ca7mp_proc_info :
.long 0x410fc070
.long 0xff0ffff0
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_ _ v7 _ p r o c _ _ v7 _ c a7 m p _ p r o c _ i n f o , _ _ v7 _ c a7 m p _ s e t u p
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.size _ _ v7 _ c a7 m p _ p r o c _ i n f o , . - _ _ v7 _ c a7 m p _ p r o c _ i n f o
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/ *
* ARM L t d . C o r t e x A 1 2 p r o c e s s o r .
* /
.type _ _ v7 _ c a12 m p _ p r o c _ i n f o , #o b j e c t
__v7_ca12mp_proc_info :
.long 0x410fc0d0
.long 0xff0ffff0
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_ _ v7 _ p r o c _ _ v7 _ c a12 m p _ p r o c _ i n f o , _ _ v7 _ c a12 m p _ s e t u p
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.size _ _ v7 _ c a12 m p _ p r o c _ i n f o , . - _ _ v7 _ c a12 m p _ p r o c _ i n f o
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/ *
* ARM L t d . C o r t e x A 1 5 p r o c e s s o r .
* /
.type _ _ v7 _ c a15 m p _ p r o c _ i n f o , #o b j e c t
__v7_ca15mp_proc_info :
.long 0x410fc0f0
.long 0xff0ffff0
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_ _ v7 _ p r o c _ _ v7 _ c a15 m p _ p r o c _ i n f o , _ _ v7 _ c a15 m p _ s e t u p
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.size _ _ v7 _ c a15 m p _ p r o c _ i n f o , . - _ _ v7 _ c a15 m p _ p r o c _ i n f o
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/ *
* Broadcom C o r p o r a t i o n B r a h m a - B 1 5 p r o c e s s o r .
* /
.type _ _ v7 _ b15 m p _ p r o c _ i n f o , #o b j e c t
__v7_b15mp_proc_info :
.long 0x420f00f0
.long 0xff0ffff0
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_ _ v7 _ p r o c _ _ v7 _ b15 m p _ p r o c _ i n f o , _ _ v7 _ b15 m p _ s e t u p
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.size _ _ v7 _ b15 m p _ p r o c _ i n f o , . - _ _ v7 _ b15 m p _ p r o c _ i n f o
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/ *
* ARM L t d . C o r t e x A 1 7 p r o c e s s o r .
* /
.type _ _ v7 _ c a17 m p _ p r o c _ i n f o , #o b j e c t
__v7_ca17mp_proc_info :
.long 0x410fc0e0
.long 0xff0ffff0
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_ _ v7 _ p r o c _ _ v7 _ c a17 m p _ p r o c _ i n f o , _ _ v7 _ c a17 m p _ s e t u p
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.size _ _ v7 _ c a17 m p _ p r o c _ i n f o , . - _ _ v7 _ c a17 m p _ p r o c _ i n f o
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/ *
* Qualcomm I n c . K r a i t p r o c e s s o r s .
* /
.type _ _ krait_ p r o c _ i n f o , #o b j e c t
__krait_proc_info :
.long 0x510f0400 @ Required ID value
.long 0xff0ffc00 @ Mask for ID
/ *
* Some K r a i t p r o c e s s o r s d o n ' t i n d i c a t e s u p p o r t f o r S D I V a n d U D I V
* instructions i n t h e A R M i n s t r u c t i o n s e t , e v e n t h o u g h t h e y a c t u a l l y
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* do s u p p o r t t h e m . T h e y a l s o d o n ' t i n d i c a t e s u p p o r t f o r f u s e d m u l t i p l y
* instructions e v e n t h o u g h t h e y a c t u a l l y d o s u p p o r t t h e m .
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* /
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_ _ v7 _ p r o c _ _ k r a i t _ p r o c _ i n f o , _ _ v7 _ s e t u p , h w c a p s = H W C A P _ I D I V | H W C A P _ V F P v4
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.size _ _ krait_ p r o c _ i n f o , . - _ _ k r a i t _ p r o c _ i n f o
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/ *
* Match a n y A R M v7 p r o c e s s o r c o r e .
* /
.type _ _ v7 _ p r o c _ i n f o , #o b j e c t
__v7_proc_info :
.long 0x000f0000 @ Required ID value
.long 0x000f0000 @ Mask for ID
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_ _ v7 _ p r o c _ _ v7 _ p r o c _ i n f o , _ _ v7 _ s e t u p
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.size _ _ v7 _ p r o c _ i n f o , . - _ _ v7 _ p r o c _ i n f o
