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linux/arch/sh/include/cpu-sh4/cpu/mmu_context.h

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Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 15:20:36 -07:00
/*
* include/asm-sh/cpu-sh4/mmu_context.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
#define __ASM_CPU_SH4_MMU_CONTEXT_H
#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
#define MMU_TTB 0xFF000008 /* Translation table base register */
#define MMU_TEA 0xFF00000C /* TLB Exception Address */
sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores. This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-17 17:49:49 +09:00
#define MMU_PTEA 0xFF000034 /* PTE assistance register */
#define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 15:20:36 -07:00
#define MMUCR 0xFF000010 /* MMU Control Register */
sh: tlb debugfs support. Export the status of the utlb and itlb entries through debugfs. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-03-29 15:24:54 +09:00
#define MMU_TLB_ENTRY_SHIFT 8
sh: Flush ITLB too in PTEAEX's flush_tlb_page() flush_tlb_page() can be used to flush TLB entries that map executable pages. Therefore, we need to ensure that the ITLB is also flushed in local_flush_tlb_page(). Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-03-21 19:51:43 +00:00
#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
#define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
sh: tlb debugfs support. Export the status of the utlb and itlb entries through debugfs. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-03-29 15:24:54 +09:00
#define MMU_ITLB_DATA_ARRAY 0xF3000000
#define MMU_ITLB_DATA_ARRAY2 0xF3800000
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 15:20:36 -07:00
#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores. This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-17 17:49:49 +09:00
#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
sh: tlb debugfs support. Export the status of the utlb and itlb entries through debugfs. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-03-29 15:24:54 +09:00
#define MMU_UTLB_DATA_ARRAY 0xF7000000
#define MMU_UTLB_DATA_ARRAY2 0xF7800000
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 15:20:36 -07:00
#define MMU_PAGE_ASSOC_BIT 0x80
sh: Disable MMUCR_AT for SH-4 nommu. Presently address translation is default-enabled regardless of whether CONFIG_MMU is set or not in the SH-4 case, this fixes it up, and also makes the control init word a bit more readable in the process. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-07 17:08:32 +09:00
#ifdef CONFIG_MMU
#define MMUCR_AT (1 << 0)
#else
#define MMUCR_AT (0)
#endif
#define MMUCR_TI (1 << 2)
sh: Invalidate the TLB after applying PMB mappings. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-11-26 21:32:40 +09:00
sh: New extended page flag to wire/unwire TLB entries Provide a new extended page flag, _PAGE_WIRED and an SH4 implementation for wiring TLB entries and use it in the fixmap code path so that we can wire the fixmap TLB entry. Signed-off-by: Matt Fleming <matt@console-pimps.org>
2009-11-17 21:05:31 +00:00
#define MMUCR_URB 0x00FC0000
#define MMUCR_URB_SHIFT 18
#define MMUCR_URB_NENTRIES 64
sh: update the TLB replacement counter for entry wiring. Presently the TLB wiring code depends on MMUCR.URB for working out where to place the wired entry, but fails to take the replacment counter in to consideration. This fixes up the wiring logic and ensures that wired entries remain so. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-03-26 11:37:16 +09:00
#define MMUCR_URC 0x0000FC00
#define MMUCR_URC_SHIFT 10
sh: New extended page flag to wire/unwire TLB entries Provide a new extended page flag, _PAGE_WIRED and an SH4 implementation for wiring TLB entries and use it in the fixmap code path so that we can wire the fixmap TLB entry. Signed-off-by: Matt Fleming <matt@console-pimps.org>
2009-11-17 21:05:31 +00:00
sh: Clean up places that make 29-bit physical assumptions. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-11-30 17:52:53 +09:00
#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
#define MMUCR_SE (1 << 4)
#else
#define MMUCR_SE (0)
#endif
sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores. This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-17 17:49:49 +09:00
#ifdef CONFIG_CPU_HAS_PTEAEX
#define MMUCR_AEX (1 << 6)
#else
#define MMUCR_AEX (0)
#endif
#ifdef CONFIG_X2TLB
#define MMUCR_ME (1 << 7)
#else
#define MMUCR_ME (0)
#endif
[PATCH] sh: Move TRA/EXPEVT/INTEVT definitions for reuse Currently entry.S is home to these definitions, so we move them somewhere more sensible. IPR IRQ handling depends on being to read from INTEVT. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-01 03:06:01 -08:00
#ifdef CONFIG_SH_STORE_QUEUES
sh: Fix up extended mode TLB for SH-X2+ cores. The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot, correspondingly, the PGD also has to be 64-bits, so fix that up. The kernel and user permission bits really are decoupled in early cuts of the silicon, which means that we also have to set corresponding kernel permissions on user pages or we end up with user pages that the kernel simply can't touch (!). Finally, with those things corrected, really enable MMUCR.ME and correct the PTEA value (this simply needs to be the upper 32-bits of the PTE, with the size and protection bit encoding). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:55:03 +09:00
#define MMUCR_SQMD (1 << 9)
[PATCH] sh: Move TRA/EXPEVT/INTEVT definitions for reuse Currently entry.S is home to these definitions, so we move them somewhere more sensible. IPR IRQ handling depends on being to read from INTEVT. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-01 03:06:01 -08:00
#else
sh: Fix up extended mode TLB for SH-X2+ cores. The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot, correspondingly, the PGD also has to be 64-bits, so fix that up. The kernel and user permission bits really are decoupled in early cuts of the silicon, which means that we also have to set corresponding kernel permissions on user pages or we end up with user pages that the kernel simply can't touch (!). Finally, with those things corrected, really enable MMUCR.ME and correct the PTEA value (this simply needs to be the upper 32-bits of the PTE, with the size and protection bit encoding). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:55:03 +09:00
#define MMUCR_SQMD (0)
[PATCH] sh: Move TRA/EXPEVT/INTEVT definitions for reuse Currently entry.S is home to these definitions, so we move them somewhere more sensible. IPR IRQ handling depends on being to read from INTEVT. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-01 03:06:01 -08:00
#endif
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 15:20:36 -07:00
sh: Fix up extended mode TLB for SH-X2+ cores. The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot, correspondingly, the PGD also has to be 64-bits, so fix that up. The kernel and user permission bits really are decoupled in early cuts of the silicon, which means that we also have to set corresponding kernel permissions on user pages or we end up with user pages that the kernel simply can't touch (!). Finally, with those things corrected, really enable MMUCR.ME and correct the PTEA value (this simply needs to be the upper 32-bits of the PTE, with the size and protection bit encoding). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:55:03 +09:00
#define MMU_NTLB_ENTRIES 64
sh: Disable MMUCR_AT for SH-4 nommu. Presently address translation is default-enabled regardless of whether CONFIG_MMU is set or not in the SH-4 case, this fixes it up, and also makes the control init word a bit more readable in the process. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-07 17:08:32 +09:00
#define MMU_CONTROL_INIT (MMUCR_AT | MMUCR_TI | MMUCR_SQMD | \
MMUCR_ME | MMUCR_SE | MMUCR_AEX)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 15:20:36 -07:00
[PATCH] sh: Move TRA/EXPEVT/INTEVT definitions for reuse Currently entry.S is home to these definitions, so we move them somewhere more sensible. IPR IRQ handling depends on being to read from INTEVT. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-01 03:06:01 -08:00
#define TRA 0xff000020
#define EXPEVT 0xff000024
#define INTEVT 0xff000028
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 15:20:36 -07:00
#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
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