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linux/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml

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dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 18:19:17 +01:00
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 USB HS PHY controller binding
description:
The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
switch. It controls PHY configuration and status, and the UTMI+ switch that
selects either OTG or HOST controller for the second PHY port. It also sets
PLL configuration.
USBPHYC
|_ PLL
|
|_ PHY port#1 _________________ HOST controller
| __ |
| / 1|________________|
|_ PHY port#2 ----| |________________
| \_0| |
|_ UTMI switch_______| OTG controller
maintainers:
dt-bindings: treewide: Update @st.com email address to @foss.st.com Not all @st.com email address are concerned, only people who have a specific @foss.st.com email will see their entry updated. For some people, who left the company, remove their email. Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Cc: Fabien Dessenne <fabien.dessenne@foss.st.com> Cc: Christophe Roullier <christophe.roullier@foss.st.com> Cc: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Cc: Lionel Debieve <lionel.debieve@foss.st.com> Cc: Amelie Delaunay <amelie.delaunay@foss.st.com> Cc: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com> Cc: Ludovic Barre <ludovic.barre@foss.st.com> Cc: Christophe Kerello <christophe.kerello@foss.st.com> Cc: pascal Paillet <p.paillet@foss.st.com> Cc: Erwan Le Ray <erwan.leray@foss.st.com> Cc: Philippe CORNU <philippe.cornu@foss.st.com> Cc: Yannick Fertre <yannick.fertre@foss.st.com> Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Cc: Olivier Moysan <olivier.moysan@foss.st.com> Cc: Hugues Fruchet <hugues.fruchet@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-By: Vinod Koul <vkoul@kernel.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20211110150144.18272-6-patrice.chotard@foss.st.com Signed-off-by: Rob Herring <robh@kernel.org>
2021-11-10 16:01:44 +01:00
- Amelie Delaunay <amelie.delaunay@foss.st.com>
dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 18:19:17 +01:00
properties:
compatible:
const: st,stm32mp1-usbphyc
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE signal. Currently, supplies are managed through phy_ops .power_on/off, and PLL activation/deactivation is managed through phy_ops .init/exit. The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB drivers dependent. To ensure a good behavior of the PLL, supplies have to be managed at PLL activation/deactivation. That means the supplies need to be put in usbphyc parent node and not in phy children nodes. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210105090525.23164-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-05 10:05:20 +01:00
vdda1v1-supply:
description: regulator providing 1V1 power supply to the PLL block
vdda1v8-supply:
description: regulator providing 1V8 power supply to the PLL block
dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property usbphyc provides a unique clock called ck_usbo_48m. STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation. ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210208114659.15269-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-08 12:46:58 +01:00
'#clock-cells':
description: number of clock cells for ck_usbo_48m consumer
const: 0
dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 18:19:17 +01:00
#Required child nodes:
patternProperties:
"^usb-phy@[0|1]$":
type: object
description:
Each port the controller provides must be represented as a sub-node.
properties:
reg:
description: phy port index.
maxItems: 1
phy-supply:
description: regulator providing 3V3 power supply to the PHY.
"#phy-cells":
enum: [ 0x0, 0x1 ]
dt-bindings: phy: add vbus-supply optional property to phy-stm32-usbphyc This patch adds vbus-supply optional property to phy sub-nodes using connector node. A regulator for USB VBUS may be needed for host mode. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210517120821.26466-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-17 14:08:20 +02:00
connector:
type: object
allOf:
- $ref: ../connector/usb-connector.yaml
properties:
vbus-supply: true
dt-bindings: phy: phy-stm32-usbphyc: add optional phy tuning properties This patch adds the description of new optional phy tuning properties for usbphyc phy sub nodes. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211015161427.220784-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-15 18:14:26 +02:00
# It can be necessary to adjust the PHY settings to compensate parasitics, which can be due
# to USB connector/receptacle, routing, ESD protection component,... Here is the list of
# all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full-
# Speed, LS for Low-Speed)
st,current-boost-microamp:
description: Current boosting in uA
enum: [ 1000, 2000 ]
st,no-lsfs-fb-cap:
description: Disables the LS/FS feedback capacitor
type: boolean
st,decrease-hs-slew-rate:
description: Decreases the HS driver slew rate by 10%
type: boolean
st,tune-hs-dc-level:
description: |
Tunes the HS driver DC level
- <0> normal level
- <1> increases the level by 5 to 7 mV
- <2> increases the level by 10 to 14 mV
- <3> decreases the level by 5 to 7 mV
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
default: 0
st,enable-fs-rftime-tuning:
description: Enables the FS rise/fall tuning option
type: boolean
st,enable-hs-rftime-reduction:
description: Enables the HS rise/fall reduction feature
type: boolean
st,trim-hs-current:
description: |
Controls HS driver current trimming for choke compensation
- <0> = 18.87 mA target current / nominal + 0%
- <1> = 19.165 mA target current / nominal + 1.56%
- <2> = 19.46 mA target current / nominal + 3.12%
- <3> = 19.755 mA target current / nominal + 4.68%
- <4> = 20.05 mA target current / nominal + 6.24%
- <5> = 20.345 mA target current / nominal + 7.8%
- <6> = 20.64 mA target current / nominal + 9.36%
- <7> = 20.935 mA target current / nominal + 10.92%
- <8> = 21.23 mA target current / nominal + 12.48%
- <9> = 21.525 mA target current / nominal + 14.04%
- <10> = 21.82 mA target current / nominal + 15.6%
- <11> = 22.115 mA target current / nominal + 17.16%
- <12> = 22.458 mA target current / nominal + 19.01%
- <13> = 22.755 mA target current / nominal + 20.58%
- <14> = 23.052 mA target current / nominal + 22.16%
- <15> = 23.348 mA target current / nominal + 23.73%
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
default: 0
st,trim-hs-impedance:
description: |
Controls HS driver impedance tuning for choke compensation
- <0> = no impedance offset
- <1> = reduce the impedance by 2 ohms
- <2> = reduce the impedance by 4 ohms
- <3> = reduce the impedance by 6 ohms
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
default: 0
st,tune-squelch-level:
description: |
Tunes the squelch DC threshold value
- <0> = no shift in threshold
- <1> = threshold shift by +7 mV
- <2> = threshold shift by -5 mV
- <3> = threshold shift by +14 mV
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
default: 0
st,enable-hs-rx-gain-eq:
description: Enables the HS Rx gain equalizer
type: boolean
st,tune-hs-rx-offset:
description: |
Adjusts the HS Rx offset
- <0> = no offset
- <1> = offset of +5 mV
- <2> = offset of +10 mV
- <3> = offset of -5 mV
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
default: 0
st,no-hs-ftime-ctrl:
description: Disables the HS fall time control of single ended signals during pre-emphasis
type: boolean
st,no-lsfs-sc:
description: Disables the short circuit protection in LS/FS driver
type: boolean
st,enable-hs-tx-staggering:
description: Enables the basic staggering in HS Tx mode
type: boolean
dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 18:19:17 +01:00
allOf:
- if:
properties:
reg:
const: 0
then:
properties:
"#phy-cells":
const: 0
else:
properties:
"#phy-cells":
const: 1
description:
The value is used to select UTMI switch output.
0 for OTG controller and 1 for Host controller.
required:
- reg
- phy-supply
- "#phy-cells"
additionalProperties: false
required:
- compatible
- reg
- clocks
- "#address-cells"
- "#size-cells"
dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE signal. Currently, supplies are managed through phy_ops .power_on/off, and PLL activation/deactivation is managed through phy_ops .init/exit. The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB drivers dependent. To ensure a good behavior of the PLL, supplies have to be managed at PLL activation/deactivation. That means the supplies need to be put in usbphyc parent node and not in phy children nodes. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210105090525.23164-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-05 10:05:20 +01:00
- vdda1v1-supply
- vdda1v8-supply
dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 18:19:17 +01:00
- usb-phy@0
- usb-phy@1
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
usbphyc: usbphyc@5a006000 {
compatible = "st,stm32mp1-usbphyc";
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
resets = <&rcc USBPHY_R>;
dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE signal. Currently, supplies are managed through phy_ops .power_on/off, and PLL activation/deactivation is managed through phy_ops .init/exit. The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB drivers dependent. To ensure a good behavior of the PLL, supplies have to be managed at PLL activation/deactivation. That means the supplies need to be put in usbphyc parent node and not in phy children nodes. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210105090525.23164-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-05 10:05:20 +01:00
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 18:19:17 +01:00
#address-cells = <1>;
#size-cells = <0>;
dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property usbphyc provides a unique clock called ck_usbo_48m. STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation. ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210208114659.15269-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-08 12:46:58 +01:00
#clock-cells = <0>;
dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 18:19:17 +01:00
usbphyc_port0: usb-phy@0 {
reg = <0>;
phy-supply = <&vdd_usb>;
#phy-cells = <0>;
dt-bindings: phy: phy-stm32-usbphyc: add optional phy tuning properties This patch adds the description of new optional phy tuning properties for usbphyc phy sub nodes. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211015161427.220784-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-15 18:14:26 +02:00
st,tune-hs-dc-level = <2>;
st,enable-fs-rftime-tuning;
st,enable-hs-rftime-reduction;
st,trim-hs-current = <15>;
st,trim-hs-impedance = <1>;
st,tune-squelch-level = <3>;
st,tune-hs-rx-offset = <2>;
st,no-lsfs-sc;
dt-bindings: phy: add vbus-supply optional property to phy-stm32-usbphyc This patch adds vbus-supply optional property to phy sub-nodes using connector node. A regulator for USB VBUS may be needed for host mode. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210517120821.26466-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-17 14:08:20 +02:00
connector {
compatible = "usb-a-connector";
vbus-supply = <&vbus_sw>;
};
dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 18:19:17 +01:00
};
usbphyc_port1: usb-phy@1 {
reg = <1>;
phy-supply = <&vdd_usb>;
#phy-cells = <1>;
dt-bindings: phy: phy-stm32-usbphyc: add optional phy tuning properties This patch adds the description of new optional phy tuning properties for usbphyc phy sub nodes. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211015161427.220784-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-15 18:14:26 +02:00
st,tune-hs-dc-level = <2>;
st,enable-fs-rftime-tuning;
st,enable-hs-rftime-reduction;
st,trim-hs-current = <15>;
st,trim-hs-impedance = <1>;
st,tune-squelch-level = <3>;
st,tune-hs-rx-offset = <2>;
st,no-lsfs-sc;
dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 18:19:17 +01:00
};
};
...
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