2011-07-10 05:14:07 +04:00
/*
* omap_hwmod_2xxx_3xxx_ipblock_data . c - common IP block data for OMAP2 / 3
*
* Copyright ( C ) 2011 Nokia Corporation
2012-05-08 21:34:27 +04:00
* Copyright ( C ) 2012 Texas Instruments , Inc .
2011-07-10 05:14:07 +04:00
* Paul Walmsley
*
* This program is free software ; you can redistribute it and / or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation .
*/
2012-10-03 04:41:35 +04:00
2012-11-30 20:41:50 +04:00
# include <linux/dmaengine.h>
# include <linux/omap-dma.h>
2012-10-03 04:41:35 +04:00
# include "omap_hwmod.h"
2012-09-20 22:41:48 +04:00
# include "hdq1w.h"
2011-07-10 05:14:07 +04:00
# include "omap_hwmod_common_data.h"
2011-07-10 05:14:08 +04:00
/* UART */
static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
. rev_offs = 0x50 ,
. sysc_offs = 0x54 ,
. syss_offs = 0x58 ,
. sysc_flags = ( SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS ) ,
. idlemodes = ( SIDLE_FORCE | SIDLE_NO | SIDLE_SMART ) ,
. sysc_fields = & omap_hwmod_sysc_type1 ,
} ;
struct omap_hwmod_class omap2_uart_class = {
. name = " uart " ,
. sysc = & omap2_uart_sysc ,
} ;
/*
* ' venc ' class
* video encoder
*/
struct omap_hwmod_class omap2_venc_hwmod_class = {
. name = " venc " ,
} ;
2011-07-10 05:14:07 +04:00
/*
* omap_hwmod class data
*/
struct omap_hwmod_class l3_hwmod_class = {
2016-10-21 13:02:12 +03:00
. name = " l3 " ,
2011-07-10 05:14:07 +04:00
} ;
struct omap_hwmod_class l4_hwmod_class = {
2016-10-21 13:02:12 +03:00
. name = " l4 " ,
2011-07-10 05:14:07 +04:00
} ;
struct omap_hwmod_class mpu_hwmod_class = {
2016-10-21 13:02:12 +03:00
. name = " mpu " ,
2011-07-10 05:14:07 +04:00
} ;
struct omap_hwmod_class iva_hwmod_class = {
2016-10-21 13:02:12 +03:00
. name = " iva " ,
2011-07-10 05:14:07 +04:00
} ;
/* Common MPU IRQ line data */
2011-07-10 05:14:07 +04:00
struct omap_hwmod_irq_info omap2_dispc_irqs [ ] = {
2012-08-28 04:43:01 +04:00
{ . irq = 25 + OMAP_INTC_START , } ,
2016-10-21 13:02:12 +03:00
{ . irq = - 1 , } ,
2011-07-10 05:14:07 +04:00
} ;
struct omap_hwmod_irq_info omap2_dma_system_irqs [ ] = {
2012-08-28 04:43:01 +04:00
{ . name = " 0 " , . irq = 12 + OMAP_INTC_START , } , /* INT_24XX_SDMA_IRQ0 */
{ . name = " 1 " , . irq = 13 + OMAP_INTC_START , } , /* INT_24XX_SDMA_IRQ1 */
{ . name = " 2 " , . irq = 14 + OMAP_INTC_START , } , /* INT_24XX_SDMA_IRQ2 */
{ . name = " 3 " , . irq = 15 + OMAP_INTC_START , } , /* INT_24XX_SDMA_IRQ3 */
2016-10-21 13:02:12 +03:00
{ . irq = - 1 , } ,
2011-07-10 05:14:07 +04:00
} ;
2012-05-08 21:34:27 +04:00
struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
. rev_offs = 0x0 ,
. sysc_offs = 0x14 ,
. syss_offs = 0x18 ,
. sysc_flags = ( SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS ) ,
. sysc_fields = & omap_hwmod_sysc_type1 ,
} ;
struct omap_hwmod_class omap2_hdq1w_class = {
. name = " hdq1w " ,
. sysc = & omap2_hdq1w_sysc ,
. reset = & omap_hdq1w_reset ,
} ;