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linux/drivers/clk/mediatek/clk-mt8135.c

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-27 08:55:21 +02:00
// SPDX-License-Identifier: GPL-2.0-only
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
clk: mediatek: Properly include clk.h We don't need to include clk.h in header files, just forward declare struct clk here. This leads us to a few places where the include of clk.h was missing in C files. Add them. Cc: James Liao <jamesjj.liao@mediatek.com> Cc: Henry Chen <henryc.chen@mediatek.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-19 15:00:46 -07:00
#include <linux/clk.h>
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
#include <linux/module.h>
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
#include <linux/of.h>
#include <linux/of_address.h>
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
#include <linux/platform_device.h>
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <dt-bindings/clock/mt8135-clk.h>
#include "clk-gate.h"
clk: mediatek: pll: Split definitions into separate header file When the PLL type clk was implemented in the MediaTek clk driver library, the data structure definitions and function declaration were put in the common header file. Since it is its own type of clk, and not all platform clk drivers utilize it, having the definitions in the common header results in wasted cycles during compilation. Split out the related definitions and declarations into its own header file, and include that only in the platform clk drivers that need it. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220208124034.414635-13-wenst@chromium.org Reviewed-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-02-08 20:40:15 +08:00
#include "clk-mtk.h"
#include "clk-pll.h"
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
static DEFINE_SPINLOCK(mt8135_clk_lock);
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_DUMMY, "top_divs_dummy", "clk_null", 1, 1),
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const axi_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"syspll_d3",
"syspll_d4",
"syspll_d6",
"univpll_d5",
"univpll2_d2",
"syspll_d3p5"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const smi_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"clkph_mck",
"syspll_d2p5",
"syspll_d3",
"syspll_d8",
"univpll_d5",
"univpll1_d2",
"univpll1_d6",
"mmpll_d3",
"mmpll_d4",
"mmpll_d5",
"mmpll_d6",
"mmpll_d7",
"vdecpll",
"lvdspll"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const mfg_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"univpll1_d4",
"syspll_d2",
"syspll_d2p5",
"syspll_d3",
"univpll_d5",
"univpll1_d2",
"mmpll_d2",
"mmpll_d3",
"mmpll_d4",
"mmpll_d5",
"mmpll_d6",
"mmpll_d7"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const irda_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"univpll2_d8",
"univpll1_d6"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const cam_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"syspll_d3",
"syspll_d3p5",
"syspll_d4",
"univpll_d5",
"univpll2_d2",
"univpll_d7",
"univpll1_d4"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const aud_intbus_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"syspll_d6",
"univpll_d10"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const jpg_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"syspll_d5",
"syspll_d4",
"syspll_d3",
"univpll_d7",
"univpll2_d2",
"univpll_d5"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const disp_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"syspll_d3p5",
"syspll_d3",
"univpll2_d2",
"univpll_d5",
"univpll1_d2",
"lvdspll",
"vdecpll"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const msdc30_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"syspll_d6",
"syspll_d5",
"univpll1_d4",
"univpll2_d4",
"msdcpll"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const usb20_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"univpll2_d6",
"univpll1_d10"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const venc_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"syspll_d3",
"syspll_d8",
"univpll_d5",
"univpll1_d6",
"mmpll_d4",
"mmpll_d5",
"mmpll_d6"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const spi_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"syspll_d6",
"syspll_d8",
"syspll_d10",
"univpll1_d6",
"univpll1_d8"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const uart_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"univpll2_d8"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const mem_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"clkph_mck"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const camtg_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"univpll_d26",
"univpll1_d6",
"syspll_d16",
"syspll_d8"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const audio_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"syspll_d24"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const fix_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"rtc32k",
"clk26m",
"univpll_d5",
"univpll_d7",
"univpll1_d2",
"univpll1_d4",
"univpll1_d6",
"univpll1_d8"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const vdec_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"vdecpll",
"clkph_mck",
"syspll_d2p5",
"syspll_d3",
"syspll_d3p5",
"syspll_d4",
"syspll_d5",
"syspll_d6",
"syspll_d8",
"univpll1_d2",
"univpll2_d2",
"univpll_d7",
"univpll_d10",
"univpll2_d4",
"lvdspll"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const ddrphycfg_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"axi_sel",
"syspll_d12"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const dpilvds_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"lvdspll",
"lvdspll_d2",
"lvdspll_d4",
"lvdspll_d8"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const pmicspi_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"univpll2_d6",
"syspll_d8",
"syspll_d10",
"univpll1_d10",
"mempll_mck_d4",
"univpll_d26",
"syspll_d24"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const smi_mfg_as_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"smi_sel",
"mfg_sel",
"mem_sel"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const gcpu_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"syspll_d4",
"univpll_d7",
"syspll_d5",
"syspll_d6"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const dpi1_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"tvhdmi_h_ck",
"tvhdmi_d2",
"tvhdmi_d4"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const cci_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"mainpll_537p3m",
"univpll_d3",
"syspll_d2p5",
"syspll_d3",
"syspll_d5"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const apll_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"apll_ck",
"apll_d4",
"apll_d8",
"apll_d16",
"apll_d24"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const hdmipll_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"hdmitx_clkdig_cts",
"hdmitx_clkdig_d2",
"hdmitx_clkdig_d3"
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const struct mtk_composite top_muxes[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
/* CLK_CFG_0 */
MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0x0140, 0, 3, INVALID_MUX_GATE_BIT),
MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
/* CLK_CFG_1 */
MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0x0144, 8, 2, 15),
MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
/* CLK_CFG_2 */
MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
/* CLK_CFG_3 */
MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
/* CLK_CFG_4 */
MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
/* CLK_CFG_6 */
MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
/* CLK_CFG_7 */
MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
0x015c, 16, 2, 23),
MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
/* CLK_CFG_8 */
MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
0x0164, 16, 2, 23),
MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
/* CLK_CFG_9 */
MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
clk: mediatek: mt8135: Properly use CLK_IS_CRITICAL flag Instead of calling clk_prepare_enable() for clocks that shall stay enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that. Fixes: a8aede794843 ("clk: mediatek: Add basic clocks for Mediatek MT8135.") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-52-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:40 +01:00
MUX_GATE_FLAGS(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15, CLK_IS_CRITICAL),
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
};
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x0040,
.clr_ofs = 0x0044,
.sta_ofs = 0x0048,
};
clk: mediatek: Consistently use GATE_MTK() macro All the various MediaTek clock drivers are, in a way or another, redefining the GATE_MTK() macro with different names: while some are doing that by actually using GATE_MTK(), others are copying it entirely (hence, entirely redefining it). Change all clock drivers to always and consistently use this macro. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-23-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:11 +01:00
#define GATE_ICG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
clk: mediatek: mt8135: Properly use CLK_IS_CRITICAL flag Instead of calling clk_prepare_enable() for clocks that shall stay enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that. Fixes: a8aede794843 ("clk: mediatek: Add basic clocks for Mediatek MT8135.") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-52-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:40 +01:00
#define GATE_ICG_AO(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL)
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const struct mtk_gate infra_clks[] = {
GATE_DUMMY(CLK_DUMMY, "infra_dummy"),
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
clk: mediatek: mt8135: Properly use CLK_IS_CRITICAL flag Instead of calling clk_prepare_enable() for clocks that shall stay enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that. Fixes: a8aede794843 ("clk: mediatek: Add basic clocks for Mediatek MT8135.") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-52-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:40 +01:00
GATE_ICG_AO(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
};
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x0010,
.sta_ofs = 0x0018,
};
static const struct mtk_gate_regs peri1_cg_regs = {
.set_ofs = 0x000c,
.clr_ofs = 0x0014,
.sta_ofs = 0x001c,
};
clk: mediatek: Consistently use GATE_MTK() macro All the various MediaTek clock drivers are, in a way or another, redefining the GATE_MTK() macro with different names: while some are doing that by actually using GATE_MTK(), others are copying it entirely (hence, entirely redefining it). Change all clock drivers to always and consistently use this macro. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-23-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:11 +01:00
#define GATE_PERI0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_PERI1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const struct mtk_gate peri_gates[] = {
GATE_DUMMY(CLK_DUMMY, "peri_dummy"),
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
/* PERI0 */
GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
/* PERI1 */
GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const char * const uart_ck_sel_parents[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
"clk26m",
"uart_sel",
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const struct mtk_composite peri_clks[] = {
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
};
clk: mediatek: reset: Support nonsequence base offsets of reset registers The bank offsets are not serial for all reset registers. For example, there are five infra reset banks for MT8192: 0x120, 0x130, 0x140, 0x150 and 0x730. To support this, - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of the reset register. - Add a new define RST_NR_PER_BANK to define reset number for each reset bank. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-23 17:33:34 +08:00
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
clk: mediatek: reset: Revise structure to control reset register To declare the reset data easier, we add a strucure to do this instead of using many input variables to mtk_register_reset_controller(). - Add mtk_clk_rst_desc to define the reset description when registering the reset controller. - Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store data of reset controller. - Document mtk_clk_rst_desc and mtk_clk_rst_data. - Modify the documentation of mtk_register_reset_controller. - Extract container_of in update functions to to_mtk_clk_rst_data(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-7-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-23 17:33:33 +08:00
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
/* infrasys */
{
.version = MTK_RST_SIMPLE,
clk: mediatek: reset: Support nonsequence base offsets of reset registers The bank offsets are not serial for all reset registers. For example, there are five infra reset banks for MT8192: 0x120, 0x130, 0x140, 0x150 and 0x730. To support this, - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of the reset register. - Add a new define RST_NR_PER_BANK to define reset number for each reset bank. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-23 17:33:34 +08:00
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
clk: mediatek: reset: Revise structure to control reset register To declare the reset data easier, we add a strucure to do this instead of using many input variables to mtk_register_reset_controller(). - Add mtk_clk_rst_desc to define the reset description when registering the reset controller. - Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store data of reset controller. - Document mtk_clk_rst_desc and mtk_clk_rst_data. - Modify the documentation of mtk_register_reset_controller. - Extract container_of in update functions to to_mtk_clk_rst_data(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-7-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-23 17:33:33 +08:00
},
/* pericfg */
{
.version = MTK_RST_SIMPLE,
clk: mediatek: reset: Support nonsequence base offsets of reset registers The bank offsets are not serial for all reset registers. For example, there are five infra reset banks for MT8192: 0x120, 0x130, 0x140, 0x150 and 0x730. To support this, - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of the reset register. - Add a new define RST_NR_PER_BANK to define reset number for each reset bank. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-23 17:33:34 +08:00
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
clk: mediatek: reset: Revise structure to control reset register To declare the reset data easier, we add a strucure to do this instead of using many input variables to mtk_register_reset_controller(). - Add mtk_clk_rst_desc to define the reset description when registering the reset controller. - Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store data of reset controller. - Document mtk_clk_rst_desc and mtk_clk_rst_data. - Modify the documentation of mtk_register_reset_controller. - Extract container_of in update functions to to_mtk_clk_rst_data(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-7-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-23 17:33:33 +08:00
}
};
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.rst_desc = &clk_rst_desc[0],
};
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const struct mtk_clk_desc peri_desc = {
.clks = peri_gates,
.num_clks = ARRAY_SIZE(peri_gates),
.composite_clks = peri_clks,
.num_composite_clks = ARRAY_SIZE(peri_clks),
.clk_lock = &mt8135_clk_lock,
.rst_desc = &clk_rst_desc[1],
};
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const struct mtk_clk_desc topck_desc = {
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.composite_clks = top_muxes,
.num_composite_clks = ARRAY_SIZE(top_muxes),
.clk_lock = &mt8135_clk_lock,
};
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static const struct of_device_id of_match_clk_mt8135[] = {
{ .compatible = "mediatek,mt8135-infracfg", .data = &infra_desc },
{ .compatible = "mediatek,mt8135-pericfg", .data = &peri_desc },
{ .compatible = "mediatek,mt8135-topckgen", .data = &topck_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8135);
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
static struct platform_driver clk_mt8135_drv = {
.driver = {
.name = "clk-mt8135",
.of_match_table = of_match_clk_mt8135,
},
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt8135_drv);
clk: mediatek: Add basic clocks for Mediatek MT8135. This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-23 10:35:41 +02:00
clk: mediatek: mt8135: Convert to simple probe and enable module build Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:43 +01:00
MODULE_DESCRIPTION("MediaTek MT8135 clocks driver");
clk: mediatek: Add MODULE_LICENSE() where missing In order to successfully build clock drivers as modules it is required to declare a module license: add it where missing. While at it, also change the MODULE_LICENSE text from "GPL v2" to "GPL" (which means the same) on clk-mt7981-eth.c. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-38-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-06 15:05:26 +01:00
MODULE_LICENSE("GPL");
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