blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
/ *
2009-09-24 18:11:24 +04:00
* Copyright 2 0 0 4 - 2 0 0 9 A n a l o g D e v i c e s I n c .
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
*
2009-09-24 18:11:24 +04:00
* Licensed u n d e r t h e A D I B S D l i c e n s e o r t h e G P L - 2 ( o r l a t e r )
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
* /
# include < l i n u x / l i n k a g e . h >
# define C A R R Y A C 0
# ifdef C O N F I G _ A R I T H M E T I C _ O P S _ L 1
.section .l1 .text
# else
.text
# endif
ENTRY( _ _ _ u d i v s i 3 )
CC = R 0 < R 1 ( I U ) ; /* If X < Y, always return 0 */
IF C C J U M P . L r e t u r n _ i d e n t ;
R2 = R 1 < < 1 6 ;
CC = R 2 < = R 0 ( I U ) ;
IF C C J U M P . L i d e n t s ;
R2 = R 0 > > 3 1 ; /* if X is a 31-bit number */
R3 = R 1 > > 1 5 ; /* and Y is a 15-bit number */
R2 = R 2 | R 3 ; /* then it's okay to use the DIVQ builtins (fallthrough to fast)*/
CC = R 2 ;
IF C C J U M P . L y _ 1 6 b i t ;
/ * METHOD 1 : F A S T D I V Q
We k n o w w e h a v e a 3 1 - b i t d i v i d e n d , a n d 1 5 - b i t d i v i s o r s o w e c a n u s e t h e
simple d i v q a p p r o a c h ( f i r s t s e t t i n g A Q t o 0 - i m p l y i n g u n s i g n e d d i v i s i o n ,
then 1 6 D I V Q ' s ) .
* /
AQ = C C ; /* Clear AQ (CC==0) */
/ * ISR S t a t e s : W h e n d i v i d i n g t w o i n t e g e r s ( 3 2 . 0 / 1 6 . 0 ) u s i n g d i v i d e p r i m i t i v e s ,
we n e e d t o s h i f t t h e d i v i d e n d o n e b i t t o t h e l e f t .
We h a v e a l r e a d y c h e c k e d t h a t w e h a v e a 3 1 - b i t n u m b e r s o w e a r e s a f e t o d o
that.
* /
R0 < < = 1 ;
DIVQ( R 0 , R 1 ) ; // 1
DIVQ( R 0 , R 1 ) ; // 2
DIVQ( R 0 , R 1 ) ; // 3
DIVQ( R 0 , R 1 ) ; // 4
DIVQ( R 0 , R 1 ) ; // 5
DIVQ( R 0 , R 1 ) ; // 6
DIVQ( R 0 , R 1 ) ; // 7
DIVQ( R 0 , R 1 ) ; // 8
DIVQ( R 0 , R 1 ) ; // 9
DIVQ( R 0 , R 1 ) ; // 10
DIVQ( R 0 , R 1 ) ; // 11
DIVQ( R 0 , R 1 ) ; // 12
DIVQ( R 0 , R 1 ) ; // 13
DIVQ( R 0 , R 1 ) ; // 14
DIVQ( R 0 , R 1 ) ; // 15
DIVQ( R 0 , R 1 ) ; // 16
R0 = R 0 . L ( Z ) ;
RTS;
.Ly_16bit :
/ * We k n o w t h a t t h e u p p e r 1 7 b i t s o f Y m i g h t h a v e b i t s s e t ,
* * or t h a t t h e s i g n b i t o f X m i g h t h a v e a b i t . I f Y i s a
* * 1 6 - bit n u m b e r , b u t n o t b i g g e r , t h e n w e c a n u s e t h e b u i l t i n s
* * with a p o s t - d i v i d e c o r r e c t i o n .
* * R3 c u r r e n t l y h o l d s Y > > 1 5 , w h i c h m e a n s R 3 ' s L S B i s t h e
* * bit w e ' r e i n t e r e s t e d i n .
* /
/ * According t o t h e I S R , t o u s e t h e D i v i d e p r i m i t i v e s f o r
* * unsigned i n t e g e r d i v i d e , t h e u s e a b l e r a n g e i s 3 1 b i t s
* /
CC = ! B I T T S T ( R 0 , 3 1 ) ;
/ * IF c o n d i t i o n i s t r u e w e c a n s c a l e o u r i n p u t s a n d u s e t h e d i v i d e p r i m i t i v e s ,
* * with s o m e p o s t - a d j u s t m e n t
* /
R3 + = - 1 ; /* if so, Y is 0x00008nnn */
CC & = A Z ;
/ * If c o n d i t i o n i s t r u e w e c a n s c a l e o u r i n p u t s a n d u s e t h e d i v i d e p r i m i t i v e s ,
* * with s o m e p o s t - a d j u s t m e n t
* /
R3 = R 1 > > 1 ; /* Pre-scaled divisor for primitive case */
R2 = R 0 > > 1 6 ;
R2 = R 3 - R 2 ; /* shifted divisor < upper 16 bits of dividend */
CC & = C A R R Y ;
IF C C J U M P . L s h i f t _ a n d _ c o r r e c t ;
/* Fall through to the identities */
/ * METHOD 2 : i d e n t i t i e s a n d m a n u a l c a l c u l a t i o n
We a r e n o t a b l e t o u s e t h e d i v i d e p r i m i t e s , b u t m a y s t i l l c a t c h s o m e s p e c i a l
cases.
* /
.Lidents :
/* Test for common identities. Value to be returned is placed in R2. */
CC = R 0 = = 0 ; /* 0/Y => 0 */
IF C C J U M P . L r e t u r n _ r0 ;
CC = R 0 = = R 1 ; /* X==Y => 1 */
IF C C J U M P . L r e t u r n _ i d e n t ;
CC = R 1 = = 1 ; /* X/1 => X */
IF C C J U M P . L r e t u r n _ i d e n t ;
R2 . L = O N E S R 1 ;
R2 = R 2 . L ( Z ) ;
CC = R 2 = = 1 ;
IF C C J U M P . L p o w e r _ o f _ t w o ;
[ - - SP] = ( R 7 : 5 ) ; /* Push registers R5-R7 */
/* Idents don't match. Go for the full operation. */
R6 = 2 ; /* assume we'll shift two */
R3 = 1 ;
P2 = R 1 ;
/* If either R0 or R1 have sign set, */
/* divide them by two, and note it's */
/* been done. */
CC = R 1 < 0 ;
R2 = R 1 > > 1 ;
IF C C R 1 = R 2 ; /* Possibly-shifted R1 */
IF ! C C R 6 = R 3 ; /* R1 doesn't, so at most 1 shifted */
P0 = 0 ;
R3 = - R 1 ;
[ - - SP] = R 3 ;
R2 = R 0 > > 1 ;
R2 = R 0 > > 1 ;
CC = R 0 < 0 ;
IF C C P 0 = R 6 ; /* Number of values divided */
IF ! C C R 2 = R 0 ; /* Shifted R0 */
/* P0 is 0, 1 (NR/=2) or 2 (NR/=2, DR/=2) */
/* r2 holds Copy dividend */
R3 = 0 ; /* Clear partial remainder */
R7 = 0 ; /* Initialise quotient bit */
P1 = 3 2 ; /* Set loop counter */
LSETUP( . L u l s t , . L u l e n d ) L C 0 = P 1 ; /* Set loop counter */
.Lulst : R6 = R 2 > > 3 1 ; /* R6 = sign bit of R2, for carry */
R2 = R 2 < < 1 ; /* Shift 64 bit dividend up by 1 bit */
R3 = R 3 < < 1 | | R 5 = [ S P ] ;
R3 = R 3 | R 6 ; /* Include any carry */
CC = R 7 < 0 ; /* Check quotient(AQ) */
/* If AQ==0, we'll sub divisor */
IF C C R 5 = R 1 ; /* and if AQ==1, we'll add it. */
R3 = R 3 + R 5 ; /* Add/sub divsor to partial remainder */
R7 = R 3 ^ R 1 ; /* Generate next quotient bit */
R5 = R 7 > > 3 1 ; /* Get AQ */
BITTGL( R 5 , 0 ) ; /* Invert it, to get what we'll shift */
.Lulend : R2 = R 2 + R 5 ; /* and "shift" it in. */
CC = P 0 = = 0 ; /* Check how many inputs we shifted */
IF C C J U M P . L n o _ m u l t ; /* if none... */
R6 = R 2 < < 1 ;
CC = P 0 = = 1 ;
IF C C R 2 = R 6 ; /* if 1, Q = Q*2 */
IF ! C C R 1 = P 2 ; /* if 2, restore stored divisor */
R3 = R 2 ; /* Copy of R2 */
R3 * = R 1 ; /* Q * divisor */
R5 = R 0 - R 3 ; /* Z = (dividend - Q * divisor) */
CC = R 1 < = R 5 ( I U ) ; /* Check if divisor <= Z? */
R6 = C C ; /* if yes, R6 = 1 */
R2 = R 2 + R 6 ; /* if yes, add one to quotient(Q) */
.Lno_mult :
SP + = 4 ;
( R7 : 5 ) = [ SP+ + ] ; /* Pop registers R5-R7 */
R0 = R 2 ; /* Store quotient */
RTS;
.Lreturn_ident :
CC = R 0 < R 1 ( I U ) ; /* If X < Y, always return 0 */
R2 = 0 ;
IF C C J U M P . L t r u e _ r e t u r n _ i d e n t ;
R2 = - 1 ( X ) ; /* X/0 => 0xFFFFFFFF */
CC = R 1 = = 0 ;
IF C C J U M P . L t r u e _ r e t u r n _ i d e n t ;
R2 = - R 2 ; /* R2 now 1 */
CC = R 0 = = R 1 ; /* X==Y => 1 */
IF C C J U M P . L t r u e _ r e t u r n _ i d e n t ;
R2 = R 0 ; /* X/1 => X */
/*FALLTHRU*/
.Ltrue_return_ident :
R0 = R 2 ;
.Lreturn_r0 :
RTS;
.Lpower_of_two :
/ * Y h a s a s i n g l e b i t s e t , w h i c h m e a n s i t ' s a p o w e r o f t w o .
* * That m e a n s w e c a n p e r f o r m t h e d i v i s i o n j u s t b y s h i f t i n g
* * X t o t h e r i g h t t h e a p p r o p r i a t e n u m b e r o f b i t s
* /
/ * signbits r e t u r n s t h e n u m b e r o f s i g n b i t s , m i n u s o n e .
* * 1 = > 3 0 , 2 = > 2 9 , . . . , 0 x4 0 0 0 0 0 0 0 = > 0 . W h i c h m e a n s w e n e e d
* * to s h i f t r i g h t n - s i g n b i t s s p a c e s . I t a l s o m e a n s 0 x80 0 0 0 0 0 0
* * is a s p e c i a l c a s e , b e c a u s e t h a t * a l s o * g i v e s a s i g n b i t s o f 0
* /
R2 = R 0 > > 3 1 ;
CC = R 1 < 0 ;
IF C C J U M P . L t r u e _ r e t u r n _ i d e n t ;
R1 . l = S I G N B I T S R 1 ;
R1 = R 1 . L ( Z ) ;
R1 + = - 3 0 ;
R0 = L S H I F T R 0 b y R 1 . L ;
RTS;
/ * METHOD 3 : P R E S C A L E A N D U S E T H E D I V I D E P R I M I T I V E S W I T H S O M E P O S T - C O R R E C T I O N
Two s c a l i n g o p e r a t i o n s a r e r e q u i r e d t o u s e t h e d i v i d e p r i m i t i v e s w i t h a
divisor > 0 x7 F F F F .
Firstly ( a s i n m e t h o d 1 ) w e n e e d t o s h i f t t h e d i v i d e n d 1 t o t h e l e f t f o r
integer d i v i s i o n .
Secondly w e n e e d t o s h i f t b o t h t h e d i v i s o r a n d d i v i d e n d 1 t o t h e r i g h t s o
both a r e i n r a n g e f o r t h e p r i m i t i v e s .
The l e f t / r i g h t s h i f t o f t h e d i v i d e n d d o e s n o t h i n g s o w e c a n s k i p i t .
* /
.Lshift_and_correct :
R2 = R 0 ;
/ / R3 i s a l r e a d y R 1 > > 1
CC= ! C C ;
AQ = C C ; /* Clear AQ, got here with CC = 0 */
DIVQ( R 2 , R 3 ) ; // 1
DIVQ( R 2 , R 3 ) ; // 2
DIVQ( R 2 , R 3 ) ; // 3
DIVQ( R 2 , R 3 ) ; // 4
DIVQ( R 2 , R 3 ) ; // 5
DIVQ( R 2 , R 3 ) ; // 6
DIVQ( R 2 , R 3 ) ; // 7
DIVQ( R 2 , R 3 ) ; // 8
DIVQ( R 2 , R 3 ) ; // 9
DIVQ( R 2 , R 3 ) ; // 10
DIVQ( R 2 , R 3 ) ; // 11
DIVQ( R 2 , R 3 ) ; // 12
DIVQ( R 2 , R 3 ) ; // 13
DIVQ( R 2 , R 3 ) ; // 14
DIVQ( R 2 , R 3 ) ; // 15
DIVQ( R 2 , R 3 ) ; // 16
/ * According t o t h e I n s t r u c t i o n S e t R e f e r e n c e :
To d i v i d e b y a d i v i s o r > 0 x7 F F F ,
1 . prescale a n d p e r f o r m d i v i d e t o o b t a i n q u o t i e n t ( Q ) ( d o n e a b o v e ) ,
2 . multiply q u o t i e n t b y u n s c a l e d d i v i s o r ( r e s u l t M )
3 . subtract t h e p r o d u c t f r o m t h e d i v i d e n t t o g e t a n e r r o r ( E = X - M )
4 . if E < d i v i s o r ( Y ) s u b t r a c t 1 , i f E > d i v i s o r ( Y ) a d d 1 , e l s e r e t u r n q u o t i e n t ( Q )
* /
R3 = R 2 . L ( Z ) ; /* Q = X' / Y' */
R2 = R 3 ; /* Preserve Q */
R2 * = R 1 ; /* M = Q * Y */
R2 = R 0 - R 2 ; /* E = X - M */
R0 = R 3 ; /* Copy Q into result reg */
/ * Correction : If r e s u l t o f t h e m u l t i p l y i s n e g a t i v e , w e o v e r f l o w e d
and n e e d t o c o r r e c t t h e r e s u l t b y s u b t r a c t i n g 1 f r o m t h e r e s u l t . * /
R3 = 0 x F F F F ( Z ) ;
R2 = R 2 > > 1 6 ; /* E >> 16 */
CC = R 2 = = R 3 ;
R3 = 1 ;
R1 = R 0 - R 3 ;
IF C C R 0 = R 1 ;
RTS;
2007-06-11 11:31:30 +04:00
ENDPROC( _ _ _ u d i v s i 3 )