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/ * linux/ a r c h / a r m / m a c h - s3 c24 1 0 / s l e e p . S
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*
* Copyright ( c ) 2 0 0 4 S i m t e c E l e c t r o n i c s
* Ben D o o k s < b e n @simtec.co.uk>
*
* S3 C 2 4 1 0 P o w e r M a n a g e r ( S u s p e n d - T o - R A M ) s u p p o r t
*
* Based o n P X A / S A 1 1 0 0 s l e e p c o d e b y :
* Nicolas P i t r e , ( c ) 2 0 0 2 M o n t a V i s t a S o f t w a r e I n c
* Cliff B r a k e , ( c ) 2 0 0 1
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify
* it u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e a s p u b l i s h e d b y
* the F r e e S o f t w a r e F o u n d a t i o n ; either version 2 of the License, or
* ( at y o u r o p t i o n ) a n y l a t e r v e r s i o n .
*
* This p r o g r a m i s d i s t r i b u t e d i n t h e h o p e t h a t i t w i l l b e u s e f u l ,
* but W I T H O U T A N Y W A R R A N T Y ; without even the implied warranty of
* MERCHANTABILITY o r F I T N E S S F O R A P A R T I C U L A R P U R P O S E . S e e t h e
* GNU G e n e r a l P u b l i c L i c e n s e f o r m o r e d e t a i l s .
*
* You s h o u l d h a v e r e c e i v e d a c o p y o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* along w i t h t h i s p r o g r a m ; if not, write to the Free Software
* Foundation, I n c . , 5 9 T e m p l e P l a c e , S u i t e 3 3 0 , B o s t o n , M A 0 2 1 1 1 - 1 3 0 7 U S A
* /
# include < l i n u x / l i n k a g e . h >
# include < a s m / a s s e m b l e r . h >
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# include < m a c h / h a r d w a r e . h >
# include < m a c h / m a p . h >
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# include < m a c h / r e g s - g p i o . h >
# include < m a c h / r e g s - c l o c k . h >
# include < m a c h / r e g s - m e m . h >
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# include < p l a t / r e g s - s e r i a l . h >
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/ * s3 c24 1 0 _ c p u _ s u s p e n d
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*
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* put t h e c p u i n t o s l e e p m o d e
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* /
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ENTRY( s3 c24 1 0 _ c p u _ s u s p e n d )
@@ prepare cpu to sleep
ldr r4 , =S3C2410_REFRESH
ldr r5 , =S3C24XX_MISCCR
ldr r6 , =S3C2410_CLKCON
ldr r7 , [ r4 ] @ get REFRESH (and ensure in TLB)
ldr r8 , [ r5 ] @ get MISCCR (and ensure in TLB)
ldr r9 , [ r6 ] @ get CLKCON (and ensure in TLB)
orr r7 , r7 , #S 3 C 2 4 1 0 _ R E F R E S H _ S E L F @ SDRAM sleep command
orr r8 , r8 , #S 3 C 2 4 1 0 _ M I S C C R _ S D S L E E P @ SDRAM power-down signals
orr r9 , r9 , #S 3 C 2 4 1 0 _ C L K C O N _ P O W E R @ power down command
teq p c , #0 @ first as a trial-run to load cache
bl s3 c24 1 0 _ d o _ s l e e p
teq r0 , r0 @ now do it for real
b s3 c24 1 0 _ d o _ s l e e p @
@@ align next bit of code to cache line
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.align 5
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s3c2410_do_sleep :
streq r7 , [ r4 ] @ SDRAM sleep command
streq r8 , [ r5 ] @ SDRAM power-down config
streq r9 , [ r6 ] @ CPU sleep
1 : beq 1 b
mov p c , r14
