2009-06-03 01:17:38 +04:00
/ *
* This f i l e c o n t a i n s t h e 6 4 - b i t " s e r v e r " P o w e r P C v a r i a n t
* of t h e l o w l e v e l e x c e p t i o n h a n d l i n g i n c l u d i n g e x c e p t i o n
* vectors, e x c e p t i o n r e t u r n , p a r t o f t h e s l b a n d s t a b
* handling a n d o t h e r f i x e d o f f s e t s p e c i f i c t h i n g s .
*
* This f i l e i s m e a n t t o b e #i n c l u d e d f r o m h e a d _ 64 . S d u e t o
2011-03-31 05:57:33 +04:00
* position d e p e n d e n t a s s e m b l y .
2009-06-03 01:17:38 +04:00
*
* Most o f t h i s o r i g i n a t e s f r o m h e a d _ 6 4 . S a n d t h u s h a s t h e s a m e
* copyright h i s t o r y .
*
* /
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 11:27:59 +04:00
# include < a s m / h w _ i r q . h >
2009-07-15 00:52:52 +04:00
# include < a s m / e x c e p t i o n - 6 4 s . h >
2010-11-18 18:06:17 +03:00
# include < a s m / p t r a c e . h >
2014-12-09 21:56:52 +03:00
# include < a s m / c p u i d l e . h >
2016-09-30 12:43:18 +03:00
# include < a s m / h e a d - 6 4 . h >
2009-07-15 00:52:52 +04:00
2009-06-03 01:17:38 +04:00
/ *
2016-09-28 04:31:48 +03:00
* There a r e a f e w c o n s t r a i n t s t o b e c o n c e r n e d w i t h .
* - Real m o d e e x c e p t i o n s c o d e / d a t a m u s t b e l o c a t e d a t t h e i r p h y s i c a l l o c a t i o n .
* - Virtual m o d e e x c e p t i o n s m u s t b e m a p p e d a t t h e i r 0 x c00 0 . . . l o c a t i o n .
* - Fixed l o c a t i o n c o d e m u s t n o t c a l l d i r e c t l y b e y o n d t h e _ _ e n d _ i n t e r r u p t s
* area w h e n b u i l t w i t h C O N F I G _ R E L O C A T A B L E . L O A D _ H A N D L E R / b c t r s e q u e n c e
* must b e u s e d .
* - LOAD_ H A N D L E R t a r g e t s m u s t b e w i t h i n f i r s t 6 4 K o f p h y s i c a l 0 /
* virtual 0 x c00 . . .
* - Conditional b r a n c h t a r g e t s m u s t b e w i t h i n + / - 3 2 K o f c a l l e r .
*
* " Virtual e x c e p t i o n s " r u n w i t h r e l o c a t i o n o n ( M S R _ I R =1 , M S R _ D R =1 ) , a n d
* therefore d o n ' t h a v e t o r u n i n p h y s i c a l l y l o c a t e d c o d e o r r f i d t o
* virtual m o d e k e r n e l c o d e . H o w e v e r o n r e l o c a t a b l e k e r n e l s t h e y d o h a v e
* to b r a n c h t o K E R N E L B A S E o f f s e t b e c a u s e t h e r e s t o f t h e k e r n e l ( o u t s i d e
* the e x c e p t i o n v e c t o r s ) m a y b e l o c a t e d e l s e w h e r e .
*
* Virtual e x c e p t i o n s c o r r e s p o n d w i t h p h y s i c a l , e x c e p t t h e i r e n t r y p o i n t s
* are o f f s e t b y 0 x c00 0 0 0 0 0 0 0 0 0 0 0 0 0 a n d a l s o t e n d t o g e t a n a d d e d 0 x40 0 0
* offset a p p l i e d . V i r t u a l e x c e p t i o n s a r e e n a b l e d w i t h t h e A l t e r n a t e
* Interrupt L o c a t i o n ( A I L ) b i t s e t i n t h e L P C R . H o w e v e r t h i s d o e s n o t
* guarantee t h e y w i l l b e d e l i v e r e d v i r t u a l l y . S o m e c o n d i t i o n s ( s e e t h e I S A )
* cause e x c e p t i o n s t o b e d e l i v e r e d i n r e a l m o d e .
*
* It' s i m p o s s i b l e t o r e c e i v e i n t e r r u p t s b e l o w 0 x30 0 v i a A I L .
*
* KVM : None o f t h e v i r t u a l e x c e p t i o n s a r e f r o m t h e g u e s t . A n y t h i n g t h a t
* escalated t o H V =1 f r o m H V =0 i s d e l i v e r e d v i a r e a l m o d e h a n d l e r s .
*
*
2009-06-03 01:17:38 +04:00
* We l a y o u t p h y s i c a l m e m o r y a s f o l l o w s :
* 0 x0 0 0 0 - 0 x00 f f : S e c o n d a r y p r o c e s s o r s p i n c o d e
2016-09-28 04:31:48 +03:00
* 0 x0 1 0 0 - 0 x18 f f : R e a l m o d e p S e r i e s i n t e r r u p t v e c t o r s
* 0 x1 9 0 0 - 0 x3 f f f : R e a l m o d e t r a m p o l i n e s
* 0 x4 0 0 0 - 0 x58 f f : R e l o n ( I R =1 ,D R =1 ) m o d e p S e r i e s i n t e r r u p t v e c t o r s
* 0 x5 9 0 0 - 0 x6 f f f : R e l o n m o d e t r a m p o l i n e s
2009-06-03 01:17:38 +04:00
* 0 x7 0 0 0 - 0 x7 f f f : F W N M I d a t a a r e a
2016-09-28 04:31:48 +03:00
* 0 x8 0 0 0 - . . . . : C o m m o n i n t e r r u p t h a n d l e r s , r e m a i n i n g e a r l y
* setup c o d e , r e s t o f k e r n e l .
2016-09-21 10:44:07 +03:00
*
* We c o u l d r e c l a i m 0 x40 0 0 - 0 x42 f f f o r r e a l m o d e t r a m p o l i n e s i f t h e s p a c e
* is n e c e s s a r y . U n t i l t h e n i t ' s m o r e c o n s i s t e n t t o e x p l i c i t l y p u t V I R T _ N O N E
* vectors t h e r e .
2016-09-28 04:31:48 +03:00
* /
OPEN_ F I X E D _ S E C T I O N ( r e a l _ v e c t o r s , 0 x01 0 0 , 0 x19 0 0 )
OPEN_ F I X E D _ S E C T I O N ( r e a l _ t r a m p o l i n e s , 0 x19 0 0 , 0 x40 0 0 )
OPEN_ F I X E D _ S E C T I O N ( v i r t _ v e c t o r s , 0 x40 0 0 , 0 x59 0 0 )
OPEN_ F I X E D _ S E C T I O N ( v i r t _ t r a m p o l i n e s , 0 x59 0 0 , 0 x70 0 0 )
# if d e f i n e d ( C O N F I G _ P P C _ P S E R I E S ) | | d e f i n e d ( C O N F I G _ P P C _ P O W E R N V )
/ *
* Data a r e a r e s e r v e d f o r F W N M I o p t i o n .
* This a d d r e s s ( 0 x70 0 0 ) i s f i x e d b y t h e R P A .
* pseries a n d p o w e r n v n e e d t o k e e p t h e w h o l e p a g e f r o m
* 0 x7 0 0 0 t o 0 x80 0 0 f r e e f o r u s e b y t h e f i r m w a r e
2009-06-03 01:17:38 +04:00
* /
2016-09-28 04:31:48 +03:00
ZERO_ F I X E D _ S E C T I O N ( f w n m i _ p a g e , 0 x70 0 0 , 0 x80 0 0 )
OPEN_ T E X T _ S E C T I O N ( 0 x80 0 0 )
# else
OPEN_ T E X T _ S E C T I O N ( 0 x70 0 0 )
# endif
USE_ F I X E D _ S E C T I O N ( r e a l _ v e c t o r s )
2009-06-03 01:17:38 +04:00
/ *
* This i s t h e s t a r t o f t h e i n t e r r u p t h a n d l e r s f o r p S e r i e s
* This c o d e r u n s w i t h r e l o c a t i o n o f f .
* Code f r o m h e r e t o _ _ e n d _ i n t e r r u p t s g e t s c o p i e d d o w n t o r e a l
* address 0 x10 0 w h e n w e a r e r u n n i n g a r e l o c a t a b l e k e r n e l .
* Therefore a n y r e l a t i v e b r a n c h e s i n t h i s s e c t i o n m u s t o n l y
* branch t o l a b e l s i n t h i s s e c t i o n .
* /
.globl __start_interrupts
__start_interrupts :
2016-09-21 10:44:07 +03:00
/* No virt vectors corresponding with 0x0..0x100 */
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ N O N E ( 0 x40 0 0 , 0 x10 0 )
2016-09-21 10:44:07 +03:00
2016-10-13 05:17:14 +03:00
2011-01-24 10:42:41 +03:00
# ifdef C O N F I G _ P P C _ P 7 _ N A P
2016-10-13 05:17:14 +03:00
/ *
* If r u n n i n g n a t i v e o n a r c h 2 . 0 6 o r l a t e r , c h e c k i f w e a r e w a k i n g u p
* from n a p / s l e e p / w i n k l e , a n d b r a n c h t o i d l e h a n d l e r .
2011-01-24 10:42:41 +03:00
* /
2016-10-13 05:17:14 +03:00
# define I D L E T E S T ( n ) \
BEGIN_ F T R _ S E C T I O N ; \
mfspr r10 ,S P R N _ S R R 1 ; \
rlwinm. r10 ,r10 ,4 7 - 3 1 ,3 0 ,3 1 ; \
beq- 1 f ; \
cmpwi c r3 ,r10 ,2 ; \
BRANCH_ T O _ C O M M O N ( r10 , s y s t e m _ r e s e t _ i d l e _ c o m m o n ) ; \
1 : \
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ H V M O D E | C P U _ F T R _ A R C H _ 2 0 6 )
# else
# define I D L E T E S T N O T E S T
# endif
KVM: PPC: Allow book3s_hv guests to use SMT processor modes
This lifts the restriction that book3s_hv guests can only run one
hardware thread per core, and allows them to use up to 4 threads
per core on POWER7. The host still has to run single-threaded.
This capability is advertised to qemu through a new KVM_CAP_PPC_SMT
capability. The return value of the ioctl querying this capability
is the number of vcpus per virtual CPU core (vcore), currently 4.
To use this, the host kernel should be booted with all threads
active, and then all the secondary threads should be offlined.
This will put the secondary threads into nap mode. KVM will then
wake them from nap mode and use them for running guest code (while
they are still offline). To wake the secondary threads, we send
them an IPI using a new xics_wake_cpu() function, implemented in
arch/powerpc/sysdev/xics/icp-native.c. In other words, at this stage
we assume that the platform has a XICS interrupt controller and
we are using icp-native.c to drive it. Since the woken thread will
need to acknowledge and clear the IPI, we also export the base
physical address of the XICS registers using kvmppc_set_xics_phys()
for use in the low-level KVM book3s code.
When a vcpu is created, it is assigned to a virtual CPU core.
The vcore number is obtained by dividing the vcpu number by the
number of threads per core in the host. This number is exported
to userspace via the KVM_CAP_PPC_SMT capability. If qemu wishes
to run the guest in single-threaded mode, it should make all vcpu
numbers be multiples of the number of threads per core.
We distinguish three states of a vcpu: runnable (i.e., ready to execute
the guest), blocked (that is, idle), and busy in host. We currently
implement a policy that the vcore can run only when all its threads
are runnable or blocked. This way, if a vcpu needs to execute elsewhere
in the kernel or in qemu, it can do so without being starved of CPU
by the other vcpus.
When a vcore starts to run, it executes in the context of one of the
vcpu threads. The other vcpu threads all go to sleep and stay asleep
until something happens requiring the vcpu thread to return to qemu,
or to wake up to run the vcore (this can happen when another vcpu
thread goes from busy in host state to blocked).
It can happen that a vcpu goes from blocked to runnable state (e.g.
because of an interrupt), and the vcore it belongs to is already
running. In that case it can start to run immediately as long as
the none of the vcpus in the vcore have started to exit the guest.
We send the next free thread in the vcore an IPI to get it to start
to execute the guest. It synchronizes with the other threads via
the vcore->entry_exit_count field to make sure that it doesn't go
into the guest if the other vcpus are exiting by the time that it
is ready to actually enter the guest.
Note that there is no fixed relationship between the hardware thread
number and the vcpu number. Hardware threads are assigned to vcpus
as they become runnable, so we will always use the lower-numbered
hardware threads in preference to higher-numbered threads if not all
the vcpus in the vcore are runnable, regardless of which vcpus are
runnable.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 04:23:08 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ B E G I N ( s y s t e m _ r e s e t , 0 x10 0 , 0 x10 0 )
2016-10-13 05:17:14 +03:00
SET_ S C R A T C H 0 ( r13 )
2016-11-02 09:57:01 +03:00
GET_ P A C A ( r13 )
clrrdi r13 ,r13 ,1 / * L a s t b i t o f H S P R G 0 i s s e t i f w a k i n g f r o m w i n k l e * /
EXCEPTION_ P R O L O G _ P S E R I E S _ P A C A ( P A C A _ E X G E N , s y s t e m _ r e s e t _ c o m m o n , E X C _ S T D ,
2016-10-13 05:17:14 +03:00
IDLETEST, 0 x10 0 )
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ E N D ( s y s t e m _ r e s e t , 0 x10 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x41 0 0 , 0 x10 0 )
2016-10-13 05:17:14 +03:00
# ifdef C O N F I G _ P P C _ P 7 _ N A P
EXC_ C O M M O N _ B E G I N ( s y s t e m _ r e s e t _ i d l e _ c o m m o n )
2016-11-02 09:57:01 +03:00
BEGIN_ F T R _ S E C T I O N
GET_ P A C A ( r13 ) / * R e s t o r e H S P R G 0 t o g e t t h e w i n k l e b i t i n r13 * /
END_ F T R _ S E C T I O N _ I F C L R ( C P U _ F T R _ A R C H _ 3 0 0 )
2016-07-08 09:20:46 +03:00
bl p n v _ r e s t o r e _ h y p _ r e s o u r c e
2014-12-09 21:56:53 +03:00
2014-12-09 21:56:52 +03:00
li r0 ,P N V _ T H R E A D _ R U N N I N G
stb r0 ,P A C A _ T H R E A D _ I D L E _ S T A T E ( r13 ) / * C l e a r t h r e a d s t a t e * /
KVM: PPC: Allow book3s_hv guests to use SMT processor modes
This lifts the restriction that book3s_hv guests can only run one
hardware thread per core, and allows them to use up to 4 threads
per core on POWER7. The host still has to run single-threaded.
This capability is advertised to qemu through a new KVM_CAP_PPC_SMT
capability. The return value of the ioctl querying this capability
is the number of vcpus per virtual CPU core (vcore), currently 4.
To use this, the host kernel should be booted with all threads
active, and then all the secondary threads should be offlined.
This will put the secondary threads into nap mode. KVM will then
wake them from nap mode and use them for running guest code (while
they are still offline). To wake the secondary threads, we send
them an IPI using a new xics_wake_cpu() function, implemented in
arch/powerpc/sysdev/xics/icp-native.c. In other words, at this stage
we assume that the platform has a XICS interrupt controller and
we are using icp-native.c to drive it. Since the woken thread will
need to acknowledge and clear the IPI, we also export the base
physical address of the XICS registers using kvmppc_set_xics_phys()
for use in the low-level KVM book3s code.
When a vcpu is created, it is assigned to a virtual CPU core.
The vcore number is obtained by dividing the vcpu number by the
number of threads per core in the host. This number is exported
to userspace via the KVM_CAP_PPC_SMT capability. If qemu wishes
to run the guest in single-threaded mode, it should make all vcpu
numbers be multiples of the number of threads per core.
We distinguish three states of a vcpu: runnable (i.e., ready to execute
the guest), blocked (that is, idle), and busy in host. We currently
implement a policy that the vcore can run only when all its threads
are runnable or blocked. This way, if a vcpu needs to execute elsewhere
in the kernel or in qemu, it can do so without being starved of CPU
by the other vcpus.
When a vcore starts to run, it executes in the context of one of the
vcpu threads. The other vcpu threads all go to sleep and stay asleep
until something happens requiring the vcpu thread to return to qemu,
or to wake up to run the vcore (this can happen when another vcpu
thread goes from busy in host state to blocked).
It can happen that a vcpu goes from blocked to runnable state (e.g.
because of an interrupt), and the vcore it belongs to is already
running. In that case it can start to run immediately as long as
the none of the vcpus in the vcore have started to exit the guest.
We send the next free thread in the vcore an IPI to get it to start
to execute the guest. It synchronizes with the other threads via
the vcore->entry_exit_count field to make sure that it doesn't go
into the guest if the other vcpus are exiting by the time that it
is ready to actually enter the guest.
Note that there is no fixed relationship between the hardware thread
number and the vcpu number. Hardware threads are assigned to vcpus
as they become runnable, so we will always use the lower-numbered
hardware threads in preference to higher-numbered threads if not all
the vcpus in the vcore are runnable, regardless of which vcpus are
runnable.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 04:23:08 +04:00
2013-10-07 20:47:53 +04:00
# ifdef C O N F I G _ K V M _ B O O K 3 S _ H V _ P O S S I B L E
2012-02-03 04:54:17 +04:00
li r0 ,K V M _ H W T H R E A D _ I N _ K E R N E L
stb r0 ,H S T A T E _ H W T H R E A D _ S T A T E ( r13 )
/* Order setting hwthread_state vs. testing hwthread_req */
sync
lbz r0 ,H S T A T E _ H W T H R E A D _ R E Q ( r13 )
cmpwi r0 ,0
beq 1 f
2017-04-19 16:05:43 +03:00
b k v m _ s t a r t _ g u e s t
KVM: PPC: Allow book3s_hv guests to use SMT processor modes
This lifts the restriction that book3s_hv guests can only run one
hardware thread per core, and allows them to use up to 4 threads
per core on POWER7. The host still has to run single-threaded.
This capability is advertised to qemu through a new KVM_CAP_PPC_SMT
capability. The return value of the ioctl querying this capability
is the number of vcpus per virtual CPU core (vcore), currently 4.
To use this, the host kernel should be booted with all threads
active, and then all the secondary threads should be offlined.
This will put the secondary threads into nap mode. KVM will then
wake them from nap mode and use them for running guest code (while
they are still offline). To wake the secondary threads, we send
them an IPI using a new xics_wake_cpu() function, implemented in
arch/powerpc/sysdev/xics/icp-native.c. In other words, at this stage
we assume that the platform has a XICS interrupt controller and
we are using icp-native.c to drive it. Since the woken thread will
need to acknowledge and clear the IPI, we also export the base
physical address of the XICS registers using kvmppc_set_xics_phys()
for use in the low-level KVM book3s code.
When a vcpu is created, it is assigned to a virtual CPU core.
The vcore number is obtained by dividing the vcpu number by the
number of threads per core in the host. This number is exported
to userspace via the KVM_CAP_PPC_SMT capability. If qemu wishes
to run the guest in single-threaded mode, it should make all vcpu
numbers be multiples of the number of threads per core.
We distinguish three states of a vcpu: runnable (i.e., ready to execute
the guest), blocked (that is, idle), and busy in host. We currently
implement a policy that the vcore can run only when all its threads
are runnable or blocked. This way, if a vcpu needs to execute elsewhere
in the kernel or in qemu, it can do so without being starved of CPU
by the other vcpus.
When a vcore starts to run, it executes in the context of one of the
vcpu threads. The other vcpu threads all go to sleep and stay asleep
until something happens requiring the vcpu thread to return to qemu,
or to wake up to run the vcore (this can happen when another vcpu
thread goes from busy in host state to blocked).
It can happen that a vcpu goes from blocked to runnable state (e.g.
because of an interrupt), and the vcore it belongs to is already
running. In that case it can start to run immediately as long as
the none of the vcpus in the vcore have started to exit the guest.
We send the next free thread in the vcore an IPI to get it to start
to execute the guest. It synchronizes with the other threads via
the vcore->entry_exit_count field to make sure that it doesn't go
into the guest if the other vcpus are exiting by the time that it
is ready to actually enter the guest.
Note that there is no fixed relationship between the hardware thread
number and the vcpu number. Hardware threads are assigned to vcpus
as they become runnable, so we will always use the lower-numbered
hardware threads in preference to higher-numbered threads if not all
the vcpus in the vcore are runnable, regardless of which vcpus are
runnable.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 04:23:08 +04:00
1 :
# endif
powerpc/powernv: Return to cpu offline loop when finished in KVM guest
When a secondary hardware thread has finished running a KVM guest, we
currently put that thread into nap mode using a nap instruction in
the KVM code. This changes the code so that instead of doing a nap
instruction directly, we instead cause the call to power7_nap() that
put the thread into nap mode to return. The reason for doing this is
to avoid having the KVM code having to know what low-power mode to
put the thread into.
In the case of a secondary thread used to run a KVM guest, the thread
will be offline from the point of view of the host kernel, and the
relevant power7_nap() call is the one in pnv_smp_cpu_disable().
In this case we don't want to clear pending IPIs in the offline loop
in that function, since that might cause us to miss the wakeup for
the next time the thread needs to run a guest. To tell whether or
not to clear the interrupt, we use the SRR1 value returned from
power7_nap(), and check if it indicates an external interrupt. We
arrange that the return from power7_nap() when we have finished running
a guest returns 0, so pending interrupts don't get flushed in that
case.
Note that it is important a secondary thread that has finished
executing in the guest, or that didn't have a guest to run, should
not return to power7_nap's caller while the kvm_hstate.hwthread_req
flag in the PACA is non-zero, because the return from power7_nap
will reenable the MMU, and the MMU might still be in guest context.
In this situation we spin at low priority in real mode waiting for
hwthread_req to become zero.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2014-12-03 06:48:40 +03:00
/* Return SRR1 from power7_nap() */
mfspr r3 ,S P R N _ S R R 1
2016-07-08 09:20:44 +03:00
blt c r3 ,2 f
2016-07-08 09:20:46 +03:00
b p n v _ w a k e u p _ l o s s
2 : b p n v _ w a k e u p _ n o l o s s
2016-10-13 05:17:14 +03:00
# endif
2014-02-26 04:08:25 +04:00
2016-09-21 10:43:30 +03:00
EXC_ C O M M O N ( s y s t e m _ r e s e t _ c o m m o n , 0 x10 0 , s y s t e m _ r e s e t _ e x c e p t i o n )
# ifdef C O N F I G _ P P C _ P S E R I E S
/ *
* Vectors f o r t h e F W N M I o p t i o n . S h a r e c o m m o n c o d e .
* /
TRAMP_ R E A L _ B E G I N ( s y s t e m _ r e s e t _ f w n m i )
SET_ S C R A T C H 0 ( r13 ) / * s a v e r13 * /
EXCEPTION_ P R O L O G _ P S E R I E S ( P A C A _ E X G E N , s y s t e m _ r e s e t _ c o m m o n , E X C _ S T D ,
NOTEST, 0 x10 0 )
# endif / * C O N F I G _ P P C _ P S E R I E S * /
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ B E G I N ( m a c h i n e _ c h e c k , 0 x20 0 , 0 x10 0 )
2011-06-29 04:18:26 +04:00
/ * This i s m o v e d o u t o f l i n e a s i t c a n b e p a t c h e d b y F W , b u t
* some c o d e p a t h m i g h t s t i l l w a n t t o b r a n c h i n t o t h e o r i g i n a l
* vector
* /
powerpc: Save CFAR before branching in interrupt entry paths
Some of the interrupt vectors on 64-bit POWER server processors are
only 32 bytes long, which is not enough for the full first-level
interrupt handler. For these we currently just have a branch to an
out-of-line handler. However, this means that we corrupt the CFAR
(come-from address register) on POWER7 and later processors.
To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces:
EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR
is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We
then put EXCEPTION_PROLOG_0 in the short interrupt vectors before
we branch to the out-of-line handler, which contains the rest of the
first-level interrupt handler. To facilitate this, we define new
_OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc.
In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more
than 6 instructions, it was necessary to move the stores that move
the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and
to get rid of one of the two HMT_MEDIUM instructions. Previously
there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was
nop'd out on processors with the PPR (POWER7 and later), and then
another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside
__EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR.
Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally
and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although
this leaves it in for the interrupt vectors where there is room for
it.
Previously we had a handler for hypervisor maintenance interrupts at
0xe50, which doesn't leave enough room for the vector for hypervisor
emulation assist interrupts at 0xe40, since we need 8 instructions.
The 0xe50 vector was only used on POWER6, as the HMI vector was moved
to 0xe60 on POWER7. Since we don't support running in hypervisor mode
on POWER6, we just remove the handler at 0xe50.
This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0
instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD
from the relocation-on vectors (since any CPU that supports
relocation-on interrupts also has the PPR).
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-02-04 22:10:15 +04:00
SET_ S C R A T C H 0 ( r13 ) / * s a v e r13 * /
2016-08-05 15:04:13 +03:00
/ *
* Running n a t i v e o n a r c h 2 . 0 6 o r l a t e r , w e m a y w a k e u p f r o m w i n k l e
2016-11-02 09:57:01 +03:00
* inside m a c h i n e c h e c k . I f y e s , t h e n l a s t b i t o f H S P R G 0 w o u l d b e s e t
2016-08-05 15:04:13 +03:00
* to 1 . H e n c e c l e a r i t u n c o n d i t i o n a l l y .
2013-10-30 18:34:31 +04:00
* /
2016-08-05 15:04:13 +03:00
GET_ P A C A ( r13 )
clrrdi r13 ,r13 ,1
SET_ P A C A ( r13 )
powerpc: Save CFAR before branching in interrupt entry paths
Some of the interrupt vectors on 64-bit POWER server processors are
only 32 bytes long, which is not enough for the full first-level
interrupt handler. For these we currently just have a branch to an
out-of-line handler. However, this means that we corrupt the CFAR
(come-from address register) on POWER7 and later processors.
To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces:
EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR
is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We
then put EXCEPTION_PROLOG_0 in the short interrupt vectors before
we branch to the out-of-line handler, which contains the rest of the
first-level interrupt handler. To facilitate this, we define new
_OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc.
In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more
than 6 instructions, it was necessary to move the stores that move
the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and
to get rid of one of the two HMT_MEDIUM instructions. Previously
there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was
nop'd out on processors with the PPR (POWER7 and later), and then
another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside
__EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR.
Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally
and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although
this leaves it in for the interrupt vectors where there is room for
it.
Previously we had a handler for hypervisor maintenance interrupts at
0xe50, which doesn't leave enough room for the vector for hypervisor
emulation assist interrupts at 0xe40, since we need 8 instructions.
The 0xe50 vector was only used on POWER6, as the HMI vector was moved
to 0xe60 on POWER7. Since we don't support running in hypervisor mode
on POWER6, we just remove the handler at 0xe50.
This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0
instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD
from the relocation-on vectors (since any CPU that supports
relocation-on interrupts also has the PPR).
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-02-04 22:10:15 +04:00
EXCEPTION_ P R O L O G _ 0 ( P A C A _ E X M C )
powerpc/book3s: handle machine check in Linux host.
Move machine check entry point into Linux. So far we were dependent on
firmware to decode MCE error details and handover the high level info to OS.
This patch introduces early machine check routine that saves the MCE
information (srr1, srr0, dar and dsisr) to the emergency stack. We allocate
stack frame on emergency stack and set the r1 accordingly. This allows us to be
prepared to take another exception without loosing context. One thing to note
here that, if we get another machine check while ME bit is off then we risk a
checkstop. Hence we restrict ourselves to save only MCE information and
register saved on PACA_EXMC save are before we turn the ME bit on. We use
paca->in_mce flag to differentiate between first entry and nested machine check
entry which helps proper use of emergency stack. We increment paca->in_mce
every time we enter in early machine check handler and decrement it while
leaving. When we enter machine check early handler first time (paca->in_mce ==
0), we are sure nobody is using MC emergency stack and allocate a stack frame
at the start of the emergency stack. During subsequent entry (paca->in_mce >
0), we know that r1 points inside emergency stack and we allocate separate
stack frame accordingly. This prevents us from clobbering MCE information
during nested machine checks.
The early machine check handler changes are placed under CPU_FTR_HVMODE
section. This makes sure that the early machine check handler will get executed
only in hypervisor kernel.
This is the code flow:
Machine Check Interrupt
|
V
0x200 vector ME=0, IR=0, DR=0
|
V
+-----------------------------------------------+
|machine_check_pSeries_early: | ME=0, IR=0, DR=0
| Alloc frame on emergency stack |
| Save srr1, srr0, dar and dsisr on stack |
+-----------------------------------------------+
|
(ME=1, IR=0, DR=0, RFID)
|
V
machine_check_handle_early ME=1, IR=0, DR=0
|
V
+-----------------------------------------------+
| machine_check_early (r3=pt_regs) | ME=1, IR=0, DR=0
| Things to do: (in next patches) |
| Flush SLB for SLB errors |
| Flush TLB for TLB errors |
| Decode and save MCE info |
+-----------------------------------------------+
|
(Fall through existing exception handler routine.)
|
V
machine_check_pSerie ME=1, IR=0, DR=0
|
(ME=1, IR=1, DR=1, RFID)
|
V
machine_check_common ME=1, IR=1, DR=1
.
.
.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-30 18:34:08 +04:00
BEGIN_ F T R _ S E C T I O N
2016-03-01 08:47:46 +03:00
b m a c h i n e _ c h e c k _ p o w e r n v _ e a r l y
powerpc/book3s: handle machine check in Linux host.
Move machine check entry point into Linux. So far we were dependent on
firmware to decode MCE error details and handover the high level info to OS.
This patch introduces early machine check routine that saves the MCE
information (srr1, srr0, dar and dsisr) to the emergency stack. We allocate
stack frame on emergency stack and set the r1 accordingly. This allows us to be
prepared to take another exception without loosing context. One thing to note
here that, if we get another machine check while ME bit is off then we risk a
checkstop. Hence we restrict ourselves to save only MCE information and
register saved on PACA_EXMC save are before we turn the ME bit on. We use
paca->in_mce flag to differentiate between first entry and nested machine check
entry which helps proper use of emergency stack. We increment paca->in_mce
every time we enter in early machine check handler and decrement it while
leaving. When we enter machine check early handler first time (paca->in_mce ==
0), we are sure nobody is using MC emergency stack and allocate a stack frame
at the start of the emergency stack. During subsequent entry (paca->in_mce >
0), we know that r1 points inside emergency stack and we allocate separate
stack frame accordingly. This prevents us from clobbering MCE information
during nested machine checks.
The early machine check handler changes are placed under CPU_FTR_HVMODE
section. This makes sure that the early machine check handler will get executed
only in hypervisor kernel.
This is the code flow:
Machine Check Interrupt
|
V
0x200 vector ME=0, IR=0, DR=0
|
V
+-----------------------------------------------+
|machine_check_pSeries_early: | ME=0, IR=0, DR=0
| Alloc frame on emergency stack |
| Save srr1, srr0, dar and dsisr on stack |
+-----------------------------------------------+
|
(ME=1, IR=0, DR=0, RFID)
|
V
machine_check_handle_early ME=1, IR=0, DR=0
|
V
+-----------------------------------------------+
| machine_check_early (r3=pt_regs) | ME=1, IR=0, DR=0
| Things to do: (in next patches) |
| Flush SLB for SLB errors |
| Flush TLB for TLB errors |
| Decode and save MCE info |
+-----------------------------------------------+
|
(Fall through existing exception handler routine.)
|
V
machine_check_pSerie ME=1, IR=0, DR=0
|
(ME=1, IR=1, DR=1, RFID)
|
V
machine_check_common ME=1, IR=1, DR=1
.
.
.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-30 18:34:08 +04:00
FTR_ S E C T I O N _ E L S E
powerpc: Save CFAR before branching in interrupt entry paths
Some of the interrupt vectors on 64-bit POWER server processors are
only 32 bytes long, which is not enough for the full first-level
interrupt handler. For these we currently just have a branch to an
out-of-line handler. However, this means that we corrupt the CFAR
(come-from address register) on POWER7 and later processors.
To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces:
EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR
is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We
then put EXCEPTION_PROLOG_0 in the short interrupt vectors before
we branch to the out-of-line handler, which contains the rest of the
first-level interrupt handler. To facilitate this, we define new
_OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc.
In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more
than 6 instructions, it was necessary to move the stores that move
the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and
to get rid of one of the two HMT_MEDIUM instructions. Previously
there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was
nop'd out on processors with the PPR (POWER7 and later), and then
another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside
__EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR.
Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally
and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although
this leaves it in for the interrupt vectors where there is room for
it.
Previously we had a handler for hypervisor maintenance interrupts at
0xe50, which doesn't leave enough room for the vector for hypervisor
emulation assist interrupts at 0xe40, since we need 8 instructions.
The 0xe50 vector was only used on POWER6, as the HMI vector was moved
to 0xe60 on POWER7. Since we don't support running in hypervisor mode
on POWER6, we just remove the handler at 0xe50.
This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0
instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD
from the relocation-on vectors (since any CPU that supports
relocation-on interrupts also has the PPR).
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-02-04 22:10:15 +04:00
b m a c h i n e _ c h e c k _ p S e r i e s _ 0
powerpc/book3s: handle machine check in Linux host.
Move machine check entry point into Linux. So far we were dependent on
firmware to decode MCE error details and handover the high level info to OS.
This patch introduces early machine check routine that saves the MCE
information (srr1, srr0, dar and dsisr) to the emergency stack. We allocate
stack frame on emergency stack and set the r1 accordingly. This allows us to be
prepared to take another exception without loosing context. One thing to note
here that, if we get another machine check while ME bit is off then we risk a
checkstop. Hence we restrict ourselves to save only MCE information and
register saved on PACA_EXMC save are before we turn the ME bit on. We use
paca->in_mce flag to differentiate between first entry and nested machine check
entry which helps proper use of emergency stack. We increment paca->in_mce
every time we enter in early machine check handler and decrement it while
leaving. When we enter machine check early handler first time (paca->in_mce ==
0), we are sure nobody is using MC emergency stack and allocate a stack frame
at the start of the emergency stack. During subsequent entry (paca->in_mce >
0), we know that r1 points inside emergency stack and we allocate separate
stack frame accordingly. This prevents us from clobbering MCE information
during nested machine checks.
The early machine check handler changes are placed under CPU_FTR_HVMODE
section. This makes sure that the early machine check handler will get executed
only in hypervisor kernel.
This is the code flow:
Machine Check Interrupt
|
V
0x200 vector ME=0, IR=0, DR=0
|
V
+-----------------------------------------------+
|machine_check_pSeries_early: | ME=0, IR=0, DR=0
| Alloc frame on emergency stack |
| Save srr1, srr0, dar and dsisr on stack |
+-----------------------------------------------+
|
(ME=1, IR=0, DR=0, RFID)
|
V
machine_check_handle_early ME=1, IR=0, DR=0
|
V
+-----------------------------------------------+
| machine_check_early (r3=pt_regs) | ME=1, IR=0, DR=0
| Things to do: (in next patches) |
| Flush SLB for SLB errors |
| Flush TLB for TLB errors |
| Decode and save MCE info |
+-----------------------------------------------+
|
(Fall through existing exception handler routine.)
|
V
machine_check_pSerie ME=1, IR=0, DR=0
|
(ME=1, IR=1, DR=1, RFID)
|
V
machine_check_common ME=1, IR=1, DR=1
.
.
.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-30 18:34:08 +04:00
ALT_ F T R _ S E C T I O N _ E N D _ I F S E T ( C P U _ F T R _ H V M O D E )
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ E N D ( m a c h i n e _ c h e c k , 0 x20 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x42 0 0 , 0 x10 0 )
2016-09-21 10:43:31 +03:00
TRAMP_ R E A L _ B E G I N ( m a c h i n e _ c h e c k _ p o w e r n v _ e a r l y )
BEGIN_ F T R _ S E C T I O N
EXCEPTION_ P R O L O G _ 1 ( P A C A _ E X M C , N O T E S T , 0 x20 0 )
/ *
* Register c o n t e n t s :
* R1 3 = P A C A
* R9 = C R
* Original R 9 t o R 1 3 i s s a v e d o n P A C A _ E X M C
*
* Switch t o m c _ e m e r g e n c y s t a c k a n d h a n d l e r e - e n t r a n c y ( w e l i m i t
* the n e s t e d M C E u p t o l e v e l 4 t o a v o i d s t a c k o v e r f l o w ) .
* Save M C E r e g i s t e r s s r r1 , s r r0 , d a r a n d d s i s r a n d t h e n s e t M E =1
*
* We u s e p a c a - > i n _ m c e t o c h e c k w h e t h e r t h i s i s t h e f i r s t e n t r y o r
* nested m a c h i n e c h e c k . W e i n c r e m e n t p a c a - > i n _ m c e t o t r a c k n e s t e d
* machine c h e c k s .
*
* If t h i s i s t h e f i r s t e n t r y t h e n s e t s t a c k p o i n t e r t o
* paca- > m c _ e m e r g e n c y _ s p , o t h e r w i s e r1 i s a l r e a d y p o i n t i n g t o
* stack f r a m e o n m c _ e m e r g e n c y s t a c k .
*
* NOTE : We a r e h e r e w i t h M S R _ M E =0 ( o f f ) , w h i c h m e a n s w e r i s k a
* checkstop i f w e g e t a n o t h e r m a c h i n e c h e c k e x c e p t i o n b e f o r e w e d o
* rfid w i t h M S R _ M E =1 .
* /
mr r11 ,r1 / * S a v e r1 * /
lhz r10 ,P A C A _ I N _ M C E ( r13 )
cmpwi r10 ,0 / * A r e w e i n n e s t e d m a c h i n e c h e c k * /
bne 0 f / * Y e s , w e a r e . * /
/* First machine check entry */
ld r1 ,P A C A M C E M E R G S P ( r13 ) / * U s e M C e m e r g e n c y s t a c k * /
0 : subi r1 ,r1 ,I N T _ F R A M E _ S I Z E / * a l l o c s t a c k f r a m e * /
addi r10 ,r10 ,1 / * i n c r e m e n t p a c a - > i n _ m c e * /
sth r10 ,P A C A _ I N _ M C E ( r13 )
/* Limit nested MCE to level 4 to avoid stack overflow */
cmpwi r10 ,4
bgt 2 f / * C h e c k i f w e h i t l i m i t o f 4 * /
std r11 ,G P R 1 ( r1 ) / * S a v e r1 o n t h e s t a c k . * /
std r11 ,0 ( r1 ) / * m a k e s t a c k c h a i n p o i n t e r * /
mfspr r11 ,S P R N _ S R R 0 / * S a v e S R R 0 * /
std r11 ,_ N I P ( r1 )
mfspr r11 ,S P R N _ S R R 1 / * S a v e S R R 1 * /
std r11 ,_ M S R ( r1 )
mfspr r11 ,S P R N _ D A R / * S a v e D A R * /
std r11 ,_ D A R ( r1 )
mfspr r11 ,S P R N _ D S I S R / * S a v e D S I S R * /
std r11 ,_ D S I S R ( r1 )
std r9 ,_ C C R ( r1 ) / * S a v e C R i n s t a c k f r a m e * /
/* Save r9 through r13 from EXMC save area to stack frame. */
EXCEPTION_ P R O L O G _ C O M M O N _ 2 ( P A C A _ E X M C )
mfmsr r11 / * g e t M S R v a l u e * /
ori r11 ,r11 ,M S R _ M E / * t u r n o n M E b i t * /
ori r11 ,r11 ,M S R _ R I / * t u r n o n R I b i t * /
LOAD_ H A N D L E R ( r12 , m a c h i n e _ c h e c k _ h a n d l e _ e a r l y )
1 : mtspr S P R N _ S R R 0 ,r12
mtspr S P R N _ S R R 1 ,r11
rfid
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
2 :
/ * Stack o v e r f l o w . S t a y o n e m e r g e n c y s t a c k a n d p a n i c .
* Keep t h e M E b i t o f f w h i l e p a n i c - i n g , s o t h a t i f w e h i t
* another m a c h i n e c h e c k w e c h e c k s t o p .
* /
addi r1 ,r1 ,I N T _ F R A M E _ S I Z E / * g o b a c k t o p r e v i o u s s t a c k f r a m e * /
ld r11 ,P A C A K M S R ( r13 )
LOAD_ H A N D L E R ( r12 , u n r e c o v e r _ m c e )
li r10 ,M S R _ M E
andc r11 ,r11 ,r10 / * T u r n o f f M S R _ M E * /
b 1 b
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ H V M O D E )
TRAMP_ R E A L _ B E G I N ( m a c h i n e _ c h e c k _ p S e r i e s )
.globl machine_check_fwnmi
machine_check_fwnmi :
SET_ S C R A T C H 0 ( r13 ) / * s a v e r13 * /
EXCEPTION_ P R O L O G _ 0 ( P A C A _ E X M C )
machine_check_pSeries_0 :
EXCEPTION_ P R O L O G _ 1 ( P A C A _ E X M C , K V M T E S T _ P R , 0 x20 0 )
/ *
* The f o l l o w i n g i s e s s e n t i a l l y E X C E P T I O N _ P R O L O G _ P S E R I E S _ 1 w i t h t h e
* difference t h a t M S R _ R I i s n o t e n a b l e d , b e c a u s e P A C A _ E X M C i s b e i n g
* used, s o n e s t e d m a c h i n e c h e c k c o r r u p t s i t . m a c h i n e _ c h e c k _ c o m m o n
* enables M S R _ R I .
* /
ld r10 ,P A C A K M S R ( r13 )
xori r10 ,r10 ,M S R _ R I
mfspr r11 ,S P R N _ S R R 0
LOAD_ H A N D L E R ( r12 , m a c h i n e _ c h e c k _ c o m m o n )
mtspr S P R N _ S R R 0 ,r12
mfspr r12 ,S P R N _ S R R 1
mtspr S P R N _ S R R 1 ,r10
rfid
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
TRAMP_ K V M _ S K I P ( P A C A _ E X M C , 0 x20 0 )
EXC_ C O M M O N _ B E G I N ( m a c h i n e _ c h e c k _ c o m m o n )
/ *
* Machine c h e c k i s d i f f e r e n t b e c a u s e w e u s e a d i f f e r e n t
* save a r e a : P A C A _ E X M C i n s t e a d o f P A C A _ E X G E N .
* /
mfspr r10 ,S P R N _ D A R
std r10 ,P A C A _ E X M C + E X _ D A R ( r13 )
mfspr r10 ,S P R N _ D S I S R
stw r10 ,P A C A _ E X M C + E X _ D S I S R ( r13 )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x20 0 , P A C A _ E X M C )
FINISH_ N A P
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
ld r3 ,P A C A _ E X M C + E X _ D A R ( r13 )
lwz r4 ,P A C A _ E X M C + E X _ D S I S R ( r13 )
/* Enable MSR_RI when finished with PACA_EXMC */
li r10 ,M S R _ R I
mtmsrd r10 ,1
std r3 ,_ D A R ( r1 )
std r4 ,_ D S I S R ( r1 )
bl s a v e _ n v g p r s
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl m a c h i n e _ c h e c k _ e x c e p t i o n
b r e t _ f r o m _ e x c e p t
# define M A C H I N E _ C H E C K _ H A N D L E R _ W I N D U P \
/* Clear MSR_RI before setting SRR0 and SRR1. */ \
li r0 ,M S R _ R I ; \
mfmsr r9 ; /* get MSR value */ \
andc r9 ,r9 ,r0 ; \
mtmsrd r9 ,1 ; /* Clear MSR_RI */ \
/* Move original SRR0 and SRR1 into the respective regs */ \
ld r9 ,_ M S R ( r1 ) ; \
mtspr S P R N _ S R R 1 ,r9 ; \
ld r3 ,_ N I P ( r1 ) ; \
mtspr S P R N _ S R R 0 ,r3 ; \
ld r9 ,_ C T R ( r1 ) ; \
mtctr r9 ; \
ld r9 ,_ X E R ( r1 ) ; \
mtxer r9 ; \
ld r9 ,_ L I N K ( r1 ) ; \
mtlr r9 ; \
REST_ G P R ( 0 , r1 ) ; \
REST_ 8 G P R S ( 2 , r1 ) ; \
REST_ G P R ( 1 0 , r1 ) ; \
ld r11 ,_ C C R ( r1 ) ; \
mtcr r11 ; \
/* Decrement paca->in_mce. */ \
lhz r12 ,P A C A _ I N _ M C E ( r13 ) ; \
subi r12 ,r12 ,1 ; \
sth r12 ,P A C A _ I N _ M C E ( r13 ) ; \
REST_ G P R ( 1 1 , r1 ) ; \
REST_ 2 G P R S ( 1 2 , r1 ) ; \
/* restore original r1. */ \
ld r1 ,G P R 1 ( r1 )
/ *
* Handle m a c h i n e c h e c k e a r l y i n r e a l m o d e . W e c o m e h e r e w i t h
* ME=1 , M M U ( I R =0 a n d D R =0 ) o f f a n d u s i n g M C e m e r g e n c y s t a c k .
* /
EXC_ C O M M O N _ B E G I N ( m a c h i n e _ c h e c k _ h a n d l e _ e a r l y )
std r0 ,G P R 0 ( r1 ) / * S a v e r0 * /
EXCEPTION_ P R O L O G _ C O M M O N _ 3 ( 0 x20 0 )
bl s a v e _ n v g p r s
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl m a c h i n e _ c h e c k _ e a r l y
std r3 ,R E S U L T ( r1 ) / * S a v e r e s u l t * /
ld r12 ,_ M S R ( r1 )
# ifdef C O N F I G _ P P C _ P 7 _ N A P
/ *
* Check i f t h r e a d w a s i n p o w e r s a v i n g m o d e . W e c o m e h e r e w h e n a n y
* of t h e f o l l o w i n g i s t r u e :
* a. t h r e a d w a s n ' t i n p o w e r s a v i n g m o d e
* b. t h r e a d w a s i n p o w e r s a v i n g m o d e w i t h n o s t a t e l o s s ,
* supervisor s t a t e l o s s o r h y p e r v i s o r s t a t e l o s s .
*
* Go b a c k t o n a p / s l e e p / w i n k l e m o d e a g a i n i f ( b ) i s t r u e .
* /
rlwinm. r11 ,r12 ,4 7 - 3 1 ,3 0 ,3 1 / * W a s i t i n p o w e r s a v i n g m o d e ? * /
beq 4 f / * N o , i t w a s n ;t */
/* Thread was in power saving mode. Go back to nap again. */
cmpwi r11 ,2
blt 3 f
/* Supervisor/Hypervisor state loss */
li r0 ,1
stb r0 ,P A C A _ N A P S T A T E L O S T ( r13 )
3 : bl m a c h i n e _ c h e c k _ q u e u e _ e v e n t
MACHINE_ C H E C K _ H A N D L E R _ W I N D U P
GET_ P A C A ( r13 )
ld r1 ,P A C A R 1 ( r13 )
/ *
* Check w h a t i d l e s t a t e t h i s C P U w a s i n a n d g o b a c k t o s a m e m o d e
* again.
* /
lbz r3 ,P A C A _ T H R E A D _ I D L E _ S T A T E ( r13 )
cmpwi r3 ,P N V _ T H R E A D _ N A P
bgt 1 0 f
2017-01-25 11:36:25 +03:00
IDLE_ S T A T E _ E N T E R _ S E Q _ N O R E T ( P P C _ N A P )
2016-09-21 10:43:31 +03:00
/* No return */
10 :
cmpwi r3 ,P N V _ T H R E A D _ S L E E P
bgt 2 f
2017-01-25 11:36:25 +03:00
IDLE_ S T A T E _ E N T E R _ S E Q _ N O R E T ( P P C _ S L E E P )
2016-09-21 10:43:31 +03:00
/* No return */
2 :
/ *
* Go b a c k t o w i n k l e . P l e a s e n o t e t h a t t h i s t h r e a d w a s w o k e n u p i n
* machine c h e c k f r o m w i n k l e a n d h a v e n o t r e s t o r e d t h e p e r - s u b c o r e
2016-11-02 09:57:01 +03:00
* state. H e n c e b e f o r e g o i n g b a c k t o w i n k l e , s e t l a s t b i t o f H S P R G 0
2016-09-21 10:43:31 +03:00
* to 1 . T h i s w i l l m a k e s u r e t h a t i f t h i s t h r e a d g e t s w o k e n u p
* again a t r e s e t v e c t o r 0 x10 0 t h e n i t w i l l g e t c h a n c e t o r e s t o r e
* the s u b c o r e s t a t e .
* /
ori r13 ,r13 ,1
SET_ P A C A ( r13 )
2017-01-25 11:36:25 +03:00
IDLE_ S T A T E _ E N T E R _ S E Q _ N O R E T ( P P C _ W I N K L E )
2016-09-21 10:43:31 +03:00
/* No return */
4 :
# endif
/ *
* Check i f w e a r e c o m i n g f r o m h y p e r v i s o r u s e r s p a c e . I f y e s t h e n w e
* continue i n h o s t k e r n e l i n V m o d e t o d e l i v e r t h e M C e v e n t .
* /
rldicl. r11 ,r12 ,4 ,6 3 / * S e e i f M C h i t w h i l e i n H V m o d e . * /
beq 5 f
andi. r11 ,r12 ,M S R _ P R / * S e e i f c o m i n g f r o m u s e r . * /
bne 9 f / * c o n t i n u e i n V m o d e i f w e a r e . * /
5 :
# ifdef C O N F I G _ K V M _ B O O K 3 S _ 6 4 _ H A N D L E R
/ *
* We a r e c o m i n g f r o m k e r n e l c o n t e x t . C h e c k i f w e a r e c o m i n g f r o m
* guest. i f y e s , t h e n w e c a n c o n t i n u e . W e w i l l f a l l t h r o u g h
* do_ k v m _ 2 0 0 - > k v m p p c _ i n t e r r u p t t o d e l i v e r t h e M C e v e n t t o g u e s t .
* /
lbz r11 ,H S T A T E _ I N _ G U E S T ( r13 )
cmpwi r11 ,0 / * C h e c k i f c o m i n g f r o m g u e s t * /
bne 9 f / * c o n t i n u e i f w e a r e . * /
# endif
/ *
* At t h i s p o i n t w e a r e n o t s u r e a b o u t w h a t c o n t e x t w e c o m e f r o m .
* Queue u p t h e M C E e v e n t a n d r e t u r n f r o m t h e i n t e r r u p t .
* But b e f o r e t h a t , c h e c k i f t h i s i s a n u n - r e c o v e r a b l e e x c e p t i o n .
* If y e s , t h e n s t a y o n e m e r g e n c y s t a c k a n d p a n i c .
* /
andi. r11 ,r12 ,M S R _ R I
bne 2 f
1 : mfspr r11 ,S P R N _ S R R 0
LOAD_ H A N D L E R ( r10 ,u n r e c o v e r _ m c e )
mtspr S P R N _ S R R 0 ,r10
ld r10 ,P A C A K M S R ( r13 )
/ *
* We a r e g o i n g d o w n . B u t t h e r e a r e c h a n c e s t h a t w e m i g h t g e t h i t b y
* another M C E d u r i n g p a n i c p a t h a n d w e m a y r u n i n t o u n s t a b l e s t a t e
* with n o w a y o u t . H e n c e , t u r n M E b i t o f f w h i l e g o i n g d o w n , s o t h a t
* when a n o t h e r M C E i s h i t d u r i n g p a n i c p a t h , s y s t e m w i l l c h e c k s t o p
* and h y p e r v i s o r w i l l g e t r e s t a r t e d c l e a n l y b y S P .
* /
li r3 ,M S R _ M E
andc r10 ,r10 ,r3 / * T u r n o f f M S R _ M E * /
mtspr S P R N _ S R R 1 ,r10
rfid
b .
2 :
/ *
* Check i f w e h a v e s u c c e s s f u l l y h a n d l e d / r e c o v e r e d f r o m e r r o r , i f n o t
* then s t a y o n e m e r g e n c y s t a c k a n d p a n i c .
* /
ld r3 ,R E S U L T ( r1 ) / * L o a d r e s u l t * /
cmpdi r3 ,0 / * s e e i f w e h a n d l e d M C E s u c c e s s f u l l y * /
beq 1 b / * i f ! h a n d l e d t h e n p a n i c * /
/ *
* Return f r o m M C i n t e r r u p t .
* Queue u p t h e M C E e v e n t s o t h a t w e c a n l o g i t l a t e r , w h i l e
* returning f r o m k e r n e l o r o p a l c a l l .
* /
bl m a c h i n e _ c h e c k _ q u e u e _ e v e n t
MACHINE_ C H E C K _ H A N D L E R _ W I N D U P
rfid
9 :
/* Deliver the machine check to host kernel in V mode. */
MACHINE_ C H E C K _ H A N D L E R _ W I N D U P
b m a c h i n e _ c h e c k _ p S e r i e s
EXC_ C O M M O N _ B E G I N ( u n r e c o v e r _ m c e )
/* Invoke machine_check_exception to print MCE event and panic. */
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl m a c h i n e _ c h e c k _ e x c e p t i o n
/ *
* We w i l l n o t r e a c h h e r e . E v e n i f w e d i d , t h e r e i s n o w a y o u t . C a l l
* unrecoverable_ e x c e p t i o n a n d d i e .
* /
1 : addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl u n r e c o v e r a b l e _ e x c e p t i o n
b 1 b
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L ( d a t a _ a c c e s s , 0 x30 0 , 0 x80 )
EXC_ V I R T ( d a t a _ a c c e s s , 0 x43 0 0 , 0 x80 , 0 x30 0 )
2016-09-21 10:43:32 +03:00
TRAMP_ K V M _ S K I P ( P A C A _ E X G E N , 0 x30 0 )
EXC_ C O M M O N _ B E G I N ( d a t a _ a c c e s s _ c o m m o n )
/ *
* Here r13 p o i n t s t o t h e p a c a , r9 c o n t a i n s t h e s a v e d C R ,
* SRR0 a n d S R R 1 a r e s a v e d i n r11 a n d r12 ,
* r9 - r13 a r e s a v e d i n p a c a - > e x g e n .
* /
mfspr r10 ,S P R N _ D A R
std r10 ,P A C A _ E X G E N + E X _ D A R ( r13 )
mfspr r10 ,S P R N _ D S I S R
stw r10 ,P A C A _ E X G E N + E X _ D S I S R ( r13 )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x30 0 , P A C A _ E X G E N )
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
ld r12 ,_ M S R ( r1 )
ld r3 ,P A C A _ E X G E N + E X _ D A R ( r13 )
lwz r4 ,P A C A _ E X G E N + E X _ D S I S R ( r13 )
li r5 ,0 x30 0
std r3 ,_ D A R ( r1 )
std r4 ,_ D S I S R ( r1 )
BEGIN_ M M U _ F T R _ S E C T I O N
b d o _ h a s h _ p a g e / * T r y t o h a n d l e a s h p t e f a u l t * /
MMU_ F T R _ S E C T I O N _ E L S E
b h a n d l e _ p a g e _ f a u l t
ALT_ M M U _ F T R _ S E C T I O N _ E N D _ I F C L R ( M M U _ F T R _ T Y P E _ R A D I X )
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ B E G I N ( d a t a _ a c c e s s _ s l b , 0 x38 0 , 0 x80 )
2011-04-05 07:59:58 +04:00
SET_ S C R A T C H 0 ( r13 )
powerpc: Save CFAR before branching in interrupt entry paths
Some of the interrupt vectors on 64-bit POWER server processors are
only 32 bytes long, which is not enough for the full first-level
interrupt handler. For these we currently just have a branch to an
out-of-line handler. However, this means that we corrupt the CFAR
(come-from address register) on POWER7 and later processors.
To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces:
EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR
is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We
then put EXCEPTION_PROLOG_0 in the short interrupt vectors before
we branch to the out-of-line handler, which contains the rest of the
first-level interrupt handler. To facilitate this, we define new
_OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc.
In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more
than 6 instructions, it was necessary to move the stores that move
the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and
to get rid of one of the two HMT_MEDIUM instructions. Previously
there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was
nop'd out on processors with the PPR (POWER7 and later), and then
another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside
__EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR.
Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally
and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although
this leaves it in for the interrupt vectors where there is room for
it.
Previously we had a handler for hypervisor maintenance interrupts at
0xe50, which doesn't leave enough room for the vector for hypervisor
emulation assist interrupts at 0xe40, since we need 8 instructions.
The 0xe50 vector was only used on POWER6, as the HMI vector was moved
to 0xe60 on POWER7. Since we don't support running in hypervisor mode
on POWER6, we just remove the handler at 0xe50.
This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0
instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD
from the relocation-on vectors (since any CPU that supports
relocation-on interrupts also has the PPR).
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-02-04 22:10:15 +04:00
EXCEPTION_ P R O L O G _ 0 ( P A C A _ E X S L B )
2016-09-30 12:43:18 +03:00
EXCEPTION_ P R O L O G _ 1 ( P A C A _ E X S L B , K V M T E S T _ P R , 0 x38 0 )
2009-06-03 01:17:38 +04:00
std r3 ,P A C A _ E X S L B + E X _ R 3 ( r13 )
mfspr r3 ,S P R N _ D A R
2011-06-29 04:18:26 +04:00
mfspr r12 ,S P R N _ S R R 1
powerpc/mm: Preserve CFAR value on SLB miss caused by access to bogus address
Currently, if userspace or the kernel accesses a completely bogus address,
for example with any of bits 46-59 set, we first take an SLB miss interrupt,
install a corresponding SLB entry with VSID 0, retry the instruction, then
take a DSI/ISI interrupt because there is no HPT entry mapping the address.
However, by the time of the second interrupt, the Come-From Address Register
(CFAR) has been overwritten by the rfid instruction at the end of the SLB
miss interrupt handler. Since bogus accesses can often be caused by a
function return after the stack has been overwritten, the CFAR value would
be very useful as it could indicate which function it was whose return had
led to the bogus address.
This patch adds code to create a full exception frame in the SLB miss handler
in the case of a bogus address, rather than inserting an SLB entry with a
zero VSID field. Then we call a new slb_miss_bad_addr() function in C code,
which delivers a signal for a user access or creates an oops for a kernel
access. In the latter case the oops message will show the CFAR value at the
time of the access.
In the case of the radix MMU, a segment miss interrupt indicates an access
outside the ranges mapped by the page tables. Previously this was handled
by the code for an unrecoverable SLB miss (one with MSR[RI] = 0), which is
not really correct. With this patch, we now handle these interrupts with
slb_miss_bad_addr(), which is much more consistent.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-09-02 14:49:21 +03:00
crset 4 * c r6 + e q
2009-06-03 01:17:38 +04:00
# ifndef C O N F I G _ R E L O C A T A B L E
2014-02-04 09:04:35 +04:00
b s l b _ m i s s _ r e a l m o d e
2009-06-03 01:17:38 +04:00
# else
/ *
2014-02-04 09:04:52 +04:00
* We c a n ' t j u s t u s e a d i r e c t b r a n c h t o s l b _ m i s s _ r e a l m o d e
2009-06-03 01:17:38 +04:00
* because t h e d i s t a n c e f r o m h e r e t o t h e r e d e p e n d s o n w h e r e
* the k e r n e l e n d s u p b e i n g p u t .
* /
mfctr r11
2014-02-04 09:04:52 +04:00
LOAD_ H A N D L E R ( r10 , s l b _ m i s s _ r e a l m o d e )
2009-06-03 01:17:38 +04:00
mtctr r10
bctr
# endif
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ E N D ( d a t a _ a c c e s s _ s l b , 0 x38 0 , 0 x80 )
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ B E G I N ( d a t a _ a c c e s s _ s l b , 0 x43 8 0 , 0 x80 )
2016-09-21 10:43:33 +03:00
SET_ S C R A T C H 0 ( r13 )
EXCEPTION_ P R O L O G _ 0 ( P A C A _ E X S L B )
EXCEPTION_ P R O L O G _ 1 ( P A C A _ E X S L B , N O T E S T , 0 x38 0 )
std r3 ,P A C A _ E X S L B + E X _ R 3 ( r13 )
mfspr r3 ,S P R N _ D A R
mfspr r12 ,S P R N _ S R R 1
crset 4 * c r6 + e q
# ifndef C O N F I G _ R E L O C A T A B L E
b s l b _ m i s s _ r e a l m o d e
# else
/ *
* We c a n ' t j u s t u s e a d i r e c t b r a n c h t o s l b _ m i s s _ r e a l m o d e
* because t h e d i s t a n c e f r o m h e r e t o t h e r e d e p e n d s o n w h e r e
* the k e r n e l e n d s u p b e i n g p u t .
* /
mfctr r11
LOAD_ H A N D L E R ( r10 , s l b _ m i s s _ r e a l m o d e )
mtctr r10
bctr
# endif
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ E N D ( d a t a _ a c c e s s _ s l b , 0 x43 8 0 , 0 x80 )
2016-09-21 10:43:33 +03:00
TRAMP_ K V M _ S K I P ( P A C A _ E X S L B , 0 x38 0 )
2016-12-06 04:41:12 +03:00
EXC_ R E A L ( i n s t r u c t i o n _ a c c e s s , 0 x40 0 , 0 x80 )
EXC_ V I R T ( i n s t r u c t i o n _ a c c e s s , 0 x44 0 0 , 0 x80 , 0 x40 0 )
2016-09-21 10:43:34 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x40 0 )
EXC_ C O M M O N _ B E G I N ( i n s t r u c t i o n _ a c c e s s _ c o m m o n )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x40 0 , P A C A _ E X G E N )
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
ld r12 ,_ M S R ( r1 )
ld r3 ,_ N I P ( r1 )
andis. r4 ,r12 ,0 x58 2 0
li r5 ,0 x40 0
std r3 ,_ D A R ( r1 )
std r4 ,_ D S I S R ( r1 )
BEGIN_ M M U _ F T R _ S E C T I O N
b d o _ h a s h _ p a g e / * T r y t o h a n d l e a s h p t e f a u l t * /
MMU_ F T R _ S E C T I O N _ E L S E
b h a n d l e _ p a g e _ f a u l t
ALT_ M M U _ F T R _ S E C T I O N _ E N D _ I F C L R ( M M U _ F T R _ T Y P E _ R A D I X )
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ B E G I N ( i n s t r u c t i o n _ a c c e s s _ s l b , 0 x48 0 , 0 x80 )
2011-04-05 07:59:58 +04:00
SET_ S C R A T C H 0 ( r13 )
powerpc: Save CFAR before branching in interrupt entry paths
Some of the interrupt vectors on 64-bit POWER server processors are
only 32 bytes long, which is not enough for the full first-level
interrupt handler. For these we currently just have a branch to an
out-of-line handler. However, this means that we corrupt the CFAR
(come-from address register) on POWER7 and later processors.
To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces:
EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR
is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We
then put EXCEPTION_PROLOG_0 in the short interrupt vectors before
we branch to the out-of-line handler, which contains the rest of the
first-level interrupt handler. To facilitate this, we define new
_OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc.
In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more
than 6 instructions, it was necessary to move the stores that move
the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and
to get rid of one of the two HMT_MEDIUM instructions. Previously
there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was
nop'd out on processors with the PPR (POWER7 and later), and then
another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside
__EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR.
Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally
and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although
this leaves it in for the interrupt vectors where there is room for
it.
Previously we had a handler for hypervisor maintenance interrupts at
0xe50, which doesn't leave enough room for the vector for hypervisor
emulation assist interrupts at 0xe40, since we need 8 instructions.
The 0xe50 vector was only used on POWER6, as the HMI vector was moved
to 0xe60 on POWER7. Since we don't support running in hypervisor mode
on POWER6, we just remove the handler at 0xe50.
This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0
instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD
from the relocation-on vectors (since any CPU that supports
relocation-on interrupts also has the PPR).
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-02-04 22:10:15 +04:00
EXCEPTION_ P R O L O G _ 0 ( P A C A _ E X S L B )
2016-09-30 12:43:18 +03:00
EXCEPTION_ P R O L O G _ 1 ( P A C A _ E X S L B , K V M T E S T _ P R , 0 x48 0 )
2009-06-03 01:17:38 +04:00
std r3 ,P A C A _ E X S L B + E X _ R 3 ( r13 )
mfspr r3 ,S P R N _ S R R 0 / * S R R 0 i s f a u l t i n g a d d r e s s * /
2011-06-29 04:18:26 +04:00
mfspr r12 ,S P R N _ S R R 1
powerpc/mm: Preserve CFAR value on SLB miss caused by access to bogus address
Currently, if userspace or the kernel accesses a completely bogus address,
for example with any of bits 46-59 set, we first take an SLB miss interrupt,
install a corresponding SLB entry with VSID 0, retry the instruction, then
take a DSI/ISI interrupt because there is no HPT entry mapping the address.
However, by the time of the second interrupt, the Come-From Address Register
(CFAR) has been overwritten by the rfid instruction at the end of the SLB
miss interrupt handler. Since bogus accesses can often be caused by a
function return after the stack has been overwritten, the CFAR value would
be very useful as it could indicate which function it was whose return had
led to the bogus address.
This patch adds code to create a full exception frame in the SLB miss handler
in the case of a bogus address, rather than inserting an SLB entry with a
zero VSID field. Then we call a new slb_miss_bad_addr() function in C code,
which delivers a signal for a user access or creates an oops for a kernel
access. In the latter case the oops message will show the CFAR value at the
time of the access.
In the case of the radix MMU, a segment miss interrupt indicates an access
outside the ranges mapped by the page tables. Previously this was handled
by the code for an unrecoverable SLB miss (one with MSR[RI] = 0), which is
not really correct. With this patch, we now handle these interrupts with
slb_miss_bad_addr(), which is much more consistent.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-09-02 14:49:21 +03:00
crclr 4 * c r6 + e q
2009-06-03 01:17:38 +04:00
# ifndef C O N F I G _ R E L O C A T A B L E
2014-02-04 09:04:35 +04:00
b s l b _ m i s s _ r e a l m o d e
2009-06-03 01:17:38 +04:00
# else
mfctr r11
2014-02-04 09:04:52 +04:00
LOAD_ H A N D L E R ( r10 , s l b _ m i s s _ r e a l m o d e )
2009-06-03 01:17:38 +04:00
mtctr r10
bctr
# endif
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ E N D ( i n s t r u c t i o n _ a c c e s s _ s l b , 0 x48 0 , 0 x80 )
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ B E G I N ( i n s t r u c t i o n _ a c c e s s _ s l b , 0 x44 8 0 , 0 x80 )
2016-09-21 10:43:35 +03:00
SET_ S C R A T C H 0 ( r13 )
EXCEPTION_ P R O L O G _ 0 ( P A C A _ E X S L B )
EXCEPTION_ P R O L O G _ 1 ( P A C A _ E X S L B , N O T E S T , 0 x48 0 )
std r3 ,P A C A _ E X S L B + E X _ R 3 ( r13 )
mfspr r3 ,S P R N _ S R R 0 / * S R R 0 i s f a u l t i n g a d d r e s s * /
mfspr r12 ,S P R N _ S R R 1
crclr 4 * c r6 + e q
# ifndef C O N F I G _ R E L O C A T A B L E
b s l b _ m i s s _ r e a l m o d e
# else
mfctr r11
LOAD_ H A N D L E R ( r10 , s l b _ m i s s _ r e a l m o d e )
mtctr r10
bctr
# endif
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ E N D ( i n s t r u c t i o n _ a c c e s s _ s l b , 0 x44 8 0 , 0 x80 )
2016-09-21 10:43:35 +03:00
TRAMP_ K V M ( P A C A _ E X S L B , 0 x48 0 )
/* This handler is used by both 0x380 and 0x480 slb miss interrupts */
EXC_ C O M M O N _ B E G I N ( s l b _ m i s s _ r e a l m o d e )
/ *
* r1 3 p o i n t s t o t h e P A C A , r9 c o n t a i n s t h e s a v e d C R ,
* r1 2 c o n t a i n t h e s a v e d S R R 1 , S R R 0 i s s t i l l r e a d y f o r r e t u r n
* r3 h a s t h e f a u l t i n g a d d r e s s
* r9 - r13 a r e s a v e d i n p a c a - > e x s l b .
* r3 i s s a v e d i n p a c a - > s l b _ r3
* cr6 . e q i s s e t f o r a D - S L B m i s s , c l e a r f o r a I - S L B m i s s
* We a s s u m e w e a r e n ' t g o i n g t o t a k e a n y e x c e p t i o n s d u r i n g t h i s
* procedure.
* /
mflr r10
# ifdef C O N F I G _ R E L O C A T A B L E
mtctr r11
# endif
stw r9 ,P A C A _ E X S L B + E X _ C C R ( r13 ) / * s a v e C R i n e x c . f r a m e * /
std r10 ,P A C A _ E X S L B + E X _ L R ( r13 ) / * s a v e L R * /
std r3 ,P A C A _ E X S L B + E X _ D A R ( r13 )
crset 4 * c r0 + e q
# ifdef C O N F I G _ P P C _ S T D _ M M U _ 6 4
BEGIN_ M M U _ F T R _ S E C T I O N
bl s l b _ a l l o c a t e _ r e a l m o d e
END_ M M U _ F T R _ S E C T I O N _ I F C L R ( M M U _ F T R _ T Y P E _ R A D I X )
# endif
ld r10 ,P A C A _ E X S L B + E X _ L R ( r13 )
ld r3 ,P A C A _ E X S L B + E X _ R 3 ( r13 )
lwz r9 ,P A C A _ E X S L B + E X _ C C R ( r13 ) / * g e t s a v e d C R * /
mtlr r10
beq 8 f / * i f b a d a d d r e s s , m a k e f u l l s t a c k f r a m e * /
andi. r10 ,r12 ,M S R _ R I / * c h e c k f o r u n r e c o v e r a b l e e x c e p t i o n * /
beq- 2 f
/* All done -- return from exception. */
.machine push
.machine " power4 "
mtcrf 0 x80 ,r9
mtcrf 0 x02 ,r9 / * I / D i n d i c a t i o n i s i n c r6 * /
mtcrf 0 x01 ,r9 / * s l b _ a l l o c a t e u s e s c r0 a n d c r7 * /
.machine pop
RESTORE_ P P R _ P A C A ( P A C A _ E X S L B , r9 )
ld r9 ,P A C A _ E X S L B + E X _ R 9 ( r13 )
ld r10 ,P A C A _ E X S L B + E X _ R 1 0 ( r13 )
ld r11 ,P A C A _ E X S L B + E X _ R 1 1 ( r13 )
ld r12 ,P A C A _ E X S L B + E X _ R 1 2 ( r13 )
ld r13 ,P A C A _ E X S L B + E X _ R 1 3 ( r13 )
rfid
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
2 : mfspr r11 ,S P R N _ S R R 0
LOAD_ H A N D L E R ( r10 ,u n r e c o v _ s l b )
mtspr S P R N _ S R R 0 ,r10
ld r10 ,P A C A K M S R ( r13 )
mtspr S P R N _ S R R 1 ,r10
rfid
b .
8 : mfspr r11 ,S P R N _ S R R 0
LOAD_ H A N D L E R ( r10 ,b a d _ a d d r _ s l b )
mtspr S P R N _ S R R 0 ,r10
ld r10 ,P A C A K M S R ( r13 )
mtspr S P R N _ S R R 1 ,r10
rfid
b .
EXC_ C O M M O N _ B E G I N ( u n r e c o v _ s l b )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x41 0 0 , P A C A _ E X S L B )
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
bl s a v e _ n v g p r s
1 : addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl u n r e c o v e r a b l e _ e x c e p t i o n
b 1 b
EXC_ C O M M O N _ B E G I N ( b a d _ a d d r _ s l b )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x38 0 , P A C A _ E X S L B )
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
ld r3 , P A C A _ E X S L B + E X _ D A R ( r13 )
std r3 , _ D A R ( r1 )
beq c r6 , 2 f
li r10 , 0 x48 0 / * f i x t r a p n u m b e r f o r I - S L B m i s s * /
std r10 , _ T R A P ( r1 )
2 : bl s a v e _ n v g p r s
addi r3 , r1 , S T A C K _ F R A M E _ O V E R H E A D
bl s l b _ m i s s _ b a d _ a d d r
b r e t _ f r o m _ e x c e p t
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ B E G I N ( h a r d w a r e _ i n t e r r u p t , 0 x50 0 , 0 x10 0 )
2011-04-05 08:27:11 +04:00
.globl _ i n t e r r u p t _ h v ;
hardware_interrupt_hv :
2011-04-05 08:20:31 +04:00
BEGIN_ F T R _ S E C T I O N
2016-09-30 12:43:18 +03:00
_ MASKABLE_ E X C E P T I O N _ P S E R I E S ( 0 x50 0 , h a r d w a r e _ i n t e r r u p t _ c o m m o n ,
2011-06-29 04:18:26 +04:00
EXC_ H V , S O F T E N _ T E S T _ H V )
KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 04:21:34 +04:00
FTR_ S E C T I O N _ E L S E
2016-09-30 12:43:18 +03:00
_ MASKABLE_ E X C E P T I O N _ P S E R I E S ( 0 x50 0 , h a r d w a r e _ i n t e r r u p t _ c o m m o n ,
powerpc/64: Include KVM guest test in all interrupt vectors
Currently, if HV KVM is configured but PR KVM isn't, we don't include
a test to see whether we were interrupted in KVM guest context for the
set of interrupts which get delivered directly to the guest by hardware
if they occur in the guest. This includes things like program
interrupts.
However, the recent bug where userspace could set the MSR for a VCPU
to have an illegal value in the TS field, and thus cause a TM Bad Thing
type of program interrupt on the hrfid that enters the guest, showed that
we can never be completely sure that these interrupts can never occur
in the guest entry/exit code. If one of these interrupts does happen
and we have HV KVM configured but not PR KVM, then we end up trying to
run the handler in the host with the MMU set to the guest MMU context,
which generally ends badly.
Thus, for robustness it is better to have the test in every interrupt
vector, so that if some way is found to trigger some interrupt in the
guest entry/exit path, we can handle it without immediately crashing
the host.
This means that the distinction between KVMTEST and KVMTEST_PR goes
away. Thus we delete KVMTEST_PR and associated macros and use KVMTEST
everywhere that we previously used either KVMTEST_PR or KVMTEST. It
also means that SOFTEN_TEST_HV_201 becomes the same as SOFTEN_TEST_PR,
so we deleted SOFTEN_TEST_HV_201 and use SOFTEN_TEST_PR instead.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-11-12 08:44:42 +03:00
EXC_ S T D , S O F T E N _ T E S T _ P R )
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 04:26:11 +04:00
ALT_ F T R _ S E C T I O N _ E N D _ I F S E T ( C P U _ F T R _ H V M O D E | C P U _ F T R _ A R C H _ 2 0 6 )
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ E N D ( h a r d w a r e _ i n t e r r u p t , 0 x50 0 , 0 x10 0 )
2016-09-30 12:43:18 +03:00
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ B E G I N ( h a r d w a r e _ i n t e r r u p t , 0 x45 0 0 , 0 x10 0 )
2016-09-21 10:43:36 +03:00
.globl _ i n t e r r u p t _ r e l o n _ h v ;
hardware_interrupt_relon_hv :
BEGIN_ F T R _ S E C T I O N
_ MASKABLE_ R E L O N _ E X C E P T I O N _ P S E R I E S ( 0 x50 0 , h a r d w a r e _ i n t e r r u p t _ c o m m o n , E X C _ H V , S O F T E N _ T E S T _ H V )
FTR_ S E C T I O N _ E L S E
_ MASKABLE_ R E L O N _ E X C E P T I O N _ P S E R I E S ( 0 x50 0 , h a r d w a r e _ i n t e r r u p t _ c o m m o n , E X C _ S T D , S O F T E N _ T E S T _ P R )
ALT_ F T R _ S E C T I O N _ E N D _ I F S E T ( C P U _ F T R _ H V M O D E )
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ E N D ( h a r d w a r e _ i n t e r r u p t , 0 x45 0 0 , 0 x10 0 )
2016-09-21 10:43:36 +03:00
2016-12-21 21:29:26 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x50 0 )
TRAMP_ K V M _ H V ( P A C A _ E X G E N , 0 x50 0 )
2016-09-21 10:43:36 +03:00
EXC_ C O M M O N _ A S Y N C ( h a r d w a r e _ i n t e r r u p t _ c o m m o n , 0 x50 0 , d o _ I R Q )
2016-12-06 04:41:12 +03:00
EXC_ R E A L ( a l i g n m e n t , 0 x60 0 , 0 x10 0 )
EXC_ V I R T ( a l i g n m e n t , 0 x46 0 0 , 0 x10 0 , 0 x60 0 )
2016-09-30 12:43:18 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x60 0 )
2016-09-21 10:43:37 +03:00
EXC_ C O M M O N _ B E G I N ( a l i g n m e n t _ c o m m o n )
mfspr r10 ,S P R N _ D A R
std r10 ,P A C A _ E X G E N + E X _ D A R ( r13 )
mfspr r10 ,S P R N _ D S I S R
stw r10 ,P A C A _ E X G E N + E X _ D S I S R ( r13 )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x60 0 , P A C A _ E X G E N )
ld r3 ,P A C A _ E X G E N + E X _ D A R ( r13 )
lwz r4 ,P A C A _ E X G E N + E X _ D S I S R ( r13 )
std r3 ,_ D A R ( r1 )
std r4 ,_ D S I S R ( r1 )
bl s a v e _ n v g p r s
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl a l i g n m e n t _ e x c e p t i o n
b r e t _ f r o m _ e x c e p t
2016-09-30 12:43:18 +03:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L ( p r o g r a m _ c h e c k , 0 x70 0 , 0 x10 0 )
EXC_ V I R T ( p r o g r a m _ c h e c k , 0 x47 0 0 , 0 x10 0 , 0 x70 0 )
2016-09-30 12:43:18 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x70 0 )
2016-09-21 10:43:38 +03:00
EXC_ C O M M O N _ B E G I N ( p r o g r a m _ c h e c k _ c o m m o n )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x70 0 , P A C A _ E X G E N )
bl s a v e _ n v g p r s
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl p r o g r a m _ c h e c k _ e x c e p t i o n
b r e t _ f r o m _ e x c e p t
2011-06-29 04:18:26 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L ( f p _ u n a v a i l a b l e , 0 x80 0 , 0 x10 0 )
EXC_ V I R T ( f p _ u n a v a i l a b l e , 0 x48 0 0 , 0 x10 0 , 0 x80 0 )
2016-09-30 12:43:18 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x80 0 )
2016-09-21 10:43:39 +03:00
EXC_ C O M M O N _ B E G I N ( f p _ u n a v a i l a b l e _ c o m m o n )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x80 0 , P A C A _ E X G E N )
bne 1 f / * i f f r o m u s e r , j u s t l o a d i t u p * /
bl s a v e _ n v g p r s
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl k e r n e l _ f p _ u n a v a i l a b l e _ e x c e p t i o n
BUG_ O P C O D E
1 :
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
BEGIN_ F T R _ S E C T I O N
/ * Test i f 2 T M s t a t e b i t s a r e z e r o . I f n o n - z e r o ( i e . u s e r s p a c e w a s i n
* transaction) , g o d o T M s t u f f
* /
rldicl. r0 , r12 , ( 6 4 - M S R _ T S _ L G ) , ( 6 4 - 2 )
bne- 2 f
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ T M )
# endif
bl l o a d _ u p _ f p u
b f a s t _ e x c e p t i o n _ r e t u r n
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
2 : /* User process was in a transaction */
bl s a v e _ n v g p r s
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl f p _ u n a v a i l a b l e _ t m
b r e t _ f r o m _ e x c e p t
# endif
2011-04-05 08:20:31 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ M A S K A B L E ( d e c r e m e n t e r , 0 x90 0 , 0 x80 )
EXC_ V I R T _ M A S K A B L E ( d e c r e m e n t e r , 0 x49 0 0 , 0 x80 , 0 x90 0 )
2016-09-21 10:43:40 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x90 0 )
EXC_ C O M M O N _ A S Y N C ( d e c r e m e n t e r _ c o m m o n , 0 x90 0 , t i m e r _ i n t e r r u p t )
powerpc: Fix "attempt to move .org backwards" error
Building a 64-bit powerpc kernel with PR KVM enabled currently gives
this error:
AS arch/powerpc/kernel/head_64.o
arch/powerpc/kernel/exceptions-64s.S: Assembler messages:
arch/powerpc/kernel/exceptions-64s.S:258: Error: attempt to move .org backwards
make[2]: *** [arch/powerpc/kernel/head_64.o] Error 1
This happens because the MASKABLE_EXCEPTION_PSERIES macro turns into
33 instructions, but we only have space for 32 at the decrementer
interrupt vector (from 0x900 to 0x980).
In the code generated by the MASKABLE_EXCEPTION_PSERIES macro, we
currently have two instances of the HMT_MEDIUM macro, which has the
effect of setting the SMT thread priority to medium. One is the
first instruction, and is overwritten by a no-op on processors where
we save the PPR (processor priority register), that is, POWER7 or
later. The other is after we have saved the PPR.
In order to reduce the code at 0x900 by one instruction, we omit the
first HMT_MEDIUM. On processors without SMT this will have no effect
since HMT_MEDIUM is a no-op there. On POWER5 and RS64 machines this
will mean that the first few instructions take a little longer in the
case where a decrementer interrupt occurs when the hardware thread is
running at low SMT priority. On POWER6 and later machines, the
hardware automatically boosts the thread priority when a decrementer
interrupt is taken if the thread priority was below medium, so this
change won't make any difference.
The alternative would be to branch out of line after saving the CFAR.
However, that would incur an extra overhead on all processors, whereas
the approach adopted here only adds overhead on older threaded processors.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-04-25 21:51:40 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ H V ( h d e c r e m e n t e r , 0 x98 0 , 0 x80 )
EXC_ V I R T _ H V ( h d e c r e m e n t e r , 0 x49 8 0 , 0 x80 , 0 x98 0 )
2016-09-21 10:43:41 +03:00
TRAMP_ K V M _ H V ( P A C A _ E X G E N , 0 x98 0 )
EXC_ C O M M O N ( h d e c r e m e n t e r _ c o m m o n , 0 x98 0 , h d e c _ i n t e r r u p t )
2011-04-05 08:20:31 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ M A S K A B L E ( d o o r b e l l _ s u p e r , 0 x a00 , 0 x10 0 )
EXC_ V I R T _ M A S K A B L E ( d o o r b e l l _ s u p e r , 0 x4 a00 , 0 x10 0 , 0 x a00 )
2016-09-30 12:43:18 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x a00 )
2016-09-21 10:43:42 +03:00
# ifdef C O N F I G _ P P C _ D O O R B E L L
EXC_ C O M M O N _ A S Y N C ( d o o r b e l l _ s u p e r _ c o m m o n , 0 x a00 , d o o r b e l l _ e x c e p t i o n )
# else
EXC_ C O M M O N _ A S Y N C ( d o o r b e l l _ s u p e r _ c o m m o n , 0 x a00 , u n k n o w n _ e x c e p t i o n )
# endif
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L ( t r a p _ 0 b , 0 x b00 , 0 x10 0 )
EXC_ V I R T ( t r a p _ 0 b , 0 x4 b00 , 0 x10 0 , 0 x b00 )
2016-09-30 12:43:18 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x b00 )
2016-09-21 10:43:43 +03:00
EXC_ C O M M O N ( t r a p _ 0 b _ c o m m o n , 0 x b00 , u n k n o w n _ e x c e p t i o n )
2017-01-30 13:21:40 +03:00
# ifdef C O N F I G _ K V M _ B O O K 3 S _ 6 4 _ H A N D L E R
/ *
* If C O N F I G _ K V M _ B O O K 3 S _ 6 4 _ H A N D L E R i s s e t , s a v e t h e P P R ( o n s y s t e m s
* that s u p p o r t i t ) b e f o r e c h a n g i n g t o H M T _ M E D I U M . T h a t a l l o w s t h e K V M
* code t o s a v e t h a t v a l u e i n t o t h e g u e s t s t a t e ( i t i s t h e g u e s t ' s P P R
* value) . O t h e r w i s e j u s t c h a n g e t o H M T _ M E D I U M a s u s e r s p a c e h a s
* already s a v e d t h e P P R .
* /
# define S Y S C A L L _ K V M T E S T \
SET_ S C R A T C H 0 ( r13 ) ; \
GET_ P A C A ( r13 ) ; \
std r9 ,P A C A _ E X G E N + E X _ R 9 ( r13 ) ; \
OPT_ G E T _ S P R ( r9 , S P R N _ P P R , C P U _ F T R _ H A S _ P P R ) ; \
HMT_ M E D I U M ; \
std r10 ,P A C A _ E X G E N + E X _ R 1 0 ( r13 ) ; \
OPT_ S A V E _ R E G _ T O _ P A C A ( P A C A _ E X G E N + E X _ P P R , r9 , C P U _ F T R _ H A S _ P P R ) ; \
mfcr r9 ; \
KVMTEST_ P R ( 0 x c00 ) ; \
GET_ S C R A T C H 0 ( r13 )
# else
# define S Y S C A L L _ K V M T E S T \
HMT_ M E D I U M
# endif
2016-10-13 05:17:14 +03:00
# define L O A D _ S Y S C A L L _ H A N D L E R ( r e g ) \
_ _ LOAD_ H A N D L E R ( r e g , s y s t e m _ c a l l _ c o m m o n )
2016-09-21 10:43:44 +03:00
/* Syscall routine is used twice, in reloc-off and reloc-on paths */
# define S Y S C A L L _ P S E R I E S _ 1 \
BEGIN_ F T R _ S E C T I O N \
cmpdi r0 ,0 x1 e b e ; \
beq- 1 f ; \
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ R E A L _ L E ) \
mr r9 ,r13 ; \
GET_ P A C A ( r13 ) ; \
mfspr r11 ,S P R N _ S R R 0 ; \
0 :
# define S Y S C A L L _ P S E R I E S _ 2 _ R F I D \
mfspr r12 ,S P R N _ S R R 1 ; \
LOAD_ S Y S C A L L _ H A N D L E R ( r10 ) ; \
mtspr S P R N _ S R R 0 ,r10 ; \
ld r10 ,P A C A K M S R ( r13 ) ; \
mtspr S P R N _ S R R 1 ,r10 ; \
rfid ; \
b . ; /* prevent speculative execution */
# define S Y S C A L L _ P S E R I E S _ 3 \
/* Fast LE/BE switch system call */ \
1 : mfspr r12 ,S P R N _ S R R 1 ; \
xori r12 ,r12 ,M S R _ L E ; \
mtspr S P R N _ S R R 1 ,r12 ; \
rfid ; /* return to userspace */ \
b . ; /* prevent speculative execution */
# if d e f i n e d ( C O N F I G _ R E L O C A T A B L E )
/ *
* We c a n ' t b r a n c h d i r e c t l y s o w e d o i t v i a t h e C T R w h i c h
* is v o l a t i l e a c r o s s s y s t e m c a l l s .
* /
# define S Y S C A L L _ P S E R I E S _ 2 _ D I R E C T \
LOAD_ S Y S C A L L _ H A N D L E R ( r12 ) ; \
mtctr r12 ; \
mfspr r12 ,S P R N _ S R R 1 ; \
li r10 ,M S R _ R I ; \
mtmsrd r10 ,1 ; \
bctr ;
# else
/* We can branch directly */
# define S Y S C A L L _ P S E R I E S _ 2 _ D I R E C T \
mfspr r12 ,S P R N _ S R R 1 ; \
li r10 ,M S R _ R I ; \
mtmsrd r10 ,1 ; /* Set RI (EE=0) */ \
b s y s t e m _ c a l l _ c o m m o n ;
# endif
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ B E G I N ( s y s t e m _ c a l l , 0 x c00 , 0 x10 0 )
2017-01-30 13:21:40 +03:00
SYSCALL_ K V M T E S T
2012-11-02 10:16:01 +04:00
SYSCALL_ P S E R I E S _ 1
SYSCALL_ P S E R I E S _ 2 _ R F I D
SYSCALL_ P S E R I E S _ 3
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ E N D ( s y s t e m _ c a l l , 0 x c00 , 0 x10 0 )
2016-09-30 12:43:18 +03:00
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ B E G I N ( s y s t e m _ c a l l , 0 x4 c00 , 0 x10 0 )
2017-01-30 13:21:40 +03:00
SYSCALL_ K V M T E S T
2016-09-21 10:43:44 +03:00
SYSCALL_ P S E R I E S _ 1
SYSCALL_ P S E R I E S _ 2 _ D I R E C T
SYSCALL_ P S E R I E S _ 3
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ E N D ( s y s t e m _ c a l l , 0 x4 c00 , 0 x10 0 )
2016-09-21 10:43:44 +03:00
2016-09-30 12:43:18 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x c00 )
2016-09-21 10:43:44 +03:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L ( s i n g l e _ s t e p , 0 x d00 , 0 x10 0 )
EXC_ V I R T ( s i n g l e _ s t e p , 0 x4 d00 , 0 x10 0 , 0 x d00 )
2016-09-30 12:43:18 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x d00 )
2016-09-21 10:43:45 +03:00
EXC_ C O M M O N ( s i n g l e _ s t e p _ c o m m o n , 0 x d00 , s i n g l e _ s t e p _ e x c e p t i o n )
2011-06-29 04:18:26 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ O O L _ H V ( h _ d a t a _ s t o r a g e , 0 x e 0 0 , 0 x20 )
2017-02-14 09:18:29 +03:00
EXC_ V I R T _ O O L _ H V ( h _ d a t a _ s t o r a g e , 0 x4 e 0 0 , 0 x20 , 0 x e 0 0 )
2016-09-21 10:43:46 +03:00
TRAMP_ K V M _ H V _ S K I P ( P A C A _ E X G E N , 0 x e 0 0 )
EXC_ C O M M O N _ B E G I N ( h _ d a t a _ s t o r a g e _ c o m m o n )
mfspr r10 ,S P R N _ H D A R
std r10 ,P A C A _ E X G E N + E X _ D A R ( r13 )
mfspr r10 ,S P R N _ H D S I S R
stw r10 ,P A C A _ E X G E N + E X _ D S I S R ( r13 )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x e 0 0 , P A C A _ E X G E N )
bl s a v e _ n v g p r s
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl u n k n o w n _ e x c e p t i o n
b r e t _ f r o m _ e x c e p t
powerpc: Save CFAR before branching in interrupt entry paths
Some of the interrupt vectors on 64-bit POWER server processors are
only 32 bytes long, which is not enough for the full first-level
interrupt handler. For these we currently just have a branch to an
out-of-line handler. However, this means that we corrupt the CFAR
(come-from address register) on POWER7 and later processors.
To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces:
EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR
is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We
then put EXCEPTION_PROLOG_0 in the short interrupt vectors before
we branch to the out-of-line handler, which contains the rest of the
first-level interrupt handler. To facilitate this, we define new
_OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc.
In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more
than 6 instructions, it was necessary to move the stores that move
the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and
to get rid of one of the two HMT_MEDIUM instructions. Previously
there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was
nop'd out on processors with the PPR (POWER7 and later), and then
another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside
__EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR.
Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally
and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although
this leaves it in for the interrupt vectors where there is room for
it.
Previously we had a handler for hypervisor maintenance interrupts at
0xe50, which doesn't leave enough room for the vector for hypervisor
emulation assist interrupts at 0xe40, since we need 8 instructions.
The 0xe50 vector was only used on POWER6, as the HMI vector was moved
to 0xe60 on POWER7. Since we don't support running in hypervisor mode
on POWER6, we just remove the handler at 0xe50.
This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0
instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD
from the relocation-on vectors (since any CPU that supports
relocation-on interrupts also has the PPR).
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-02-04 22:10:15 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ O O L _ H V ( h _ i n s t r _ s t o r a g e , 0 x e 2 0 , 0 x20 )
2017-02-14 09:18:29 +03:00
EXC_ V I R T _ O O L _ H V ( h _ i n s t r _ s t o r a g e , 0 x4 e 2 0 , 0 x20 , 0 x e 2 0 )
2016-09-21 10:43:47 +03:00
TRAMP_ K V M _ H V ( P A C A _ E X G E N , 0 x e 2 0 )
EXC_ C O M M O N ( h _ i n s t r _ s t o r a g e _ c o m m o n , 0 x e 2 0 , u n k n o w n _ e x c e p t i o n )
powerpc: Save CFAR before branching in interrupt entry paths
Some of the interrupt vectors on 64-bit POWER server processors are
only 32 bytes long, which is not enough for the full first-level
interrupt handler. For these we currently just have a branch to an
out-of-line handler. However, this means that we corrupt the CFAR
(come-from address register) on POWER7 and later processors.
To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces:
EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR
is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We
then put EXCEPTION_PROLOG_0 in the short interrupt vectors before
we branch to the out-of-line handler, which contains the rest of the
first-level interrupt handler. To facilitate this, we define new
_OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc.
In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more
than 6 instructions, it was necessary to move the stores that move
the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and
to get rid of one of the two HMT_MEDIUM instructions. Previously
there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was
nop'd out on processors with the PPR (POWER7 and later), and then
another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside
__EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR.
Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally
and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although
this leaves it in for the interrupt vectors where there is room for
it.
Previously we had a handler for hypervisor maintenance interrupts at
0xe50, which doesn't leave enough room for the vector for hypervisor
emulation assist interrupts at 0xe40, since we need 8 instructions.
The 0xe50 vector was only used on POWER6, as the HMI vector was moved
to 0xe60 on POWER7. Since we don't support running in hypervisor mode
on POWER6, we just remove the handler at 0xe50.
This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0
instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD
from the relocation-on vectors (since any CPU that supports
relocation-on interrupts also has the PPR).
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-02-04 22:10:15 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ O O L _ H V ( e m u l a t i o n _ a s s i s t , 0 x e 4 0 , 0 x20 )
EXC_ V I R T _ O O L _ H V ( e m u l a t i o n _ a s s i s t , 0 x4 e 4 0 , 0 x20 , 0 x e 4 0 )
2016-09-21 10:43:48 +03:00
TRAMP_ K V M _ H V ( P A C A _ E X G E N , 0 x e 4 0 )
EXC_ C O M M O N ( e m u l a t i o n _ a s s i s t _ c o m m o n , 0 x e 4 0 , e m u l a t i o n _ a s s i s t _ i n t e r r u p t )
powerpc: Save CFAR before branching in interrupt entry paths
Some of the interrupt vectors on 64-bit POWER server processors are
only 32 bytes long, which is not enough for the full first-level
interrupt handler. For these we currently just have a branch to an
out-of-line handler. However, this means that we corrupt the CFAR
(come-from address register) on POWER7 and later processors.
To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces:
EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR
is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We
then put EXCEPTION_PROLOG_0 in the short interrupt vectors before
we branch to the out-of-line handler, which contains the rest of the
first-level interrupt handler. To facilitate this, we define new
_OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc.
In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more
than 6 instructions, it was necessary to move the stores that move
the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and
to get rid of one of the two HMT_MEDIUM instructions. Previously
there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was
nop'd out on processors with the PPR (POWER7 and later), and then
another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside
__EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR.
Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally
and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although
this leaves it in for the interrupt vectors where there is room for
it.
Previously we had a handler for hypervisor maintenance interrupts at
0xe50, which doesn't leave enough room for the vector for hypervisor
emulation assist interrupts at 0xe40, since we need 8 instructions.
The 0xe50 vector was only used on POWER6, as the HMI vector was moved
to 0xe60 on POWER7. Since we don't support running in hypervisor mode
on POWER6, we just remove the handler at 0xe50.
This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0
instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD
from the relocation-on vectors (since any CPU that supports
relocation-on interrupts also has the PPR).
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-02-04 22:10:15 +04:00
2016-09-21 10:44:07 +03:00
/ *
* hmi_ e x c e p t i o n t r a m p o l i n e i s a s p e c i a l c a s e . I t j u m p s t o h m i _ e x c e p t i o n _ e a r l y
* first, a n d t h e n e v e n t a u l l y f r o m t h e r e t o t h e t r a m p o l i n e t o g e t i n t o v i r t u a l
* mode.
* /
2016-12-06 04:41:12 +03:00
_ _ EXC_ R E A L _ O O L _ H V _ D I R E C T ( h m i _ e x c e p t i o n , 0 x e 6 0 , 0 x20 , h m i _ e x c e p t i o n _ e a r l y )
2016-12-06 04:40:15 +03:00
_ _ TRAMP_ R E A L _ O O L _ M A S K A B L E _ H V ( h m i _ e x c e p t i o n , 0 x e 6 0 )
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ N O N E ( 0 x4 e 6 0 , 0 x20 )
2016-09-21 10:43:49 +03:00
TRAMP_ K V M _ H V ( P A C A _ E X G E N , 0 x e 6 0 )
TRAMP_ R E A L _ B E G I N ( h m i _ e x c e p t i o n _ e a r l y )
EXCEPTION_ P R O L O G _ 1 ( P A C A _ E X G E N , K V M T E S T _ H V , 0 x e 6 0 )
mr r10 ,r1 / * S a v e r1 * /
ld r1 ,P A C A E M E R G S P ( r13 ) / * U s e e m e r g e n c y s t a c k * /
subi r1 ,r1 ,I N T _ F R A M E _ S I Z E / * a l l o c s t a c k f r a m e * /
std r9 ,_ C C R ( r1 ) / * s a v e C R i n s t a c k f r a m e * /
mfspr r11 ,S P R N _ H S R R 0 / * S a v e H S R R 0 * /
std r11 ,_ N I P ( r1 ) / * s a v e H S R R 0 i n s t a c k f r a m e * /
mfspr r12 ,S P R N _ H S R R 1 / * S a v e S R R 1 * /
std r12 ,_ M S R ( r1 ) / * s a v e S R R 1 i n s t a c k f r a m e * /
std r10 ,0 ( r1 ) / * m a k e s t a c k c h a i n p o i n t e r * /
std r0 ,G P R 0 ( r1 ) / * s a v e r0 i n s t a c k f r a m e * /
std r10 ,G P R 1 ( r1 ) / * s a v e r1 i n s t a c k f r a m e * /
EXCEPTION_ P R O L O G _ C O M M O N _ 2 ( P A C A _ E X G E N )
EXCEPTION_ P R O L O G _ C O M M O N _ 3 ( 0 x e 6 0 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
2017-01-27 07:24:33 +03:00
BRANCH_ L I N K _ T O _ F A R ( r4 , h m i _ e x c e p t i o n _ r e a l m o d e )
2016-09-21 10:43:49 +03:00
/* Windup the stack. */
/* Move original HSRR0 and HSRR1 into the respective regs */
ld r9 ,_ M S R ( r1 )
mtspr S P R N _ H S R R 1 ,r9
ld r3 ,_ N I P ( r1 )
mtspr S P R N _ H S R R 0 ,r3
ld r9 ,_ C T R ( r1 )
mtctr r9
ld r9 ,_ X E R ( r1 )
mtxer r9
ld r9 ,_ L I N K ( r1 )
mtlr r9
REST_ G P R ( 0 , r1 )
REST_ 8 G P R S ( 2 , r1 )
REST_ G P R ( 1 0 , r1 )
ld r11 ,_ C C R ( r1 )
mtcr r11
REST_ G P R ( 1 1 , r1 )
REST_ 2 G P R S ( 1 2 , r1 )
/* restore original r1. */
ld r1 ,G P R 1 ( r1 )
/ *
* Go t o v i r t u a l m o d e a n d p u l l t h e H M I e v e n t i n f o r m a t i o n f r o m
* firmware.
* /
.globl hmi_exception_after_realmode
hmi_exception_after_realmode :
SET_ S C R A T C H 0 ( r13 )
EXCEPTION_ P R O L O G _ 0 ( P A C A _ E X G E N )
b t r a m p _ r e a l _ h m i _ e x c e p t i o n
EXC_ C O M M O N _ A S Y N C ( h m i _ e x c e p t i o n _ c o m m o n , 0 x e 6 0 , h a n d l e _ h m i _ e x c e p t i o n )
powerpc: Save CFAR before branching in interrupt entry paths
Some of the interrupt vectors on 64-bit POWER server processors are
only 32 bytes long, which is not enough for the full first-level
interrupt handler. For these we currently just have a branch to an
out-of-line handler. However, this means that we corrupt the CFAR
(come-from address register) on POWER7 and later processors.
To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces:
EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR
is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We
then put EXCEPTION_PROLOG_0 in the short interrupt vectors before
we branch to the out-of-line handler, which contains the rest of the
first-level interrupt handler. To facilitate this, we define new
_OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc.
In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more
than 6 instructions, it was necessary to move the stores that move
the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and
to get rid of one of the two HMT_MEDIUM instructions. Previously
there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was
nop'd out on processors with the PPR (POWER7 and later), and then
another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside
__EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR.
Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally
and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although
this leaves it in for the interrupt vectors where there is room for
it.
Previously we had a handler for hypervisor maintenance interrupts at
0xe50, which doesn't leave enough room for the vector for hypervisor
emulation assist interrupts at 0xe40, since we need 8 instructions.
The 0xe50 vector was only used on POWER6, as the HMI vector was moved
to 0xe60 on POWER7. Since we don't support running in hypervisor mode
on POWER6, we just remove the handler at 0xe50.
This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0
instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD
from the relocation-on vectors (since any CPU that supports
relocation-on interrupts also has the PPR).
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-02-04 22:10:15 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ O O L _ M A S K A B L E _ H V ( h _ d o o r b e l l , 0 x e 8 0 , 0 x20 )
EXC_ V I R T _ O O L _ M A S K A B L E _ H V ( h _ d o o r b e l l , 0 x4 e 8 0 , 0 x20 , 0 x e 8 0 )
2016-09-21 10:43:50 +03:00
TRAMP_ K V M _ H V ( P A C A _ E X G E N , 0 x e 8 0 )
# ifdef C O N F I G _ P P C _ D O O R B E L L
EXC_ C O M M O N _ A S Y N C ( h _ d o o r b e l l _ c o m m o n , 0 x e 8 0 , d o o r b e l l _ e x c e p t i o n )
# else
EXC_ C O M M O N _ A S Y N C ( h _ d o o r b e l l _ c o m m o n , 0 x e 8 0 , u n k n o w n _ e x c e p t i o n )
# endif
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ O O L _ M A S K A B L E _ H V ( h _ v i r t _ i r q , 0 x e a0 , 0 x20 )
EXC_ V I R T _ O O L _ M A S K A B L E _ H V ( h _ v i r t _ i r q , 0 x4 e a0 , 0 x20 , 0 x e a0 )
2016-09-21 10:43:51 +03:00
TRAMP_ K V M _ H V ( P A C A _ E X G E N , 0 x e a0 )
EXC_ C O M M O N _ A S Y N C ( h _ v i r t _ i r q _ c o m m o n , 0 x e a0 , d o _ I R Q )
2016-07-08 09:37:06 +03:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ N O N E ( 0 x e c0 , 0 x20 )
EXC_ V I R T _ N O N E ( 0 x4 e c0 , 0 x20 )
EXC_ R E A L _ N O N E ( 0 x e e 0 , 0 x20 )
EXC_ V I R T _ N O N E ( 0 x4 e e 0 , 0 x20 )
2016-09-21 10:43:52 +03:00
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ O O L ( p e r f o r m a n c e _ m o n i t o r , 0 x f00 , 0 x20 )
EXC_ V I R T _ O O L ( p e r f o r m a n c e _ m o n i t o r , 0 x4 f00 , 0 x20 , 0 x f00 )
2016-09-21 10:43:53 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x f00 )
EXC_ C O M M O N _ A S Y N C ( p e r f o r m a n c e _ m o n i t o r _ c o m m o n , 0 x f00 , p e r f o r m a n c e _ m o n i t o r _ e x c e p t i o n )
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ O O L ( a l t i v e c _ u n a v a i l a b l e , 0 x f20 , 0 x20 )
EXC_ V I R T _ O O L ( a l t i v e c _ u n a v a i l a b l e , 0 x4 f20 , 0 x20 , 0 x f20 )
2016-09-21 10:43:54 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x f20 )
EXC_ C O M M O N _ B E G I N ( a l t i v e c _ u n a v a i l a b l e _ c o m m o n )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x f20 , P A C A _ E X G E N )
# ifdef C O N F I G _ A L T I V E C
BEGIN_ F T R _ S E C T I O N
beq 1 f
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
BEGIN_ F T R _ S E C T I O N _ N E S T E D ( 6 9 )
/ * Test i f 2 T M s t a t e b i t s a r e z e r o . I f n o n - z e r o ( i e . u s e r s p a c e w a s i n
* transaction) , g o d o T M s t u f f
* /
rldicl. r0 , r12 , ( 6 4 - M S R _ T S _ L G ) , ( 6 4 - 2 )
bne- 2 f
END_ F T R _ S E C T I O N _ N E S T E D ( C P U _ F T R _ T M , C P U _ F T R _ T M , 6 9 )
# endif
bl l o a d _ u p _ a l t i v e c
b f a s t _ e x c e p t i o n _ r e t u r n
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
2 : /* User process was in a transaction */
bl s a v e _ n v g p r s
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl a l t i v e c _ u n a v a i l a b l e _ t m
b r e t _ f r o m _ e x c e p t
# endif
1 :
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ A L T I V E C )
# endif
bl s a v e _ n v g p r s
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl a l t i v e c _ u n a v a i l a b l e _ e x c e p t i o n
b r e t _ f r o m _ e x c e p t
2009-06-03 01:17:38 +04:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ O O L ( v s x _ u n a v a i l a b l e , 0 x f40 , 0 x20 )
EXC_ V I R T _ O O L ( v s x _ u n a v a i l a b l e , 0 x4 f40 , 0 x20 , 0 x f40 )
2016-09-21 10:43:55 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x f40 )
EXC_ C O M M O N _ B E G I N ( v s x _ u n a v a i l a b l e _ c o m m o n )
EXCEPTION_ P R O L O G _ C O M M O N ( 0 x f40 , P A C A _ E X G E N )
# ifdef C O N F I G _ V S X
BEGIN_ F T R _ S E C T I O N
beq 1 f
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
BEGIN_ F T R _ S E C T I O N _ N E S T E D ( 6 9 )
/ * Test i f 2 T M s t a t e b i t s a r e z e r o . I f n o n - z e r o ( i e . u s e r s p a c e w a s i n
* transaction) , g o d o T M s t u f f
* /
rldicl. r0 , r12 , ( 6 4 - M S R _ T S _ L G ) , ( 6 4 - 2 )
bne- 2 f
END_ F T R _ S E C T I O N _ N E S T E D ( C P U _ F T R _ T M , C P U _ F T R _ T M , 6 9 )
# endif
b l o a d _ u p _ v s x
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
2 : /* User process was in a transaction */
bl s a v e _ n v g p r s
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl v s x _ u n a v a i l a b l e _ t m
b r e t _ f r o m _ e x c e p t
# endif
1 :
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ V S X )
# endif
bl s a v e _ n v g p r s
RECONCILE_ I R Q _ S T A T E ( r10 , r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl v s x _ u n a v a i l a b l e _ e x c e p t i o n
b r e t _ f r o m _ e x c e p t
2016-09-30 12:43:18 +03:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ O O L ( f a c i l i t y _ u n a v a i l a b l e , 0 x f60 , 0 x20 )
EXC_ V I R T _ O O L ( f a c i l i t y _ u n a v a i l a b l e , 0 x4 f60 , 0 x20 , 0 x f60 )
2016-09-21 10:43:56 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x f60 )
EXC_ C O M M O N ( f a c i l i t y _ u n a v a i l a b l e _ c o m m o n , 0 x f60 , f a c i l i t y _ u n a v a i l a b l e _ e x c e p t i o n )
2016-09-30 12:43:18 +03:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ O O L _ H V ( h _ f a c i l i t y _ u n a v a i l a b l e , 0 x f80 , 0 x20 )
EXC_ V I R T _ O O L _ H V ( h _ f a c i l i t y _ u n a v a i l a b l e , 0 x4 f80 , 0 x20 , 0 x f80 )
2016-09-21 10:43:57 +03:00
TRAMP_ K V M _ H V ( P A C A _ E X G E N , 0 x f80 )
EXC_ C O M M O N ( h _ f a c i l i t y _ u n a v a i l a b l e _ c o m m o n , 0 x f80 , f a c i l i t y _ u n a v a i l a b l e _ e x c e p t i o n )
2016-09-30 12:43:18 +03:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ N O N E ( 0 x f a0 , 0 x20 )
EXC_ V I R T _ N O N E ( 0 x4 f a0 , 0 x20 )
EXC_ R E A L _ N O N E ( 0 x f c0 , 0 x20 )
EXC_ V I R T _ N O N E ( 0 x4 f c0 , 0 x20 )
EXC_ R E A L _ N O N E ( 0 x f e 0 , 0 x20 )
EXC_ V I R T _ N O N E ( 0 x4 f e 0 , 0 x20 )
EXC_ R E A L _ N O N E ( 0 x10 0 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x50 0 0 , 0 x10 0 )
EXC_ R E A L _ N O N E ( 0 x11 0 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x51 0 0 , 0 x10 0 )
2013-02-13 20:21:38 +04:00
2009-06-03 01:17:38 +04:00
# ifdef C O N F I G _ C B E _ R A S
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ H V ( c b e _ s y s t e m _ e r r o r , 0 x12 0 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x52 0 0 , 0 x10 0 )
2016-09-30 12:43:18 +03:00
TRAMP_ K V M _ H V _ S K I P ( P A C A _ E X G E N , 0 x12 0 0 )
2016-09-21 10:43:59 +03:00
EXC_ C O M M O N ( c b e _ s y s t e m _ e r r o r _ c o m m o n , 0 x12 0 0 , c b e _ s y s t e m _ e r r o r _ e x c e p t i o n )
2016-09-30 12:43:18 +03:00
# else / * C O N F I G _ C B E _ R A S * /
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ N O N E ( 0 x12 0 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x52 0 0 , 0 x10 0 )
2016-09-30 12:43:18 +03:00
# endif
2011-06-29 04:18:26 +04:00
2016-09-21 10:43:59 +03:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L ( i n s t r u c t i o n _ b r e a k p o i n t , 0 x13 0 0 , 0 x10 0 )
EXC_ V I R T ( i n s t r u c t i o n _ b r e a k p o i n t , 0 x53 0 0 , 0 x10 0 , 0 x13 0 0 )
2016-09-30 12:43:18 +03:00
TRAMP_ K V M _ S K I P ( P A C A _ E X G E N , 0 x13 0 0 )
2016-09-21 10:44:00 +03:00
EXC_ C O M M O N ( i n s t r u c t i o n _ b r e a k p o i n t _ c o m m o n , 0 x13 0 0 , i n s t r u c t i o n _ b r e a k p o i n t _ e x c e p t i o n )
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ N O N E ( 0 x14 0 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x54 0 0 , 0 x10 0 )
2016-09-30 12:43:18 +03:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ B E G I N ( d e n o r m _ e x c e p t i o n _ h v , 0 x15 0 0 , 0 x10 0 )
2012-09-10 04:35:26 +04:00
mtspr S P R N _ S P R G _ H S C R A T C H 0 ,r13
powerpc: Save CFAR before branching in interrupt entry paths
Some of the interrupt vectors on 64-bit POWER server processors are
only 32 bytes long, which is not enough for the full first-level
interrupt handler. For these we currently just have a branch to an
out-of-line handler. However, this means that we corrupt the CFAR
(come-from address register) on POWER7 and later processors.
To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces:
EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR
is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We
then put EXCEPTION_PROLOG_0 in the short interrupt vectors before
we branch to the out-of-line handler, which contains the rest of the
first-level interrupt handler. To facilitate this, we define new
_OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc.
In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more
than 6 instructions, it was necessary to move the stores that move
the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and
to get rid of one of the two HMT_MEDIUM instructions. Previously
there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was
nop'd out on processors with the PPR (POWER7 and later), and then
another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside
__EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR.
Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally
and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although
this leaves it in for the interrupt vectors where there is room for
it.
Previously we had a handler for hypervisor maintenance interrupts at
0xe50, which doesn't leave enough room for the vector for hypervisor
emulation assist interrupts at 0xe40, since we need 8 instructions.
The 0xe50 vector was only used on POWER6, as the HMI vector was moved
to 0xe60 on POWER7. Since we don't support running in hypervisor mode
on POWER6, we just remove the handler at 0xe50.
This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0
instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD
from the relocation-on vectors (since any CPU that supports
relocation-on interrupts also has the PPR).
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-02-04 22:10:15 +04:00
EXCEPTION_ P R O L O G _ 0 ( P A C A _ E X G E N )
2013-08-12 10:12:06 +04:00
EXCEPTION_ P R O L O G _ 1 ( P A C A _ E X G E N , N O T E S T , 0 x15 0 0 )
2012-09-10 04:35:26 +04:00
# ifdef C O N F I G _ P P C _ D E N O R M A L I S A T I O N
mfspr r10 ,S P R N _ H S R R 1
mfspr r11 ,S P R N _ H S R R 0 / * s a v e H S R R 0 * /
2016-09-21 10:43:31 +03:00
andis. r10 ,r10 ,( H S R R 1 _ D E N O R M ) @h /* denorm? */
addi r11 ,r11 ,- 4 / * H S R R 0 i s n e x t i n s t r u c t i o n * /
bne+ d e n o r m _ a s s i s t
# endif
powerpc/book3s: handle machine check in Linux host.
Move machine check entry point into Linux. So far we were dependent on
firmware to decode MCE error details and handover the high level info to OS.
This patch introduces early machine check routine that saves the MCE
information (srr1, srr0, dar and dsisr) to the emergency stack. We allocate
stack frame on emergency stack and set the r1 accordingly. This allows us to be
prepared to take another exception without loosing context. One thing to note
here that, if we get another machine check while ME bit is off then we risk a
checkstop. Hence we restrict ourselves to save only MCE information and
register saved on PACA_EXMC save are before we turn the ME bit on. We use
paca->in_mce flag to differentiate between first entry and nested machine check
entry which helps proper use of emergency stack. We increment paca->in_mce
every time we enter in early machine check handler and decrement it while
leaving. When we enter machine check early handler first time (paca->in_mce ==
0), we are sure nobody is using MC emergency stack and allocate a stack frame
at the start of the emergency stack. During subsequent entry (paca->in_mce >
0), we know that r1 points inside emergency stack and we allocate separate
stack frame accordingly. This prevents us from clobbering MCE information
during nested machine checks.
The early machine check handler changes are placed under CPU_FTR_HVMODE
section. This makes sure that the early machine check handler will get executed
only in hypervisor kernel.
This is the code flow:
Machine Check Interrupt
|
V
0x200 vector ME=0, IR=0, DR=0
|
V
+-----------------------------------------------+
|machine_check_pSeries_early: | ME=0, IR=0, DR=0
| Alloc frame on emergency stack |
| Save srr1, srr0, dar and dsisr on stack |
+-----------------------------------------------+
|
(ME=1, IR=0, DR=0, RFID)
|
V
machine_check_handle_early ME=1, IR=0, DR=0
|
V
+-----------------------------------------------+
| machine_check_early (r3=pt_regs) | ME=1, IR=0, DR=0
| Things to do: (in next patches) |
| Flush SLB for SLB errors |
| Flush TLB for TLB errors |
| Decode and save MCE info |
+-----------------------------------------------+
|
(Fall through existing exception handler routine.)
|
V
machine_check_pSerie ME=1, IR=0, DR=0
|
(ME=1, IR=1, DR=1, RFID)
|
V
machine_check_common ME=1, IR=1, DR=1
.
.
.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-30 18:34:08 +04:00
2016-09-21 10:43:31 +03:00
KVMTEST_ P R ( 0 x15 0 0 )
EXCEPTION_ P R O L O G _ P S E R I E S _ 1 ( d e n o r m _ c o m m o n , E X C _ H V )
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ E N D ( d e n o r m _ e x c e p t i o n _ h v , 0 x15 0 0 , 0 x10 0 )
2016-08-10 13:48:43 +03:00
2016-09-21 10:44:01 +03:00
# ifdef C O N F I G _ P P C _ D E N O R M A L I S A T I O N
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ B E G I N ( d e n o r m _ e x c e p t i o n , 0 x55 0 0 , 0 x10 0 )
2016-09-21 10:44:01 +03:00
b e x c _ r e a l _ 0 x15 0 0 _ d e n o r m _ e x c e p t i o n _ h v
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ E N D ( d e n o r m _ e x c e p t i o n , 0 x55 0 0 , 0 x10 0 )
2016-09-21 10:44:01 +03:00
# else
2016-12-06 04:41:12 +03:00
EXC_ V I R T _ N O N E ( 0 x55 0 0 , 0 x10 0 )
2016-09-21 10:43:31 +03:00
# endif
2016-09-21 10:44:01 +03:00
TRAMP_ K V M _ S K I P ( P A C A _ E X G E N , 0 x15 0 0 )
2011-06-29 04:18:26 +04:00
2012-09-10 04:35:26 +04:00
# ifdef C O N F I G _ P P C _ D E N O R M A L I S A T I O N
2016-09-30 12:43:18 +03:00
TRAMP_ R E A L _ B E G I N ( d e n o r m _ a s s i s t )
2012-09-10 04:35:26 +04:00
BEGIN_ F T R _ S E C T I O N
/ *
* To d e n o r m a l i s e w e n e e d t o m o v e a c o p y o f t h e r e g i s t e r t o i t s e l f .
* For P O W E R 6 d o t h a t h e r e f o r a l l F P r e g s .
* /
mfmsr r10
ori r10 ,r10 ,( M S R _ F P | M S R _ F E 0 | M S R _ F E 1 )
xori r10 ,r10 ,( M S R _ F E 0 | M S R _ F E 1 )
mtmsrd r10
sync
2013-05-30 01:33:18 +04:00
# define F M R 2 ( n ) f m r ( n ) , ( n ) ; fmr n+1, n+1
# define F M R 4 ( n ) F M R 2 ( n ) ; FMR2(n+2)
# define F M R 8 ( n ) F M R 4 ( n ) ; FMR4(n+4)
# define F M R 1 6 ( n ) F M R 8 ( n ) ; FMR8(n+8)
# define F M R 3 2 ( n ) F M R 1 6 ( n ) ; FMR16(n+16)
FMR3 2 ( 0 )
2012-09-10 04:35:26 +04:00
FTR_ S E C T I O N _ E L S E
/ *
* To d e n o r m a l i s e w e n e e d t o m o v e a c o p y o f t h e r e g i s t e r t o i t s e l f .
* For P O W E R 7 d o t h a t h e r e f o r t h e f i r s t 3 2 V S X r e g i s t e r s o n l y .
* /
mfmsr r10
oris r10 ,r10 ,M S R _ V S X @h
mtmsrd r10
sync
2013-05-30 01:33:18 +04:00
# define X V C P S G N D P 2 ( n ) X V C P S G N D P ( n ,n ,n ) ; XVCPSGNDP(n+1,n+1,n+1)
# define X V C P S G N D P 4 ( n ) X V C P S G N D P 2 ( n ) ; XVCPSGNDP2(n+2)
# define X V C P S G N D P 8 ( n ) X V C P S G N D P 4 ( n ) ; XVCPSGNDP4(n+4)
# define X V C P S G N D P 1 6 ( n ) X V C P S G N D P 8 ( n ) ; XVCPSGNDP8(n+8)
# define X V C P S G N D P 3 2 ( n ) X V C P S G N D P 1 6 ( n ) ; XVCPSGNDP16(n+16)
XVCPSGNDP3 2 ( 0 )
2012-09-10 04:35:26 +04:00
ALT_ F T R _ S E C T I O N _ E N D _ I F C L R ( C P U _ F T R _ A R C H _ 2 0 6 )
2013-05-30 01:33:19 +04:00
BEGIN_ F T R _ S E C T I O N
b d e n o r m _ d o n e
END_ F T R _ S E C T I O N _ I F C L R ( C P U _ F T R _ A R C H _ 2 0 7 S )
/ *
* To d e n o r m a l i s e w e n e e d t o m o v e a c o p y o f t h e r e g i s t e r t o i t s e l f .
* For P O W E R 8 w e n e e d t o d o t h a t f o r a l l 6 4 V S X r e g i s t e r s
* /
XVCPSGNDP3 2 ( 3 2 )
denorm_done :
2012-09-10 04:35:26 +04:00
mtspr S P R N _ H S R R 0 ,r11
mtcrf 0 x80 ,r9
ld r9 ,P A C A _ E X G E N + E X _ R 9 ( r13 )
2012-12-07 01:51:04 +04:00
RESTORE_ P P R _ P A C A ( P A C A _ E X G E N , r10 )
2013-08-12 10:12:06 +04:00
BEGIN_ F T R _ S E C T I O N
ld r10 ,P A C A _ E X G E N + E X _ C F A R ( r13 )
mtspr S P R N _ C F A R ,r10
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ C F A R )
2012-09-10 04:35:26 +04:00
ld r10 ,P A C A _ E X G E N + E X _ R 1 0 ( r13 )
ld r11 ,P A C A _ E X G E N + E X _ R 1 1 ( r13 )
ld r12 ,P A C A _ E X G E N + E X _ R 1 2 ( r13 )
ld r13 ,P A C A _ E X G E N + E X _ R 1 3 ( r13 )
HRFID
b .
# endif
2016-09-21 10:44:01 +03:00
EXC_ C O M M O N _ H V ( d e n o r m _ c o m m o n , 0 x15 0 0 , u n k n o w n _ e x c e p t i o n )
# ifdef C O N F I G _ C B E _ R A S
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ H V ( c b e _ m a i n t e n a n c e , 0 x16 0 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x56 0 0 , 0 x10 0 )
2016-09-21 10:44:01 +03:00
TRAMP_ K V M _ H V _ S K I P ( P A C A _ E X G E N , 0 x16 0 0 )
2016-09-21 10:44:02 +03:00
EXC_ C O M M O N ( c b e _ m a i n t e n a n c e _ c o m m o n , 0 x16 0 0 , c b e _ m a i n t e n a n c e _ e x c e p t i o n )
2016-09-21 10:44:01 +03:00
# else / * C O N F I G _ C B E _ R A S * /
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ N O N E ( 0 x16 0 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x56 0 0 , 0 x10 0 )
2016-09-21 10:44:01 +03:00
# endif
2016-09-21 10:44:02 +03:00
2016-12-06 04:41:12 +03:00
EXC_ R E A L ( a l t i v e c _ a s s i s t , 0 x17 0 0 , 0 x10 0 )
EXC_ V I R T ( a l t i v e c _ a s s i s t , 0 x57 0 0 , 0 x10 0 , 0 x17 0 0 )
2016-09-21 10:44:01 +03:00
TRAMP_ K V M ( P A C A _ E X G E N , 0 x17 0 0 )
2016-09-21 10:44:03 +03:00
# ifdef C O N F I G _ A L T I V E C
EXC_ C O M M O N ( a l t i v e c _ a s s i s t _ c o m m o n , 0 x17 0 0 , a l t i v e c _ a s s i s t _ e x c e p t i o n )
# else
EXC_ C O M M O N ( a l t i v e c _ a s s i s t _ c o m m o n , 0 x17 0 0 , u n k n o w n _ e x c e p t i o n )
# endif
2016-09-21 10:44:01 +03:00
# ifdef C O N F I G _ C B E _ R A S
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ H V ( c b e _ t h e r m a l , 0 x18 0 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x58 0 0 , 0 x10 0 )
2016-09-21 10:44:01 +03:00
TRAMP_ K V M _ H V _ S K I P ( P A C A _ E X G E N , 0 x18 0 0 )
2016-09-21 10:44:04 +03:00
EXC_ C O M M O N ( c b e _ t h e r m a l _ c o m m o n , 0 x18 0 0 , c b e _ t h e r m a l _ e x c e p t i o n )
2016-09-21 10:44:01 +03:00
# else / * C O N F I G _ C B E _ R A S * /
2016-12-06 04:41:12 +03:00
EXC_ R E A L _ N O N E ( 0 x18 0 0 , 0 x10 0 )
EXC_ V I R T _ N O N E ( 0 x58 0 0 , 0 x10 0 )
2016-09-21 10:44:01 +03:00
# endif
2009-06-03 01:17:38 +04:00
/ *
2012-11-14 22:49:48 +04:00
* An i n t e r r u p t c a m e i n w h i l e s o f t - d i s a b l e d . W e s e t p a c a - > i r q _ h a p p e n e d , t h e n :
* - If i t w a s a d e c r e m e n t e r i n t e r r u p t , w e b u m p t h e d e c t o m a x a n d a n d r e t u r n .
* - If i t w a s a d o o r b e l l w e r e t u r n i m m e d i a t e l y s i n c e d o o r b e l l s a r e e d g e
* triggered a n d w o n ' t a u t o m a t i c a l l y r e f i r e .
2014-07-29 17:10:01 +04:00
* - If i t w a s a H M I w e r e t u r n i m m e d i a t e l y s i n c e w e h a n d l e d i t i n r e a l m o d e
* and i t w o n ' t r e f i r e .
2012-11-14 22:49:48 +04:00
* - else w e h a r d d i s a b l e a n d r e t u r n .
* This i s c a l l e d w i t h r10 c o n t a i n i n g t h e v a l u e t o O R t o t h e p a c a f i e l d .
2009-06-03 01:17:38 +04:00
* /
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 11:27:59 +04:00
# define M A S K E D _ I N T E R R U P T ( _ H ) \
masked_ ## _ H # # i n t e r r u p t : \
std r11 ,P A C A _ E X G E N + E X _ R 1 1 ( r13 ) ; \
lbz r11 ,P A C A I R Q H A P P E N E D ( r13 ) ; \
or r11 ,r11 ,r10 ; \
stb r11 ,P A C A I R Q H A P P E N E D ( r13 ) ; \
2012-11-14 22:49:48 +04:00
cmpwi r10 ,P A C A _ I R Q _ D E C ; \
bne 1 f ; \
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 11:27:59 +04:00
lis r10 ,0 x7 f f f ; \
ori r10 ,r10 ,0 x f f f f ; \
mtspr S P R N _ D E C ,r10 ; \
b 2 f ; \
2012-11-14 22:49:48 +04:00
1 : cmpwi r10 ,P A C A _ I R Q _ D B E L L ; \
2014-07-29 17:10:01 +04:00
beq 2 f ; \
cmpwi r10 ,P A C A _ I R Q _ H M I ; \
2012-11-14 22:49:48 +04:00
beq 2 f ; \
mfspr r10 ,S P R N _ ## _ H # # S R R 1 ; \
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 11:27:59 +04:00
rldicl r10 ,r10 ,4 8 ,1 ; /* clear MSR_EE */ \
rotldi r10 ,r10 ,1 6 ; \
mtspr S P R N _ ## _ H # # S R R 1 ,r10 ; \
2 : mtcrf 0 x80 ,r9 ; \
ld r9 ,P A C A _ E X G E N + E X _ R 9 ( r13 ) ; \
ld r10 ,P A C A _ E X G E N + E X _ R 1 0 ( r13 ) ; \
ld r11 ,P A C A _ E X G E N + E X _ R 1 1 ( r13 ) ; \
GET_ S C R A T C H 0 ( r13 ) ; \
# # _ H## r f i d ; \
2009-06-03 01:17:38 +04:00
b .
2016-09-28 04:31:48 +03:00
/ *
* Real m o d e e x c e p t i o n s a c t u a l l y u s e t h i s t o o , b u t a l t e r n a t e
* instruction c o d e p a t c h e s ( w h i c h e n d u p i n t h e c o m m o n . t e x t a r e a )
* cannot r e a c h t h e s e i f t h e y a r e p u t t h e r e .
* /
USE_ F I X E D _ S E C T I O N ( v i r t _ t r a m p o l i n e s )
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 11:27:59 +04:00
MASKED_ I N T E R R U P T ( )
MASKED_ I N T E R R U P T ( H )
2009-06-03 01:17:38 +04:00
2013-09-20 08:52:50 +04:00
# ifdef C O N F I G _ K V M _ B O O K 3 S _ 6 4 _ H A N D L E R
2016-09-30 12:43:18 +03:00
TRAMP_ R E A L _ B E G I N ( k v m p p c _ s k i p _ i n t e r r u p t )
2013-09-20 08:52:50 +04:00
/ *
* Here a l l G P R s a r e u n c h a n g e d f r o m w h e n t h e i n t e r r u p t h a p p e n e d
* except f o r r13 , w h i c h i s s a v e d i n S P R G _ S C R A T C H 0 .
* /
mfspr r13 , S P R N _ S R R 0
addi r13 , r13 , 4
mtspr S P R N _ S R R 0 , r13
GET_ S C R A T C H 0 ( r13 )
rfid
b .
2016-09-30 12:43:18 +03:00
TRAMP_ R E A L _ B E G I N ( k v m p p c _ s k i p _ H i n t e r r u p t )
2013-09-20 08:52:50 +04:00
/ *
* Here a l l G P R s a r e u n c h a n g e d f r o m w h e n t h e i n t e r r u p t h a p p e n e d
* except f o r r13 , w h i c h i s s a v e d i n S P R G _ S C R A T C H 0 .
* /
mfspr r13 , S P R N _ H S R R 0
addi r13 , r13 , 4
mtspr S P R N _ H S R R 0 , r13
GET_ S C R A T C H 0 ( r13 )
hrfid
b .
# endif
2009-06-03 01:17:38 +04:00
/ *
2016-04-08 01:00:34 +03:00
* Ensure t h a t a n y h a n d l e r s t h a t g e t i n v o k e d f r o m t h e e x c e p t i o n p r o l o g s
* above a r e b e l o w t h e f i r s t 6 4 K B ( 0 x10 0 0 0 ) o f t h e k e r n e l i m a g e b e c a u s e
* the p r o l o g s a s s e m b l e t h e a d d r e s s e s o f t h e s e h a n d l e r s u s i n g t h e
* LOAD_ H A N D L E R m a c r o , w h i c h u s e s a n o r i i n s t r u c t i o n .
2009-06-03 01:17:38 +04:00
* /
/*** Common interrupt handlers ***/
2012-11-02 10:21:43 +04:00
/ *
* Relocation- o n i n t e r r u p t s : A s u b s e t o f t h e i n t e r r u p t s c a n b e d e l i v e r e d
* with I R =1 / D R =1 , i f A I L = =2 a n d M S R . H V w o n ' t b e c h a n g e d b y d e l i v e r i n g
* it. A d d r e s s e s a r e t h e s a m e a s t h e o r i g i n a l i n t e r r u p t a d d r e s s e s , b u t
* offset b y 0 x c00 0 0 0 0 0 0 0 0 0 4 0 0 0 .
* It' s i m p o s s i b l e t o r e c e i v e i n t e r r u p t s b e l o w 0 x30 0 v i a t h i s m e c h a n i s m .
* KVM : None o f t h e s e t r a p s a r e f r o m t h e g u e s t ; anything that escalated
* to H V =1 f r o m H V =0 i s d e l i v e r e d v i a r e a l m o d e h a n d l e r s .
* /
/ *
* This u s e s t h e s t a n d a r d m a c r o , s i n c e t h e o r i g i n a l 0 x30 0 v e c t o r
* only h a s e x t r a g u f f f o r S T A B - b a s e d p r o c e s s o r s - - w h i c h n e v e r
* come h e r e .
* /
2016-09-30 12:43:18 +03:00
2016-09-28 04:31:48 +03:00
EXC_ C O M M O N _ B E G I N ( p p c64 _ r u n l a t c h _ o n _ t r a m p o l i n e )
2014-02-04 09:04:35 +04:00
b _ _ p p c64 _ r u n l a t c h _ o n
2012-03-01 05:45:27 +04:00
2016-09-28 04:31:48 +03:00
USE_ F I X E D _ S E C T I O N ( v i r t _ t r a m p o l i n e s )
powerpc/book3s64: Fix branching to OOL handlers in relocatable kernel
Some of the interrupt vectors on 64-bit POWER server processors are only
32 bytes long (8 instructions), which is not enough for the full
first-level interrupt handler. For these we need to branch to an
out-of-line (OOL) handler. But when we are running a relocatable kernel,
interrupt vectors till __end_interrupts marker are copied down to real
address 0x100. So, branching to labels (ie. OOL handlers) outside this
section must be handled differently (see LOAD_HANDLER()), considering
relocatable kernel, which would need at least 4 instructions.
However, branching from interrupt vector means that we corrupt the
CFAR (come-from address register) on POWER7 and later processors as
mentioned in commit 1707dd16. So, EXCEPTION_PROLOG_0 (6 instructions)
that contains the part up to the point where the CFAR is saved in the
PACA should be part of the short interrupt vectors before we branch out
to OOL handlers.
But as mentioned already, there are interrupt vectors on 64-bit POWER
server processors that are only 32 bytes long (like vectors 0x4f00,
0x4f20, etc.), which cannot accomodate the above two cases at the same
time owing to space constraint. Currently, in these interrupt vectors,
we simply branch out to OOL handlers, without using LOAD_HANDLER(),
which leaves us vulnerable when running a relocatable kernel (eg. kdump
case). While this has been the case for sometime now and kdump is used
widely, we were fortunate not to see any problems so far, for three
reasons:
1. In almost all cases, production kernel (relocatable) is used for
kdump as well, which would mean that crashed kernel's OOL handler
would be at the same place where we end up branching to, from short
interrupt vector of kdump kernel.
2. Also, OOL handler was unlikely the reason for crash in almost all
the kdump scenarios, which meant we had a sane OOL handler from
crashed kernel that we branched to.
3. On most 64-bit POWER server processors, page size is large enough
that marking interrupt vector code as executable (see commit
429d2e83) leads to marking OOL handler code from crashed kernel,
that sits right below interrupt vector code from kdump kernel, as
executable as well.
Let us fix this by moving the __end_interrupts marker down past OOL
handlers to make sure that we also copy OOL handlers to real address
0x100 when running a relocatable kernel.
This fix has been tested successfully in kdump scenario, on an LPAR with
4K page size by using different default/production kernel and kdump
kernel.
Also tested by manually corrupting the OOL handlers in the first kernel
and then kdump'ing, and then causing the OOL handlers to fire - mpe.
Fixes: c1fb6816fb1b ("powerpc: Add relocation on exception vector handlers")
Cc: stable@vger.kernel.org
Signed-off-by: Hari Bathini <hbathini@linux.vnet.ibm.com>
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-04-15 15:48:02 +03:00
/ *
* The _ _ e n d _ i n t e r r u p t s m a r k e r m u s t b e p a s t t h e o u t - o f - l i n e ( O O L )
* handlers, s o t h a t t h e y a r e c o p i e d t o r e a l a d d r e s s 0 x10 0 w h e n r u n n i n g
* a r e l o c a t a b l e k e r n e l . T h i s e n s u r e s t h e y c a n b e r e a c h e d f r o m t h e s h o r t
* trampoline h a n d l e r s ( l i k e 0 x4 f00 , 0 x4 f20 , e t c . ) w h i c h b r a n c h
* directly, w i t h o u t u s i n g L O A D _ H A N D L E R ( ) .
* /
.align 7
.globl __end_interrupts
__end_interrupts :
2016-09-28 04:31:48 +03:00
DEFINE_ F I X E D _ S Y M B O L ( _ _ e n d _ i n t e r r u p t s )
2013-01-10 10:44:19 +04:00
2013-03-25 05:31:31 +04:00
# ifdef C O N F I G _ P P C _ 9 7 0 _ N A P
2016-10-11 10:47:56 +03:00
EXC_ C O M M O N _ B E G I N ( p o w e r4 _ f i x u p _ n a p )
2013-03-25 05:31:31 +04:00
andc r9 ,r9 ,r10
std r9 ,T I _ L O C A L _ F L A G S ( r11 )
ld r10 ,_ L I N K ( r1 ) / * m a k e i d l e t a s k d o t h e * /
std r10 ,_ N I P ( r1 ) / * e q u i v a l e n t o f a b l r * /
blr
# endif
2016-09-28 04:31:48 +03:00
CLOSE_ F I X E D _ S E C T I O N ( r e a l _ v e c t o r s ) ;
CLOSE_ F I X E D _ S E C T I O N ( r e a l _ t r a m p o l i n e s ) ;
CLOSE_ F I X E D _ S E C T I O N ( v i r t _ v e c t o r s ) ;
CLOSE_ F I X E D _ S E C T I O N ( v i r t _ t r a m p o l i n e s ) ;
USE_ T E X T _ S E C T I O N ( )
2009-06-03 01:17:38 +04:00
/ *
* Hash t a b l e s t u f f
* /
2016-10-13 06:43:52 +03:00
.balign IFETCH_ALIGN_BYTES
2014-02-04 09:06:11 +04:00
do_hash_page :
2016-04-29 16:26:07 +03:00
# ifdef C O N F I G _ P P C _ S T D _ M M U _ 6 4
2010-03-30 03:59:25 +04:00
andis. r0 ,r4 ,0 x a41 0 / * w e i r d e r r o r ? * /
2009-06-03 01:17:38 +04:00
bne- h a n d l e _ p a g e _ f a u l t / * i f n o t , t r y t o i n s e r t a H P T E * /
2010-03-30 03:59:25 +04:00
andis. r0 ,r4 ,D S I S R _ D A B R M A T C H @h
bne- h a n d l e _ d a b r _ f a u l t
2012-07-05 08:41:35 +04:00
CURRENT_ T H R E A D _ I N F O ( r11 , r1 )
powerpc: Allow perf_counters to access user memory at interrupt time
This provides a mechanism to allow the perf_counters code to access
user memory in a PMU interrupt routine. Such an access can cause
various kinds of interrupt: SLB miss, MMU hash table miss, segment
table miss, or TLB miss, depending on the processor. This commit
only deals with 64-bit classic/server processors, which use an MMU
hash table. 32-bit processors are already able to access user memory
at interrupt time. Since we don't soft-disable on 32-bit, we avoid
the possibility of reentering hash_page or the TLB miss handlers,
since they run with interrupts disabled.
On 64-bit processors, an SLB miss interrupt on a user address will
update the slb_cache and slb_cache_ptr fields in the paca. This is
OK except in the case where a PMU interrupt occurs in switch_slb,
which also accesses those fields. To prevent this, we hard-disable
interrupts in switch_slb. Interrupts are already soft-disabled at
this point, and will get hard-enabled when they get soft-enabled
later.
This also reworks slb_flush_and_rebolt: to avoid hard-disabling twice,
and to make sure that it clears the slb_cache_ptr when called from
other callers than switch_slb, the existing routine is renamed to
__slb_flush_and_rebolt, which is called by switch_slb and the new
version of slb_flush_and_rebolt.
Similarly, switch_stab (used on POWER3 and RS64 processors) gets a
hard_irq_disable() to protect the per-cpu variables used there and
in ste_allocate.
If a MMU hashtable miss interrupt occurs, normally we would call
hash_page to look up the Linux PTE for the address and create a HPTE.
However, hash_page is fairly complex and takes some locks, so to
avoid the possibility of deadlock, we check the preemption count
to see if we are in a (pseudo-)NMI handler, and if so, we don't call
hash_page but instead treat it like a bad access that will get
reported up through the exception table mechanism. An interrupt
whose handler runs even though the interrupt occurred when
soft-disabled (such as the PMU interrupt) is considered a pseudo-NMI
handler, which should use nmi_enter()/nmi_exit() rather than
irq_enter()/irq_exit().
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2009-08-17 09:17:54 +04:00
lwz r0 ,T I _ P R E E M P T ( r11 ) / * I f w e ' r e i n a n " N M I " * /
andis. r0 ,r0 ,N M I _ M A S K @h /* (i.e. an irq when soft-disabled) */
bne 7 7 f / * t h e n d o n ' t c a l l h a s h _ p a g e n o w * /
2009-06-03 01:17:38 +04:00
/ *
* r3 c o n t a i n s t h e f a u l t i n g a d d r e s s
2015-12-01 06:36:44 +03:00
* r4 m s r
2009-06-03 01:17:38 +04:00
* r5 c o n t a i n s t h e t r a p n u m b e r
2014-12-04 08:30:14 +03:00
* r6 c o n t a i n s d s i s r
2009-06-03 01:17:38 +04:00
*
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 11:27:59 +04:00
* at r e t u r n r3 = 0 f o r s u c c e s s , 1 f o r p a g e f a u l t , n e g a t i v e f o r e r r o r
2009-06-03 01:17:38 +04:00
* /
2015-12-01 06:36:44 +03:00
mr r4 ,r12
2014-12-04 08:30:14 +03:00
ld r6 ,_ D S I S R ( r1 )
2015-12-01 06:36:44 +03:00
bl _ _ h a s h _ p a g e / * b u i l d H P T E i f p o s s i b l e * /
cmpdi r3 ,0 / * s e e i f _ _ h a s h _ p a g e s u c c e e d e d * /
2009-06-03 01:17:38 +04:00
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 11:27:59 +04:00
/* Success */
2009-06-03 01:17:38 +04:00
beq f a s t _ e x c _ r e t u r n _ i r q / * R e t u r n f r o m e x c e p t i o n o n s u c c e s s * /
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 11:27:59 +04:00
/* Error */
blt- 1 3 f
2016-04-29 16:26:07 +03:00
# endif / * C O N F I G _ P P C _ S T D _ M M U _ 6 4 * /
2010-03-30 03:59:25 +04:00
2009-06-03 01:17:38 +04:00
/* Here we have a page fault that hash_page can't handle. */
handle_page_fault :
11 : ld r4 ,_ D A R ( r1 )
ld r5 ,_ D S I S R ( r1 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
2014-02-04 09:04:35 +04:00
bl d o _ p a g e _ f a u l t
2009-06-03 01:17:38 +04:00
cmpdi r3 ,0
2012-03-07 09:48:45 +04:00
beq+ 1 2 f
2014-02-04 09:04:35 +04:00
bl s a v e _ n v g p r s
2009-06-03 01:17:38 +04:00
mr r5 ,r3
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
lwz r4 ,_ D A R ( r1 )
2014-02-04 09:04:35 +04:00
bl b a d _ p a g e _ f a u l t
b r e t _ f r o m _ e x c e p t
2009-06-03 01:17:38 +04:00
2012-03-07 09:48:45 +04:00
/* We have a data breakpoint exception - handle it */
handle_dabr_fault :
2014-02-04 09:04:35 +04:00
bl s a v e _ n v g p r s
2012-03-07 09:48:45 +04:00
ld r4 ,_ D A R ( r1 )
ld r5 ,_ D S I S R ( r1 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
2014-02-04 09:04:35 +04:00
bl d o _ b r e a k
12 : b r e t _ f r o m _ e x c e p t _ l i t e
2012-03-07 09:48:45 +04:00
2009-06-03 01:17:38 +04:00
2016-04-29 16:26:07 +03:00
# ifdef C O N F I G _ P P C _ S T D _ M M U _ 6 4
2009-06-03 01:17:38 +04:00
/ * We h a v e a p a g e f a u l t t h a t h a s h _ p a g e c o u l d h a n d l e b u t H V r e f u s e d
* the P T E i n s e r t i o n
* /
2014-02-04 09:04:35 +04:00
13 : bl s a v e _ n v g p r s
2009-06-03 01:17:38 +04:00
mr r5 ,r3
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
ld r4 ,_ D A R ( r1 )
2014-02-04 09:04:35 +04:00
bl l o w _ h a s h _ f a u l t
b r e t _ f r o m _ e x c e p t
2016-04-29 16:26:07 +03:00
# endif
2009-06-03 01:17:38 +04:00
powerpc: Allow perf_counters to access user memory at interrupt time
This provides a mechanism to allow the perf_counters code to access
user memory in a PMU interrupt routine. Such an access can cause
various kinds of interrupt: SLB miss, MMU hash table miss, segment
table miss, or TLB miss, depending on the processor. This commit
only deals with 64-bit classic/server processors, which use an MMU
hash table. 32-bit processors are already able to access user memory
at interrupt time. Since we don't soft-disable on 32-bit, we avoid
the possibility of reentering hash_page or the TLB miss handlers,
since they run with interrupts disabled.
On 64-bit processors, an SLB miss interrupt on a user address will
update the slb_cache and slb_cache_ptr fields in the paca. This is
OK except in the case where a PMU interrupt occurs in switch_slb,
which also accesses those fields. To prevent this, we hard-disable
interrupts in switch_slb. Interrupts are already soft-disabled at
this point, and will get hard-enabled when they get soft-enabled
later.
This also reworks slb_flush_and_rebolt: to avoid hard-disabling twice,
and to make sure that it clears the slb_cache_ptr when called from
other callers than switch_slb, the existing routine is renamed to
__slb_flush_and_rebolt, which is called by switch_slb and the new
version of slb_flush_and_rebolt.
Similarly, switch_stab (used on POWER3 and RS64 processors) gets a
hard_irq_disable() to protect the per-cpu variables used there and
in ste_allocate.
If a MMU hashtable miss interrupt occurs, normally we would call
hash_page to look up the Linux PTE for the address and create a HPTE.
However, hash_page is fairly complex and takes some locks, so to
avoid the possibility of deadlock, we check the preemption count
to see if we are in a (pseudo-)NMI handler, and if so, we don't call
hash_page but instead treat it like a bad access that will get
reported up through the exception table mechanism. An interrupt
whose handler runs even though the interrupt occurred when
soft-disabled (such as the PMU interrupt) is considered a pseudo-NMI
handler, which should use nmi_enter()/nmi_exit() rather than
irq_enter()/irq_exit().
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2009-08-17 09:17:54 +04:00
/ *
* We c o m e h e r e a s a r e s u l t o f a D S I a t a p o i n t w h e r e w e d o n ' t w a n t
* to c a l l h a s h _ p a g e , s u c h a s w h e n w e a r e a c c e s s i n g m e m o r y ( p o s s i b l y
* user m e m o r y ) i n s i d e a P M U i n t e r r u p t t h a t o c c u r r e d w h i l e i n t e r r u p t s
* were s o f t - d i s a b l e d . W e w a n t t o i n v o k e t h e e x c e p t i o n h a n d l e r f o r
* the a c c e s s , o r p a n i c i f t h e r e i s n ' t a h a n d l e r .
* /
2014-02-04 09:04:35 +04:00
77 : bl s a v e _ n v g p r s
powerpc: Allow perf_counters to access user memory at interrupt time
This provides a mechanism to allow the perf_counters code to access
user memory in a PMU interrupt routine. Such an access can cause
various kinds of interrupt: SLB miss, MMU hash table miss, segment
table miss, or TLB miss, depending on the processor. This commit
only deals with 64-bit classic/server processors, which use an MMU
hash table. 32-bit processors are already able to access user memory
at interrupt time. Since we don't soft-disable on 32-bit, we avoid
the possibility of reentering hash_page or the TLB miss handlers,
since they run with interrupts disabled.
On 64-bit processors, an SLB miss interrupt on a user address will
update the slb_cache and slb_cache_ptr fields in the paca. This is
OK except in the case where a PMU interrupt occurs in switch_slb,
which also accesses those fields. To prevent this, we hard-disable
interrupts in switch_slb. Interrupts are already soft-disabled at
this point, and will get hard-enabled when they get soft-enabled
later.
This also reworks slb_flush_and_rebolt: to avoid hard-disabling twice,
and to make sure that it clears the slb_cache_ptr when called from
other callers than switch_slb, the existing routine is renamed to
__slb_flush_and_rebolt, which is called by switch_slb and the new
version of slb_flush_and_rebolt.
Similarly, switch_stab (used on POWER3 and RS64 processors) gets a
hard_irq_disable() to protect the per-cpu variables used there and
in ste_allocate.
If a MMU hashtable miss interrupt occurs, normally we would call
hash_page to look up the Linux PTE for the address and create a HPTE.
However, hash_page is fairly complex and takes some locks, so to
avoid the possibility of deadlock, we check the preemption count
to see if we are in a (pseudo-)NMI handler, and if so, we don't call
hash_page but instead treat it like a bad access that will get
reported up through the exception table mechanism. An interrupt
whose handler runs even though the interrupt occurred when
soft-disabled (such as the PMU interrupt) is considered a pseudo-NMI
handler, which should use nmi_enter()/nmi_exit() rather than
irq_enter()/irq_exit().
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2009-08-17 09:17:54 +04:00
mr r4 ,r3
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
li r5 ,S I G S E G V
2014-02-04 09:04:35 +04:00
bl b a d _ p a g e _ f a u l t
b r e t _ f r o m _ e x c e p t
2014-07-15 14:25:02 +04:00
/ *
* Here w e h a v e d e t e c t e d t h a t t h e k e r n e l s t a c k p o i n t e r i s b a d .
* R9 c o n t a i n s t h e s a v e d C R , r13 p o i n t s t o t h e p a c a ,
* r1 0 c o n t a i n s t h e ( b a d ) k e r n e l s t a c k p o i n t e r ,
* r1 1 a n d r12 c o n t a i n t h e s a v e d S R R 0 a n d S R R 1 .
* We s w i t c h t o u s i n g a n e m e r g e n c y s t a c k , s a v e t h e r e g i s t e r s t h e r e ,
* and c a l l k e r n e l _ b a d _ s t a c k ( ) , w h i c h p a n i c s .
* /
bad_stack :
ld r1 ,P A C A E M E R G S P ( r13 )
subi r1 ,r1 ,6 4 + I N T _ F R A M E _ S I Z E
std r9 ,_ C C R ( r1 )
std r10 ,G P R 1 ( r1 )
std r11 ,_ N I P ( r1 )
std r12 ,_ M S R ( r1 )
mfspr r11 ,S P R N _ D A R
mfspr r12 ,S P R N _ D S I S R
std r11 ,_ D A R ( r1 )
std r12 ,_ D S I S R ( r1 )
mflr r10
mfctr r11
mfxer r12
std r10 ,_ L I N K ( r1 )
std r11 ,_ C T R ( r1 )
std r12 ,_ X E R ( r1 )
SAVE_ G P R ( 0 ,r1 )
SAVE_ G P R ( 2 ,r1 )
ld r10 ,E X _ R 3 ( r3 )
std r10 ,G P R 3 ( r1 )
SAVE_ G P R ( 4 ,r1 )
SAVE_ 4 G P R S ( 5 ,r1 )
ld r9 ,E X _ R 9 ( r3 )
ld r10 ,E X _ R 1 0 ( r3 )
SAVE_ 2 G P R S ( 9 ,r1 )
ld r9 ,E X _ R 1 1 ( r3 )
ld r10 ,E X _ R 1 2 ( r3 )
ld r11 ,E X _ R 1 3 ( r3 )
std r9 ,G P R 1 1 ( r1 )
std r10 ,G P R 1 2 ( r1 )
std r11 ,G P R 1 3 ( r1 )
BEGIN_ F T R _ S E C T I O N
ld r10 ,E X _ C F A R ( r3 )
std r10 ,O R I G _ G P R 3 ( r1 )
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ C F A R )
SAVE_ 8 G P R S ( 1 4 ,r1 )
SAVE_ 1 0 G P R S ( 2 2 ,r1 )
lhz r12 ,P A C A _ T R A P _ S A V E ( r13 )
std r12 ,_ T R A P ( r1 )
addi r11 ,r1 ,I N T _ F R A M E _ S I Z E
std r11 ,0 ( r1 )
li r12 ,0
std r12 ,0 ( r11 )
ld r2 ,P A C A T O C ( r13 )
ld r11 ,e x c e p t i o n _ m a r k e r @toc(r2)
std r12 ,R E S U L T ( r1 )
std r11 ,S T A C K _ F R A M E _ O V E R H E A D - 1 6 ( r1 )
1 : addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl k e r n e l _ b a d _ s t a c k
b 1 b
2016-09-21 10:44:05 +03:00
/ *
* Called f r o m a r c h _ l o c a l _ i r q _ e n a b l e w h e n a n i n t e r r u p t n e e d s
* to b e r e s e n t . r3 c o n t a i n s 0 x50 0 , 0 x90 0 , 0 x a00 o r 0 x e 8 0 t o i n d i c a t e
* which k i n d o f i n t e r r u p t . M S R : E E i s a l r e a d y o f f . W e g e n e r a t e a
* stackframe l i k e i f a r e a l i n t e r r u p t h a d h a p p e n e d .
*
* Note : While M S R : E E i s o f f , w e n e e d t o m a k e s u r e t h a t _ M S R
* in t h e g e n e r a t e d f r a m e h a s E E s e t t o 1 o r t h e e x c e p t i o n
* handler w i l l n o t p r o p e r l y r e - e n a b l e t h e m .
* /
_ GLOBAL( _ _ r e p l a y _ i n t e r r u p t )
/ * We a r e g o i n g t o j u m p t o t h e e x c e p t i o n c o m m o n c o d e w h i c h
* will r e t r i e v e v a r i o u s r e g i s t e r v a l u e s f r o m t h e P A C A w h i c h
* we d o n ' t g i v e a d a m n a b o u t , s o w e d o n ' t b o t h e r s t o r i n g t h e m .
* /
mfmsr r12
mflr r11
mfcr r9
ori r12 ,r12 ,M S R _ E E
cmpwi r3 ,0 x90 0
beq d e c r e m e n t e r _ c o m m o n
cmpwi r3 ,0 x50 0
beq h a r d w a r e _ i n t e r r u p t _ c o m m o n
BEGIN_ F T R _ S E C T I O N
cmpwi r3 ,0 x e 8 0
beq h _ d o o r b e l l _ c o m m o n
cmpwi r3 ,0 x e a0
beq h _ v i r t _ i r q _ c o m m o n
cmpwi r3 ,0 x e 6 0
beq h m i _ e x c e p t i o n _ c o m m o n
FTR_ S E C T I O N _ E L S E
cmpwi r3 ,0 x a00
beq d o o r b e l l _ s u p e r _ c o m m o n
ALT_ F T R _ S E C T I O N _ E N D _ I F S E T ( C P U _ F T R _ H V M O D E )
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