ARM: mvebu: fix cpuidle implementation to work on big-endian systems
On Marvell Armada XP, when a CPU comes back from deep idle state of
cpuidle, it restarts its execution at armada_370_xp_cpu_resume(),
which puts back the CPU into the coherency, and then calls the generic
cpu_resume() function.
While this works on little-endian configurations, it doesn't work on
big-endian configurations because the CPU restarts in little-endian,
and therefore must be switched back to big-endian to operate
properly. To achieve this, a 'setend be' instruction must be executed
in big-endian configurations. However, the ARM_BE8() macro that is
used to implement nice compile-time conditional for ARM LE vs. ARM BE8
is not easily usable in inline assembly.
Therefore, this patch moves the armada_370_xp_cpu_resume() C function,
which was anyway just a block of inline assembly, into a proper
pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be)
instruction.
Without this patch, an Armada XP big endian configuration with cpuidle
enabled fails to boot, as it hangs as soon as one of the CPU hits the
deep idle state.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404130165-3593-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 16:09:25 +04:00
/ *
* Copyright ( C ) 2 0 1 4 M a r v e l l
*
* Thomas P e t a z z o n i < t h o m a s . p e t a z z o n i @free-electrons.com>
* Gregory C l e m e n t < g r e g o r y . c l e m e n t @free-electrons.com>
*
* This f i l e i s l i c e n s e d u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c
* License v e r s i o n 2 . T h i s p r o g r a m i s l i c e n s e d " a s i s " w i t h o u t a n y
* warranty o f a n y k i n d , w h e t h e r e x p r e s s o r i m p l i e d .
* /
# include < l i n u x / l i n k a g e . h >
# include < a s m / a s s e m b l e r . h >
/ *
* This i s t h e e n t r y p o i n t t h r o u g h w h i c h C P U s e x i t i n g c p u i d l e d e e p
* idle s t a t e a r e g o i n g .
* /
ENTRY( a r m a d a _ 3 7 0 _ x p _ c p u _ r e s u m e )
ARM_ B E 8 ( s e t e n d b e ) @ go BE8 if entered LE
bl l l _ a d d _ c p u _ t o _ s m p _ g r o u p
bl l l _ e n a b l e _ c o h e r e n c y
b c p u _ r e s u m e
ENDPROC( a r m a d a _ 3 7 0 _ x p _ c p u _ r e s u m e )
2014-07-23 17:00:52 +04:00
ENTRY( a r m a d a _ 3 8 x _ c p u _ r e s u m e )
/* do we need it for Armada 38x*/
ARM_ B E 8 ( s e t e n d b e ) @ go BE8 if entered LE
bl v7 _ i n v a l i d a t e _ l 1
mrc p15 , 4 , r1 , c15 , c0 @ get SCU base address
orr r1 , r1 , #0x8 @ SCU CPU Power Status Register
mrc 1 5 , 0 , r0 , c r0 , c r0 , 5 @ get the CPU ID
and r0 , r0 , #15
add r1 , r1 , r0
mov r0 , #0x0
strb r0 , [ r1 ] @ switch SCU power state to Normal mode
b c p u _ r e s u m e
ENDPROC( a r m a d a _ 3 8 x _ c p u _ r e s u m e )
2014-07-23 17:00:40 +04:00
.global mvebu_boot_wa_start
.global mvebu_boot_wa_end
/* The following code will be executed from SRAM */
ENTRY( m v e b u _ b o o t _ w a _ s t a r t )
mvebu_boot_wa_start :
ARM_ B E 8 ( s e t e n d b e )
adr r0 , 1 f
ldr r0 , [ r0 ] @ load the address of the
@ resume register
ldr r0 , [ r0 ] @ load the value in the
@ resume register
ARM_ B E 8 ( r e v r0 , r0 ) @ the value is stored LE
mov p c , r0 @ jump to this value
/ *
* the l a s t w o r d o f t h i s p i e c e o f c o d e w i l l b e f i l l e d b y t h e p h y s i c a l
* address o f t h e b o o t a d d r e s s r e g i s t e r j u s t a f t e r b e i n g c o p i e d i n S R A M
* /
1 :
.long .
mvebu_boot_wa_end :
ENDPROC( m v e b u _ b o o t _ w a _ e n d )
