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// SPDX-License-Identifier: GPL-2.0-only
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/*
* linux / arch / arm / kernel / smp . c
*
* Copyright ( C ) 2002 ARM Limited , All Rights Reserved .
*/
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# include <linux/module.h>
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# include <linux/delay.h>
# include <linux/init.h>
# include <linux/spinlock.h>
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# include <linux/sched/mm.h>
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# include <linux/sched/hotplug.h>
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# include <linux/sched/task_stack.h>
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# include <linux/interrupt.h>
# include <linux/cache.h>
# include <linux/profile.h>
# include <linux/errno.h>
# include <linux/mm.h>
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# include <linux/err.h>
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# include <linux/cpu.h>
# include <linux/seq_file.h>
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# include <linux/irq.h>
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# include <linux/nmi.h>
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# include <linux/percpu.h>
# include <linux/clockchips.h>
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# include <linux/completion.h>
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# include <linux/cpufreq.h>
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# include <linux/irq_work.h>
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# include <linux/kernel_stat.h>
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# include <linux/atomic.h>
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# include <asm/bugs.h>
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# include <asm/smp.h>
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# include <asm/cacheflush.h>
# include <asm/cpu.h>
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# include <asm/cputype.h>
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# include <asm/exception.h>
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# include <asm/idmap.h>
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# include <asm/topology.h>
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# include <asm/mmu_context.h>
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# include <asm/procinfo.h>
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# include <asm/processor.h>
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# include <asm/sections.h>
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# include <asm/tlbflush.h>
# include <asm/ptrace.h>
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# include <asm/smp_plat.h>
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# include <asm/virt.h>
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# include <asm/mach/arch.h>
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# include <asm/mpu.h>
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# define CREATE_TRACE_POINTS
# include <trace/events/ipi.h>
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/*
* as from 2.5 , kernels no longer have an init_tasks structure
* so we need some other way of telling a new secondary core
* where to place its SVC stack
*/
struct secondary_data secondary_data ;
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enum ipi_msg_type {
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IPI_WAKEUP ,
IPI_TIMER ,
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IPI_RESCHEDULE ,
IPI_CALL_FUNC ,
IPI_CPU_STOP ,
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IPI_IRQ_WORK ,
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IPI_COMPLETION ,
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NR_IPI ,
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/*
* CPU_BACKTRACE is special and not included in NR_IPI
* or tracable with trace_ipi_ *
*/
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
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IPI_CPU_BACKTRACE = NR_IPI ,
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/*
* SGI8 - 15 can be reserved by secure firmware , and thus may
* not be usable by the kernel . Please keep the above limited
* to at most 8 entries .
*/
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
MAX_IPI
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} ;
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
static int ipi_irq_base __read_mostly ;
static int nr_ipi __read_mostly = NR_IPI ;
static struct irq_desc * ipi_desc [ MAX_IPI ] __read_mostly ;
static void ipi_setup ( int cpu ) ;
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static DECLARE_COMPLETION ( cpu_running ) ;
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static struct smp_operations smp_ops __ro_after_init ;
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void __init smp_set_ops ( const struct smp_operations * ops )
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{
if ( ops )
smp_ops = * ops ;
} ;
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static unsigned long get_arch_pgd ( pgd_t * pgd )
{
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# ifdef CONFIG_ARM_LPAE
return __phys_to_pfn ( virt_to_phys ( pgd ) ) ;
# else
return virt_to_phys ( pgd ) ;
# endif
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}
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# if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
static int secondary_biglittle_prepare ( unsigned int cpu )
{
if ( ! cpu_vtable [ cpu ] )
cpu_vtable [ cpu ] = kzalloc ( sizeof ( * cpu_vtable [ cpu ] ) , GFP_KERNEL ) ;
return cpu_vtable [ cpu ] ? 0 : - ENOMEM ;
}
static void secondary_biglittle_init ( void )
{
init_proc_vtable ( lookup_processor ( read_cpuid_id ( ) ) - > proc ) ;
}
# else
static int secondary_biglittle_prepare ( unsigned int cpu )
{
return 0 ;
}
static void secondary_biglittle_init ( void )
{
}
# endif
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int __cpu_up ( unsigned int cpu , struct task_struct * idle )
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{
int ret ;
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if ( ! smp_ops . smp_boot_secondary )
return - ENOSYS ;
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ret = secondary_biglittle_prepare ( cpu ) ;
if ( ret )
return ret ;
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/*
* We need to tell the secondary core where to find
* its stack and the page tables .
*/
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secondary_data . stack = task_stack_page ( idle ) + THREAD_START_SP ;
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# ifdef CONFIG_ARM_MPU
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secondary_data . mpu_rgn_info = & mpu_rgn_info ;
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# endif
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# ifdef CONFIG_MMU
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secondary_data . pgdir = virt_to_phys ( idmap_pgd ) ;
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secondary_data . swapper_pg_dir = get_arch_pgd ( swapper_pg_dir ) ;
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# endif
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sync_cache_w ( & secondary_data ) ;
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/*
* Now bring the CPU into our world .
*/
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ret = smp_ops . smp_boot_secondary ( cpu , idle ) ;
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if ( ret = = 0 ) {
/*
* CPU was successfully started , wait for it
* to come online or time out .
*/
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wait_for_completion_timeout ( & cpu_running ,
msecs_to_jiffies ( 1000 ) ) ;
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if ( ! cpu_online ( cpu ) ) {
pr_crit ( " CPU%u: failed to come online \n " , cpu ) ;
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ret = - EIO ;
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}
} else {
pr_err ( " CPU%u: failed to boot: %d \n " , cpu , ret ) ;
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}
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memset ( & secondary_data , 0 , sizeof ( secondary_data ) ) ;
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return ret ;
}
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/* platform specific SMP operations */
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void __init smp_init_cpus ( void )
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{
if ( smp_ops . smp_init_cpus )
smp_ops . smp_init_cpus ( ) ;
}
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int platform_can_secondary_boot ( void )
{
return ! ! smp_ops . smp_boot_secondary ;
}
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int platform_can_cpu_hotplug ( void )
{
# ifdef CONFIG_HOTPLUG_CPU
if ( smp_ops . cpu_kill )
return 1 ;
# endif
return 0 ;
}
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# ifdef CONFIG_HOTPLUG_CPU
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static int platform_cpu_kill ( unsigned int cpu )
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{
if ( smp_ops . cpu_kill )
return smp_ops . cpu_kill ( cpu ) ;
return 1 ;
}
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static int platform_cpu_disable ( unsigned int cpu )
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{
if ( smp_ops . cpu_disable )
return smp_ops . cpu_disable ( cpu ) ;
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return 0 ;
}
int platform_can_hotplug_cpu ( unsigned int cpu )
{
/* cpu_die must be specified to support hotplug */
if ( ! smp_ops . cpu_die )
return 0 ;
if ( smp_ops . cpu_can_disable )
return smp_ops . cpu_can_disable ( cpu ) ;
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/*
* By default , allow disabling all CPUs except the first one ,
* since this is special on a lot of platforms , e . g . because
* of clock tick interrupts .
*/
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return cpu ! = 0 ;
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}
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static void ipi_teardown ( int cpu )
{
int i ;
if ( WARN_ON_ONCE ( ! ipi_irq_base ) )
return ;
for ( i = 0 ; i < nr_ipi ; i + + )
disable_percpu_irq ( ipi_irq_base + i ) ;
}
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/*
* __cpu_disable runs on the processor to be shutdown .
*/
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int __cpu_disable ( void )
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{
unsigned int cpu = smp_processor_id ( ) ;
int ret ;
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ret = platform_cpu_disable ( cpu ) ;
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if ( ret )
return ret ;
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# ifdef CONFIG_GENERIC_ARCH_TOPOLOGY
remove_cpu_topology ( cpu ) ;
# endif
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/*
* Take this CPU offline . Once we clear this , we can ' t return ,
* and we must not schedule until we ' re ready to give up the cpu .
*/
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set_cpu_online ( cpu , false ) ;
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
ipi_teardown ( cpu ) ;
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/*
* OK - migrate IRQs away from this CPU
*/
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irq_migrate_all_off_this_cpu ( ) ;
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/*
* Flush user cache and TLB mappings , and then remove this CPU
* from the vm mask set of all processes .
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*
* Caches are flushed to the Level of Unification Inner Shareable
* to write - back dirty lines to unified caches shared by all CPUs .
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*/
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flush_cache_louis ( ) ;
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local_flush_tlb_all ( ) ;
return 0 ;
}
/*
* called on the thread which is asking for a CPU to be shutdown -
* waits until shutdown has completed , or it is timed out .
*/
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void __cpu_die ( unsigned int cpu )
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{
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if ( ! cpu_wait_death ( cpu , 5 ) ) {
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pr_err ( " CPU%u: cpu didn't die \n " , cpu ) ;
return ;
}
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pr_debug ( " CPU%u: shutdown \n " , cpu ) ;
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clear_tasks_mm_cpumask ( cpu ) ;
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/*
* platform_cpu_kill ( ) is generally expected to do the powering off
* and / or cutting of clocks to the dying CPU . Optionally , this may
* be done by the CPU which is dying in preference to supporting
* this call , but that means there is _no_ synchronisation between
* the requesting CPU and the dying CPU actually losing power .
*/
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if ( ! platform_cpu_kill ( cpu ) )
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pr_err ( " CPU%u: unable to kill \n " , cpu ) ;
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}
/*
* Called from the idle thread for the CPU which has been shutdown .
*
* Note that we disable IRQs here , but do not re - enable them
* before returning to the caller . This is also the behaviour
* of the other hotplug - cpu capable cores , so presumably coming
* out of idle fixes this .
*/
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void arch_cpu_idle_dead ( void )
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{
unsigned int cpu = smp_processor_id ( ) ;
idle_task_exit ( ) ;
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local_irq_disable ( ) ;
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/*
* Flush the data out of the L1 cache for this CPU . This must be
* before the completion to ensure that data is safely written out
* before platform_cpu_kill ( ) gets called - which may disable
* * this * CPU and power down its cache .
*/
flush_cache_louis ( ) ;
/*
* Tell __cpu_die ( ) that this CPU is now safe to dispose of . Once
* this returns , power and / or clocks can be removed at any point
* from this CPU and its cache by platform_cpu_kill ( ) .
*/
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( void ) cpu_report_death ( ) ;
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/*
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* Ensure that the cache lines associated with that completion are
* written out . This covers the case where _this_ CPU is doing the
* powering down , to ensure that the completion is visible to the
* CPU waiting for this one .
*/
flush_cache_louis ( ) ;
/*
* The actual CPU shutdown procedure is at least platform ( if not
* CPU ) specific . This may remove power , or it may simply spin .
*
* Platforms are generally expected * NOT * to return from this call ,
* although there are some which do because they have no way to
* power down the CPU . These platforms are the _only_ reason we
* have a return path which uses the fragment of assembly below .
*
* The return path should not be used for platforms which can
* power off the CPU .
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*/
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if ( smp_ops . cpu_die )
smp_ops . cpu_die ( cpu ) ;
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pr_warn ( " CPU%u: smp_ops.cpu_die() returned, trying to resuscitate \n " ,
cpu ) ;
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/*
* Do not return to the idle loop - jump back to the secondary
* cpu initialisation . There ' s some initialisation which needs
* to be repeated to undo the effects of taking the CPU offline .
*/
__asm__ ( " mov sp, %0 \n "
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" mov fp, #0 \n "
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" b secondary_start_kernel "
:
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: " r " ( task_stack_page ( current ) + THREAD_SIZE - 8 ) ) ;
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}
# endif /* CONFIG_HOTPLUG_CPU */
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/*
* Called by both boot and secondaries to move global data into
* per - processor storage .
*/
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static void smp_store_cpu_info ( unsigned int cpuid )
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{
struct cpuinfo_arm * cpu_info = & per_cpu ( cpu_data , cpuid ) ;
cpu_info - > loops_per_jiffy = loops_per_jiffy ;
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cpu_info - > cpuid = read_cpuid_id ( ) ;
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store_cpu_topology ( cpuid ) ;
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check_cpu_icache_size ( cpuid ) ;
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}
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/*
* This is the secondary CPU boot entry . We ' re using this CPUs
* idle thread stack , but a set of temporary page tables .
*/
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asmlinkage void secondary_start_kernel ( void )
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{
struct mm_struct * mm = & init_mm ;
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unsigned int cpu ;
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secondary_biglittle_init ( ) ;
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/*
* The identity mapping is uncached ( strongly ordered ) , so
* switch away from it before attempting any exclusive accesses .
*/
cpu_switch_mm ( mm - > pgd , mm ) ;
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local_flush_bp_all ( ) ;
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enter_lazy_tlb ( mm , current ) ;
local_flush_tlb_all ( ) ;
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/*
* All kernel threads share the same mm context ; grab a
* reference and switch to it .
*/
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cpu = smp_processor_id ( ) ;
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mmgrab ( mm ) ;
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current - > active_mm = mm ;
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cpumask_set_cpu ( cpu , mm_cpumask ( mm ) ) ;
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cpu_init ( ) ;
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# ifndef CONFIG_MMU
setup_vectors_base ( ) ;
# endif
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pr_debug ( " CPU%u: Booted secondary processor \n " , cpu ) ;
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preempt_disable ( ) ;
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trace_hardirqs_off ( ) ;
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/*
* Give the platform a chance to do its own initialisation .
*/
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if ( smp_ops . smp_secondary_init )
smp_ops . smp_secondary_init ( cpu ) ;
2005-06-18 12:33:31 +04:00
2008-09-07 18:57:22 +04:00
notify_cpu_starting ( cpu ) ;
2008-02-04 19:30:57 +03:00
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
ipi_setup ( cpu ) ;
2005-06-18 12:33:31 +04:00
calibrate_delay ( ) ;
smp_store_cpu_info ( cpu ) ;
/*
2011-06-20 19:46:01 +04:00
* OK , now it ' s safe to let the boot CPU continue . Wait for
* the CPU migration code to notice that the CPU is online
2012-01-18 19:59:45 +04:00
* before we continue - which happens after __cpu_up returns .
2005-06-18 12:33:31 +04:00
*/
2009-05-28 17:16:52 +04:00
set_cpu_online ( cpu , true ) ;
2018-05-10 15:00:43 +03:00
check_other_bugs ( ) ;
2012-01-18 19:59:45 +04:00
complete ( & cpu_running ) ;
2011-10-14 15:44:41 +04:00
local_irq_enable ( ) ;
local_fiq_enable ( ) ;
2015-08-25 15:52:09 +03:00
local_abt_enable ( ) ;
2011-10-14 15:44:41 +04:00
2005-06-18 12:33:31 +04:00
/*
* OK , it ' s off to the idle thread for us
*/
2016-02-26 21:43:40 +03:00
cpu_startup_entry ( CPUHP_AP_ONLINE_IDLE ) ;
2005-06-18 12:33:31 +04:00
}
2005-04-17 02:20:36 +04:00
void __init smp_cpus_done ( unsigned int max_cpus )
{
2015-01-04 22:01:23 +03:00
int cpu ;
unsigned long bogosum = 0 ;
for_each_online_cpu ( cpu )
bogosum + = per_cpu ( cpu_data , cpu ) . loops_per_jiffy ;
printk ( KERN_INFO " SMP: Total of %d processors activated "
" (%lu.%02lu BogoMIPS). \n " ,
num_online_cpus ( ) ,
bogosum / ( 500000 / HZ ) ,
( bogosum / ( 5000 / HZ ) ) % 100 ) ;
2012-02-17 20:54:28 +04:00
hyp_mode_check ( ) ;
2005-04-17 02:20:36 +04:00
}
void __init smp_prepare_boot_cpu ( void )
{
2012-11-29 23:39:54 +04:00
set_my_cpu_offset ( per_cpu_offset ( smp_processor_id ( ) ) ) ;
2005-04-17 02:20:36 +04:00
}
2010-12-03 14:09:48 +03:00
void __init smp_prepare_cpus ( unsigned int max_cpus )
2005-04-17 02:20:36 +04:00
{
2010-12-03 14:09:48 +03:00
unsigned int ncores = num_possible_cpus ( ) ;
2005-04-17 02:20:36 +04:00
2011-08-08 16:21:59 +04:00
init_cpu_topology ( ) ;
2010-12-03 14:09:48 +03:00
smp_store_cpu_info ( smp_processor_id ( ) ) ;
2005-04-17 02:20:36 +04:00
/*
2010-12-03 14:09:48 +03:00
* are we trying to boot more cores than exist ?
2005-04-17 02:20:36 +04:00
*/
2010-12-03 14:09:48 +03:00
if ( max_cpus > ncores )
max_cpus = ncores ;
2011-07-07 04:56:51 +04:00
if ( ncores > 1 & & max_cpus ) {
/*
* Initialise the present map , which describes the set of CPUs
* actually populated at the present time . A platform should
2013-01-14 19:54:28 +04:00
* re - initialize the map in the platforms smp_prepare_cpus ( )
* if present ! = possible ( e . g . physical hotplug ) .
2011-07-07 04:56:51 +04:00
*/
2012-03-29 09:08:30 +04:00
init_cpu_present ( cpu_possible_mask ) ;
2011-07-07 04:56:51 +04:00
2010-12-03 14:09:48 +03:00
/*
* Initialise the SCU if there are more than one CPU
* and let them know where to start .
*/
2013-01-14 19:54:28 +04:00
if ( smp_ops . smp_prepare_cpus )
smp_ops . smp_prepare_cpus ( max_cpus ) ;
2010-12-03 14:09:48 +03:00
}
2005-04-17 02:20:36 +04:00
}
2014-07-26 00:05:31 +04:00
static const char * ipi_types [ NR_IPI ] __tracepoint_string = {
2020-11-30 13:24:09 +03:00
[ IPI_WAKEUP ] = " CPU wakeup interrupts " ,
[ IPI_TIMER ] = " Timer broadcast interrupts " ,
[ IPI_RESCHEDULE ] = " Rescheduling interrupts " ,
[ IPI_CALL_FUNC ] = " Function call interrupts " ,
[ IPI_CPU_STOP ] = " CPU stop interrupts " ,
[ IPI_IRQ_WORK ] = " IRQ work interrupts " ,
[ IPI_COMPLETION ] = " completion interrupts " ,
2010-11-15 17:40:29 +03:00
} ;
2020-06-23 00:15:54 +03:00
static void smp_cross_call ( const struct cpumask * target , unsigned int ipinr ) ;
2014-07-26 00:05:31 +04:00
2010-11-15 17:33:51 +03:00
void show_ipi_list ( struct seq_file * p , int prec )
2005-04-17 02:20:36 +04:00
{
2010-11-15 17:40:29 +03:00
unsigned int cpu , i ;
2005-04-17 02:20:36 +04:00
2010-11-15 17:40:29 +03:00
for ( i = 0 ; i < NR_IPI ; i + + ) {
2020-09-25 18:22:00 +03:00
unsigned int irq ;
if ( ! ipi_desc [ i ] )
continue ;
irq = irq_desc_get_irq ( ipi_desc [ i ] ) ;
2010-11-15 17:40:29 +03:00
seq_printf ( p , " %*s%u: " , prec - 1 , " IPI " , i ) ;
2005-04-17 02:20:36 +04:00
2012-12-04 00:13:03 +04:00
for_each_online_cpu ( cpu )
2020-06-23 23:15:00 +03:00
seq_printf ( p , " %10u " , kstat_irqs_cpu ( irq , cpu ) ) ;
2005-04-17 02:20:36 +04:00
2010-11-15 17:40:29 +03:00
seq_printf ( p , " %s \n " , ipi_types [ i ] ) ;
}
2005-04-17 02:20:36 +04:00
}
2014-07-26 00:05:31 +04:00
void arch_send_call_function_ipi_mask ( const struct cpumask * mask )
{
smp_cross_call ( mask , IPI_CALL_FUNC ) ;
}
void arch_send_wakeup_ipi_mask ( const struct cpumask * mask )
{
smp_cross_call ( mask , IPI_WAKEUP ) ;
}
void arch_send_call_function_single_ipi ( int cpu )
{
2015-12-18 13:06:19 +03:00
smp_cross_call ( cpumask_of ( cpu ) , IPI_CALL_FUNC ) ;
2014-07-26 00:05:31 +04:00
}
# ifdef CONFIG_IRQ_WORK
void arch_irq_work_raise ( void )
{
2014-08-16 20:47:53 +04:00
if ( arch_irq_work_has_interrupt ( ) )
2014-07-26 00:05:31 +04:00
smp_cross_call ( cpumask_of ( smp_processor_id ( ) ) , IPI_IRQ_WORK ) ;
}
# endif
2009-05-17 21:58:34 +04:00
# ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
2012-10-30 16:13:42 +04:00
void tick_broadcast ( const struct cpumask * mask )
2009-05-17 21:58:34 +04:00
{
2010-12-20 17:47:19 +03:00
smp_cross_call ( mask , IPI_TIMER ) ;
2009-05-17 21:58:34 +04:00
}
2010-07-26 16:19:43 +04:00
# endif
2009-05-17 21:58:34 +04:00
2009-07-03 17:44:46 +04:00
static DEFINE_RAW_SPINLOCK ( stop_lock ) ;
2005-04-17 02:20:36 +04:00
/*
* ipi_cpu_stop - handle IPI from smp_send_stop ( )
*/
static void ipi_cpu_stop ( unsigned int cpu )
{
2017-05-16 21:42:33 +03:00
if ( system_state < = SYSTEM_RUNNING ) {
2009-07-03 17:44:46 +04:00
raw_spin_lock ( & stop_lock ) ;
2014-10-28 14:26:42 +03:00
pr_crit ( " CPU%u: stopping \n " , cpu ) ;
2010-07-26 16:31:27 +04:00
dump_stack ( ) ;
2009-07-03 17:44:46 +04:00
raw_spin_unlock ( & stop_lock ) ;
2010-07-26 16:31:27 +04:00
}
2005-04-17 02:20:36 +04:00
2009-05-28 17:16:52 +04:00
set_cpu_online ( cpu , false ) ;
2005-04-17 02:20:36 +04:00
local_fiq_disable ( ) ;
local_irq_disable ( ) ;
ARM: avoid Cortex-A9 livelock on tight dmb loops
machine_crash_nonpanic_core() does this:
while (1)
cpu_relax();
because the kernel has crashed, and we have no known safe way to deal
with the CPU. So, we place the CPU into an infinite loop which we
expect it to never exit - at least not until the system as a whole is
reset by some method.
In the absence of erratum 754327, this code assembles to:
b .
In other words, an infinite loop. When erratum 754327 is enabled,
this becomes:
1: dmb
b 1b
It has been observed that on some systems (eg, OMAP4) where, if a
crash is triggered, the system tries to kexec into the panic kernel,
but fails after taking the secondary CPU down - placing it into one
of these loops. This causes the system to livelock, and the most
noticable effect is the system stops after issuing:
Loading crashdump kernel...
to the system console.
The tested as working solution I came up with was to add wfe() to
these infinite loops thusly:
while (1) {
cpu_relax();
wfe();
}
which, without 754327 builds to:
1: wfe
b 1b
or with 754327 is enabled:
1: dmb
wfe
b 1b
Adding "wfe" does two things depending on the environment we're running
under:
- where we're running on bare metal, and the processor implements
"wfe", it stops us spinning endlessly in a loop where we're never
going to do any useful work.
- if we're running in a VM, it allows the CPU to be given back to the
hypervisor and rescheduled for other purposes (maybe a different VM)
rather than wasting CPU cycles inside a crashed VM.
However, in light of erratum 794072, Will Deacon wanted to see 10 nops
as well - which is reasonable to cover the case where we have erratum
754327 enabled _and_ we have a processor that doesn't implement the
wfe hint.
So, we now end up with:
1: wfe
b 1b
when erratum 754327 is disabled, or:
1: dmb
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
wfe
b 1b
when erratum 754327 is enabled. We also get the dmb + 10 nop
sequence elsewhere in the kernel, in terminating loops.
This is reasonable - it means we get the workaround for erratum
794072 when erratum 754327 is enabled, but still relinquish the dead
processor - either by placing it in a lower power mode when wfe is
implemented as such or by returning it to the hypervisior, or in the
case where wfe is a no-op, we use the workaround specified in erratum
794072 to avoid the problem.
These as two entirely orthogonal problems - the 10 nops addresses
erratum 794072, and the wfe is an optimisation that makes the system
more efficient when crashed either in terms of power consumption or
by allowing the host/other VMs to make use of the CPU.
I don't see any reason not to use kexec() inside a VM - it has the
potential to provide automated recovery from a failure of the VMs
kernel with the opportunity for saving a crashdump of the failure.
A panic() with a reboot timeout won't do that, and reading the
libvirt documentation, setting on_reboot to "preserve" won't either
(the documentation states "The preserve action for an on_reboot event
is treated as a destroy".) Surely it has to be a good thing to
avoiding having CPUs spinning inside a VM that is doing no useful
work.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2018-04-10 13:35:36 +03:00
while ( 1 ) {
2005-04-17 02:20:36 +04:00
cpu_relax ( ) ;
ARM: avoid Cortex-A9 livelock on tight dmb loops
machine_crash_nonpanic_core() does this:
while (1)
cpu_relax();
because the kernel has crashed, and we have no known safe way to deal
with the CPU. So, we place the CPU into an infinite loop which we
expect it to never exit - at least not until the system as a whole is
reset by some method.
In the absence of erratum 754327, this code assembles to:
b .
In other words, an infinite loop. When erratum 754327 is enabled,
this becomes:
1: dmb
b 1b
It has been observed that on some systems (eg, OMAP4) where, if a
crash is triggered, the system tries to kexec into the panic kernel,
but fails after taking the secondary CPU down - placing it into one
of these loops. This causes the system to livelock, and the most
noticable effect is the system stops after issuing:
Loading crashdump kernel...
to the system console.
The tested as working solution I came up with was to add wfe() to
these infinite loops thusly:
while (1) {
cpu_relax();
wfe();
}
which, without 754327 builds to:
1: wfe
b 1b
or with 754327 is enabled:
1: dmb
wfe
b 1b
Adding "wfe" does two things depending on the environment we're running
under:
- where we're running on bare metal, and the processor implements
"wfe", it stops us spinning endlessly in a loop where we're never
going to do any useful work.
- if we're running in a VM, it allows the CPU to be given back to the
hypervisor and rescheduled for other purposes (maybe a different VM)
rather than wasting CPU cycles inside a crashed VM.
However, in light of erratum 794072, Will Deacon wanted to see 10 nops
as well - which is reasonable to cover the case where we have erratum
754327 enabled _and_ we have a processor that doesn't implement the
wfe hint.
So, we now end up with:
1: wfe
b 1b
when erratum 754327 is disabled, or:
1: dmb
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
wfe
b 1b
when erratum 754327 is enabled. We also get the dmb + 10 nop
sequence elsewhere in the kernel, in terminating loops.
This is reasonable - it means we get the workaround for erratum
794072 when erratum 754327 is enabled, but still relinquish the dead
processor - either by placing it in a lower power mode when wfe is
implemented as such or by returning it to the hypervisior, or in the
case where wfe is a no-op, we use the workaround specified in erratum
794072 to avoid the problem.
These as two entirely orthogonal problems - the 10 nops addresses
erratum 794072, and the wfe is an optimisation that makes the system
more efficient when crashed either in terms of power consumption or
by allowing the host/other VMs to make use of the CPU.
I don't see any reason not to use kexec() inside a VM - it has the
potential to provide automated recovery from a failure of the VMs
kernel with the opportunity for saving a crashdump of the failure.
A panic() with a reboot timeout won't do that, and reading the
libvirt documentation, setting on_reboot to "preserve" won't either
(the documentation states "The preserve action for an on_reboot event
is treated as a destroy".) Surely it has to be a good thing to
avoiding having CPUs spinning inside a VM that is doing no useful
work.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2018-04-10 13:35:36 +03:00
wfe ( ) ;
}
2005-04-17 02:20:36 +04:00
}
2012-11-28 06:54:41 +04:00
static DEFINE_PER_CPU ( struct completion * , cpu_completion ) ;
int register_ipi_completion ( struct completion * completion , int cpu )
{
per_cpu ( cpu_completion , cpu ) = completion ;
return IPI_COMPLETION ;
}
static void ipi_complete ( unsigned int cpu )
{
complete ( per_cpu ( cpu_completion , cpu ) ) ;
}
2005-04-17 02:20:36 +04:00
/*
* Main handler for inter - processor interrupts
*/
2011-01-07 01:32:52 +03:00
asmlinkage void __exception_irq_entry do_IPI ( int ipinr , struct pt_regs * regs )
2011-10-06 18:18:14 +04:00
{
handle_IPI ( ipinr , regs ) ;
}
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
static void do_handle_IPI ( int ipinr )
2005-04-17 02:20:36 +04:00
{
unsigned int cpu = smp_processor_id ( ) ;
2020-06-23 23:15:00 +03:00
if ( ( unsigned ) ipinr < NR_IPI )
2015-06-19 23:37:56 +03:00
trace_ipi_entry_rcuidle ( ipi_types [ ipinr ] ) ;
2005-04-17 02:20:36 +04:00
2010-11-15 12:54:18 +03:00
switch ( ipinr ) {
2012-09-19 11:16:07 +04:00
case IPI_WAKEUP :
break ;
2012-10-30 15:17:01 +04:00
# ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
2010-11-15 12:54:18 +03:00
case IPI_TIMER :
2012-10-30 15:17:01 +04:00
tick_receive_broadcast ( ) ;
2010-11-15 12:54:18 +03:00
break ;
2012-10-30 15:17:01 +04:00
# endif
2005-04-17 02:20:36 +04:00
2010-11-15 12:54:18 +03:00
case IPI_RESCHEDULE :
2011-04-05 19:23:39 +04:00
scheduler_ipi ( ) ;
2010-11-15 12:54:18 +03:00
break ;
2005-04-17 02:20:36 +04:00
2010-11-15 12:54:18 +03:00
case IPI_CALL_FUNC :
generic_smp_call_function_interrupt ( ) ;
break ;
2005-04-17 02:20:36 +04:00
2010-11-15 12:54:18 +03:00
case IPI_CPU_STOP :
ipi_cpu_stop ( cpu ) ;
break ;
2005-04-17 02:20:36 +04:00
2013-10-29 23:32:56 +04:00
# ifdef CONFIG_IRQ_WORK
case IPI_IRQ_WORK :
irq_work_run ( ) ;
break ;
# endif
2012-11-28 06:54:41 +04:00
case IPI_COMPLETION :
ipi_complete ( cpu ) ;
break ;
2014-09-04 02:57:13 +04:00
case IPI_CPU_BACKTRACE :
2016-05-21 03:00:33 +03:00
printk_nmi_enter ( ) ;
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
nmi_cpu_backtrace ( get_irq_regs ( ) ) ;
2016-05-21 03:00:33 +03:00
printk_nmi_exit ( ) ;
2014-09-04 02:57:13 +04:00
break ;
2010-11-15 12:54:18 +03:00
default :
2014-10-28 14:26:42 +03:00
pr_crit ( " CPU%u: Unknown IPI message 0x%x \n " ,
cpu , ipinr ) ;
2010-11-15 12:54:18 +03:00
break ;
2005-04-17 02:20:36 +04:00
}
2014-07-26 00:05:31 +04:00
if ( ( unsigned ) ipinr < NR_IPI )
2015-06-19 23:37:56 +03:00
trace_ipi_exit_rcuidle ( ipi_types [ ipinr ] ) ;
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
}
/* Legacy version, should go away once all irqchips have been converted */
void handle_IPI ( int ipinr , struct pt_regs * regs )
{
struct pt_regs * old_regs = set_irq_regs ( regs ) ;
irq_enter ( ) ;
do_handle_IPI ( ipinr ) ;
irq_exit ( ) ;
2006-10-25 16:59:16 +04:00
set_irq_regs ( old_regs ) ;
2005-04-17 02:20:36 +04:00
}
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
static irqreturn_t ipi_handler ( int irq , void * data )
{
do_handle_IPI ( irq - ipi_irq_base ) ;
return IRQ_HANDLED ;
}
2020-06-23 00:15:54 +03:00
static void smp_cross_call ( const struct cpumask * target , unsigned int ipinr )
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
{
2020-06-23 00:15:54 +03:00
trace_ipi_raise_rcuidle ( target , ipi_types [ ipinr ] ) ;
__ipi_send_mask ( ipi_desc [ ipinr ] , target ) ;
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
}
static void ipi_setup ( int cpu )
{
int i ;
2020-06-23 00:15:54 +03:00
if ( WARN_ON_ONCE ( ! ipi_irq_base ) )
ARM: Allow IPIs to be handled as normal interrupts
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
the arch code to request them as if the were normal interrupts.
A standard handler is then called by the core IRQ code to deal
with the IPI.
This means that we don't need to call irq_enter/irq_exit, and
that we don't need to deal with set_irq_regs either. So let's
move the dispatcher into its own function, and leave handle_IPI()
as a compatibility function.
On the sending side, let's make use of ipi_send_mask, which
already exists for this purpose.
One of the major difference is that we end up, in some cases
(such as when performing IRQ time accounting on the scheduler
IPI), end up with nested irq_enter()/irq_exit() pairs.
Other than the (relatively small) overhead, there should be
no consequences to it (these pairs are designed to nest
correctly, and the accounting shouldn't be off).
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23 22:38:41 +03:00
return ;
for ( i = 0 ; i < nr_ipi ; i + + )
enable_percpu_irq ( ipi_irq_base + i , 0 ) ;
}
void __init set_smp_ipi_range ( int ipi_base , int n )
{
int i ;
WARN_ON ( n < MAX_IPI ) ;
nr_ipi = min ( n , MAX_IPI ) ;
for ( i = 0 ; i < nr_ipi ; i + + ) {
int err ;
err = request_percpu_irq ( ipi_base + i , ipi_handler ,
" IPI " , & irq_stat ) ;
WARN_ON ( err ) ;
ipi_desc [ i ] = irq_to_desc ( ipi_base + i ) ;
irq_set_status_flags ( ipi_base + i , IRQ_HIDDEN ) ;
}
ipi_irq_base = ipi_base ;
/* Setup the boot CPU immediately */
ipi_setup ( smp_processor_id ( ) ) ;
}
2005-04-17 02:20:36 +04:00
void smp_send_reschedule ( int cpu )
{
2010-12-20 17:47:19 +03:00
smp_cross_call ( cpumask_of ( cpu ) , IPI_RESCHEDULE ) ;
2005-04-17 02:20:36 +04:00
}
void smp_send_stop ( void )
{
2010-12-02 12:53:54 +03:00
unsigned long timeout ;
2012-04-27 15:51:43 +04:00
struct cpumask mask ;
2005-04-17 02:20:36 +04:00
2012-04-27 15:51:43 +04:00
cpumask_copy ( & mask , cpu_online_mask ) ;
cpumask_clear_cpu ( smp_processor_id ( ) , & mask ) ;
2012-07-28 18:19:55 +04:00
if ( ! cpumask_empty ( & mask ) )
smp_cross_call ( & mask , IPI_CPU_STOP ) ;
2005-06-28 16:49:16 +04:00
2010-12-02 12:53:54 +03:00
/* Wait up to one second for other CPUs to stop */
timeout = USEC_PER_SEC ;
while ( num_online_cpus ( ) > 1 & & timeout - - )
udelay ( 1 ) ;
2005-06-28 16:49:16 +04:00
2010-12-02 12:53:54 +03:00
if ( num_online_cpus ( ) > 1 )
2014-09-16 23:41:43 +04:00
pr_warn ( " SMP: failed to stop secondary CPUs \n " ) ;
2005-06-28 16:49:16 +04:00
}
2018-11-02 13:51:31 +03:00
/* In case panic() and panic() called at the same time on CPU1 and CPU2,
* and CPU 1 calls panic_smp_self_stop ( ) before crash_smp_send_stop ( )
* CPU1 can ' t receive the ipi irqs from CPU2 , CPU1 will be always online ,
* kdump fails . So split out the panic_smp_self_stop ( ) and add
* set_cpu_online ( smp_processor_id ( ) , false ) .
*/
void panic_smp_self_stop ( void )
{
pr_debug ( " CPU %u will stop doing anything useful since another CPU has paniced \n " ,
smp_processor_id ( ) ) ;
set_cpu_online ( smp_processor_id ( ) , false ) ;
while ( 1 )
cpu_relax ( ) ;
}
2005-06-28 16:49:16 +04:00
/*
2005-04-17 02:20:36 +04:00
* not supported here
2005-06-28 16:49:16 +04:00
*/
2007-07-23 15:59:46 +04:00
int setup_profiling_timer ( unsigned int multiplier )
2005-06-28 16:49:16 +04:00
{
2005-04-17 02:20:36 +04:00
return - EINVAL ;
2005-06-28 16:49:16 +04:00
}
2012-09-05 03:08:59 +04:00
# ifdef CONFIG_CPU_FREQ
static DEFINE_PER_CPU ( unsigned long , l_p_j_ref ) ;
static DEFINE_PER_CPU ( unsigned long , l_p_j_ref_freq ) ;
static unsigned long global_l_p_j_ref ;
static unsigned long global_l_p_j_ref_freq ;
static int cpufreq_callback ( struct notifier_block * nb ,
unsigned long val , void * data )
{
struct cpufreq_freqs * freq = data ;
2019-04-29 12:33:58 +03:00
struct cpumask * cpus = freq - > policy - > cpus ;
int cpu , first = cpumask_first ( cpus ) ;
unsigned int lpj ;
2012-09-05 03:08:59 +04:00
if ( freq - > flags & CPUFREQ_CONST_LOOPS )
return NOTIFY_OK ;
2019-04-29 12:33:58 +03:00
if ( ! per_cpu ( l_p_j_ref , first ) ) {
for_each_cpu ( cpu , cpus ) {
per_cpu ( l_p_j_ref , cpu ) =
per_cpu ( cpu_data , cpu ) . loops_per_jiffy ;
per_cpu ( l_p_j_ref_freq , cpu ) = freq - > old ;
}
2012-09-05 03:08:59 +04:00
if ( ! global_l_p_j_ref ) {
global_l_p_j_ref = loops_per_jiffy ;
global_l_p_j_ref_freq = freq - > old ;
}
}
if ( ( val = = CPUFREQ_PRECHANGE & & freq - > old < freq - > new ) | |
2014-03-19 09:54:58 +04:00
( val = = CPUFREQ_POSTCHANGE & & freq - > old > freq - > new ) ) {
2012-09-05 03:08:59 +04:00
loops_per_jiffy = cpufreq_scale ( global_l_p_j_ref ,
global_l_p_j_ref_freq ,
freq - > new ) ;
2019-04-29 12:33:58 +03:00
lpj = cpufreq_scale ( per_cpu ( l_p_j_ref , first ) ,
per_cpu ( l_p_j_ref_freq , first ) , freq - > new ) ;
for_each_cpu ( cpu , cpus )
per_cpu ( cpu_data , cpu ) . loops_per_jiffy = lpj ;
2012-09-05 03:08:59 +04:00
}
return NOTIFY_OK ;
}
static struct notifier_block cpufreq_notifier = {
. notifier_call = cpufreq_callback ,
} ;
static int __init register_cpufreq_notifier ( void )
{
return cpufreq_register_notifier ( & cpufreq_notifier ,
CPUFREQ_TRANSITION_NOTIFIER ) ;
}
core_initcall ( register_cpufreq_notifier ) ;
# endif
2014-09-04 02:57:13 +04:00
static void raise_nmi ( cpumask_t * mask )
{
2020-06-23 00:15:54 +03:00
__ipi_send_mask ( ipi_desc [ IPI_CPU_BACKTRACE ] , mask ) ;
2014-09-04 02:57:13 +04:00
}
nmi_backtrace: add more trigger_*_cpu_backtrace() methods
Patch series "improvements to the nmi_backtrace code" v9.
This patch series modifies the trigger_xxx_backtrace() NMI-based remote
backtracing code to make it more flexible, and makes a few small
improvements along the way.
The motivation comes from the task isolation code, where there are
scenarios where we want to be able to diagnose a case where some cpu is
about to interrupt a task-isolated cpu. It can be helpful to see both
where the interrupting cpu is, and also an approximation of where the
cpu that is being interrupted is. The nmi_backtrace framework allows us
to discover the stack of the interrupted cpu.
I've tested that the change works as desired on tile, and build-tested
x86, arm, mips, and sparc64. For x86 I confirmed that the generic
cpuidle stuff as well as the architecture-specific routines are in the
new cpuidle section. For arm, mips, and sparc I just build-tested it
and made sure the generic cpuidle routines were in the new cpuidle
section, but I didn't attempt to figure out which the platform-specific
idle routines might be. That might be more usefully done by someone
with platform experience in follow-up patches.
This patch (of 4):
Currently you can only request a backtrace of either all cpus, or all
cpus but yourself. It can also be helpful to request a remote backtrace
of a single cpu, and since we want that, the logical extension is to
support a cpumask as the underlying primitive.
This change modifies the existing lib/nmi_backtrace.c code to take a
cpumask as its basic primitive, and modifies the linux/nmi.h code to use
the new "cpumask" method instead.
The existing clients of nmi_backtrace (arm and x86) are converted to
using the new cpumask approach in this change.
The other users of the backtracing API (sparc64 and mips) are converted
to use the cpumask approach rather than the all/allbutself approach.
The mips code ignored the "include_self" boolean but with this change it
will now also dump a local backtrace if requested.
Link: http://lkml.kernel.org/r/1472487169-14923-2-git-send-email-cmetcalf@mellanox.com
Signed-off-by: Chris Metcalf <cmetcalf@mellanox.com>
Tested-by: Daniel Thompson <daniel.thompson@linaro.org> [arm]
Reviewed-by: Aaron Tomlin <atomlin@redhat.com>
Reviewed-by: Petr Mladek <pmladek@suse.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Miller <davem@davemloft.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-10-08 03:02:45 +03:00
void arch_trigger_cpumask_backtrace ( const cpumask_t * mask , bool exclude_self )
2014-09-04 02:57:13 +04:00
{
nmi_backtrace: add more trigger_*_cpu_backtrace() methods
Patch series "improvements to the nmi_backtrace code" v9.
This patch series modifies the trigger_xxx_backtrace() NMI-based remote
backtracing code to make it more flexible, and makes a few small
improvements along the way.
The motivation comes from the task isolation code, where there are
scenarios where we want to be able to diagnose a case where some cpu is
about to interrupt a task-isolated cpu. It can be helpful to see both
where the interrupting cpu is, and also an approximation of where the
cpu that is being interrupted is. The nmi_backtrace framework allows us
to discover the stack of the interrupted cpu.
I've tested that the change works as desired on tile, and build-tested
x86, arm, mips, and sparc64. For x86 I confirmed that the generic
cpuidle stuff as well as the architecture-specific routines are in the
new cpuidle section. For arm, mips, and sparc I just build-tested it
and made sure the generic cpuidle routines were in the new cpuidle
section, but I didn't attempt to figure out which the platform-specific
idle routines might be. That might be more usefully done by someone
with platform experience in follow-up patches.
This patch (of 4):
Currently you can only request a backtrace of either all cpus, or all
cpus but yourself. It can also be helpful to request a remote backtrace
of a single cpu, and since we want that, the logical extension is to
support a cpumask as the underlying primitive.
This change modifies the existing lib/nmi_backtrace.c code to take a
cpumask as its basic primitive, and modifies the linux/nmi.h code to use
the new "cpumask" method instead.
The existing clients of nmi_backtrace (arm and x86) are converted to
using the new cpumask approach in this change.
The other users of the backtracing API (sparc64 and mips) are converted
to use the cpumask approach rather than the all/allbutself approach.
The mips code ignored the "include_self" boolean but with this change it
will now also dump a local backtrace if requested.
Link: http://lkml.kernel.org/r/1472487169-14923-2-git-send-email-cmetcalf@mellanox.com
Signed-off-by: Chris Metcalf <cmetcalf@mellanox.com>
Tested-by: Daniel Thompson <daniel.thompson@linaro.org> [arm]
Reviewed-by: Aaron Tomlin <atomlin@redhat.com>
Reviewed-by: Petr Mladek <pmladek@suse.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Miller <davem@davemloft.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-10-08 03:02:45 +03:00
nmi_trigger_cpumask_backtrace ( mask , exclude_self , raise_nmi ) ;
2014-09-04 02:57:13 +04:00
}