2017-12-25 20:54:32 +01:00
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2003-2004 Simtec Electronics
// Ben Dooks <ben@simtec.co.uk>
//
2020-07-19 11:39:39 +02:00
// https://www.handhelds.org/projects/rx3715.html
2005-04-16 15:20:36 -07:00
# include <linux/kernel.h>
# include <linux/types.h>
# include <linux/interrupt.h>
# include <linux/list.h>
2010-05-22 19:47:18 +01:00
# include <linux/memblock.h>
2005-04-16 15:20:36 -07:00
# include <linux/timer.h>
# include <linux/init.h>
# include <linux/tty.h>
# include <linux/console.h>
2011-12-21 16:26:03 -08:00
# include <linux/device.h>
2005-10-29 19:07:23 +01:00
# include <linux/platform_device.h>
2005-04-16 15:20:36 -07:00
# include <linux/serial_core.h>
2014-02-14 10:32:45 +09:00
# include <linux/serial_s3c.h>
2005-04-16 15:20:36 -07:00
# include <linux/serial.h>
2008-09-06 12:10:45 +01:00
# include <linux/io.h>
2006-04-02 16:16:15 +01:00
# include <linux/mtd/mtd.h>
2017-08-04 17:29:10 +02:00
# include <linux/mtd/rawnand.h>
2020-09-30 01:01:15 +02:00
# include <linux/mtd/nand-ecc-sw-hamming.h>
2006-04-02 16:16:15 +01:00
# include <linux/mtd/partitions.h>
2005-04-16 15:20:36 -07:00
# include <asm/mach/arch.h>
# include <asm/mach/irq.h>
2013-01-02 10:18:58 -08:00
# include <asm/mach/map.h>
# include <linux/platform_data/mtd-nand-s3c2410.h>
2019-09-02 22:33:24 +02:00
# include <linux/platform_data/fb-s3c2410.h>
2005-04-16 15:20:36 -07:00
# include <asm/irq.h>
# include <asm/mach-types.h>
2019-09-02 18:37:30 +02:00
# include "regs-gpio.h"
# include "gpio-samsung.h"
# include "gpio-cfg.h"
2005-11-01 19:44:28 +00:00
2019-09-02 18:37:30 +02:00
# include "cpu.h"
# include "devs.h"
# include "pm.h"
2005-04-16 15:20:36 -07:00
2019-09-02 17:47:55 +02:00
# include "s3c24xx.h"
2013-01-02 10:18:58 -08:00
# include "h1940.h"
2012-01-03 14:02:03 +01:00
2005-04-16 15:20:36 -07:00
static struct map_desc rx3715_iodesc [ ] __initdata = {
/* dump ISA space somewhere unused */
2005-11-09 14:05:31 +00:00
{
. virtual = ( u32 ) S3C24XX_VA_ISA_WORD ,
. pfn = __phys_to_pfn ( S3C2410_CS3 ) ,
. length = SZ_1M ,
. type = MT_DEVICE ,
} , {
. virtual = ( u32 ) S3C24XX_VA_ISA_BYTE ,
. pfn = __phys_to_pfn ( S3C2410_CS3 ) ,
. length = SZ_1M ,
. type = MT_DEVICE ,
} ,
2005-04-16 15:20:36 -07:00
} ;
static struct s3c2410_uartcfg rx3715_uartcfgs [ ] = {
[ 0 ] = {
. hwport = 0 ,
. flags = 0 ,
. ucon = 0x3c5 ,
. ulcon = 0x03 ,
. ufcon = 0x51 ,
2011-10-24 11:47:51 +02:00
. clk_sel = S3C2410_UCON_CLKSEL3 ,
2005-04-16 15:20:36 -07:00
} ,
[ 1 ] = {
. hwport = 1 ,
. flags = 0 ,
. ucon = 0x3c5 ,
. ulcon = 0x03 ,
. ufcon = 0x00 ,
2011-10-24 11:47:51 +02:00
. clk_sel = S3C2410_UCON_CLKSEL3 ,
2005-04-16 15:20:36 -07:00
} ,
/* IR port */
[ 2 ] = {
. hwport = 2 ,
. uart_flags = UPF_CONS_FLOW ,
. ucon = 0x3c5 ,
. ulcon = 0x43 ,
. ufcon = 0x51 ,
2011-10-24 11:47:51 +02:00
. clk_sel = S3C2410_UCON_CLKSEL3 ,
2005-04-16 15:20:36 -07:00
}
} ;
2005-11-01 19:44:28 +00:00
/* framebuffer lcd controller information */
2007-10-16 01:28:56 -07:00
static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
2007-10-16 01:28:58 -07:00
. lcdcon5 = S3C2410_LCDCON5_INVVLINE |
S3C2410_LCDCON5_FRM565 |
S3C2410_LCDCON5_HWSWP ,
2005-11-01 19:44:28 +00:00
2007-10-16 01:28:57 -07:00
. type = S3C2410_LCDCON1_TFT ,
. width = 240 ,
. height = 320 ,
2007-10-16 01:29:06 -07:00
. pixclock = 260000 ,
2007-10-16 01:28:57 -07:00
. xres = 240 ,
. yres = 320 ,
. bpp = 16 ,
. left_margin = 36 ,
. right_margin = 36 ,
2007-10-16 01:29:00 -07:00
. hsync_len = 8 ,
2007-10-16 01:28:59 -07:00
. upper_margin = 6 ,
. lower_margin = 7 ,
2007-10-16 01:29:00 -07:00
. vsync_len = 3 ,
2007-10-16 01:28:56 -07:00
} ;
static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
. displays = & rx3715_lcdcfg ,
. num_displays = 1 ,
. default_display = 0 ,
2005-11-01 19:44:28 +00:00
. lpcsel = 0xf82 ,
. gpccon = 0xaa955699 ,
. gpccon_mask = 0xffc003cc ,
2019-09-02 22:33:24 +02:00
. gpccon_reg = S3C2410_GPCCON ,
2005-11-01 19:44:28 +00:00
. gpcup = 0x0000ffff ,
. gpcup_mask = 0xffffffff ,
2019-09-02 22:33:24 +02:00
. gpcup_reg = S3C2410_GPCUP ,
2005-11-01 19:44:28 +00:00
. gpdcon = 0xaa95aaa1 ,
. gpdcon_mask = 0xffc0fff0 ,
2019-09-02 22:33:24 +02:00
. gpdcon_reg = S3C2410_GPDCON ,
2005-11-01 19:44:28 +00:00
. gpdup = 0x0000faff ,
. gpdup_mask = 0xffffffff ,
2019-09-02 22:33:24 +02:00
. gpdup_reg = S3C2410_GPDUP ,
2005-11-01 19:44:28 +00:00
} ;
2009-09-28 13:59:49 +03:00
static struct mtd_partition __initdata rx3715_nand_part [ ] = {
2006-04-02 16:16:15 +01:00
[ 0 ] = {
. name = " Whole Flash " ,
. offset = 0 ,
. size = MTDPART_SIZ_FULL ,
. mask_flags = MTD_WRITEABLE ,
}
} ;
2009-09-28 13:59:49 +03:00
static struct s3c2410_nand_set __initdata rx3715_nand_sets [ ] = {
2006-04-02 16:16:15 +01:00
[ 0 ] = {
. name = " Internal " ,
. nr_chips = 1 ,
. nr_partitions = ARRAY_SIZE ( rx3715_nand_part ) ,
. partitions = rx3715_nand_part ,
} ,
} ;
2009-09-28 13:59:49 +03:00
static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
2006-04-02 16:16:15 +01:00
. tacls = 25 ,
. twrph0 = 50 ,
. twrph1 = 15 ,
. nr_sets = ARRAY_SIZE ( rx3715_nand_sets ) ,
. sets = rx3715_nand_sets ,
2020-08-27 10:51:58 +02:00
. engine_type = NAND_ECC_ENGINE_TYPE_SOFT ,
2006-04-02 16:16:15 +01:00
} ;
2005-04-16 15:20:36 -07:00
static struct platform_device * rx3715_devices [ ] __initdata = {
2009-11-23 00:13:39 +00:00
& s3c_device_ohci ,
2005-04-16 15:20:36 -07:00
& s3c_device_lcd ,
& s3c_device_wdt ,
2008-10-31 16:14:40 +00:00
& s3c_device_i2c0 ,
2005-04-16 15:20:36 -07:00
& s3c_device_iis ,
2006-04-02 16:16:15 +01:00
& s3c_device_nand ,
2005-04-16 15:20:36 -07:00
} ;
2005-09-20 17:24:33 +01:00
static void __init rx3715_map_io ( void )
2005-04-16 15:20:36 -07:00
{
s3c24xx_init_io ( rx3715_iodesc , ARRAY_SIZE ( rx3715_iodesc ) ) ;
s3c24xx_init_uarts ( rx3715_uartcfgs , ARRAY_SIZE ( rx3715_uartcfgs ) ) ;
2020-08-20 22:42:03 +02:00
s3c24xx_set_timer_source ( S3C24XX_PWM3 , S3C24XX_PWM4 ) ;
2005-04-16 15:20:36 -07:00
}
2014-05-09 05:49:19 +09:00
static void __init rx3715_init_time ( void )
{
s3c2440_init_clocks ( 16934000 ) ;
2020-08-20 22:42:03 +02:00
s3c24xx_timer_init ( ) ;
2014-05-09 05:49:19 +09:00
}
2010-05-22 18:18:57 +01:00
/* H1940 and RX3715 need to reserve this for suspend */
static void __init rx3715_reserve ( void )
{
2010-05-22 19:47:18 +01:00
memblock_reserve ( 0x30003000 , 0x1000 ) ;
memblock_reserve ( 0x30081000 , 0x1000 ) ;
2010-05-22 18:18:57 +01:00
}
2005-04-16 15:20:36 -07:00
static void __init rx3715_init_machine ( void )
{
2007-03-19 15:10:20 +01:00
# ifdef CONFIG_PM_H1940
2006-12-07 20:47:58 +01:00
memcpy ( phys_to_virt ( H1940_SUSPEND_RESUMEAT ) , h1940_pm_return , 1024 ) ;
2007-03-19 15:10:20 +01:00
# endif
2008-12-12 00:24:18 +00:00
s3c_pm_init ( ) ;
2006-12-07 20:47:58 +01:00
2009-09-28 13:59:49 +03:00
s3c_nand_set_platdata ( & rx3715_nand_info ) ;
2007-10-16 01:28:56 -07:00
s3c24xx_fb_set_platdata ( & rx3715_fb_info ) ;
2020-08-06 20:20:45 +02:00
/* Configure the I2S pins (GPE0...GPE4) in correct mode */
s3c_gpio_cfgall_range ( S3C2410_GPE ( 0 ) , 5 , S3C_GPIO_SFN ( 2 ) ,
S3C_GPIO_PULL_NONE ) ;
2007-04-20 11:19:16 +01:00
platform_add_devices ( rx3715_devices , ARRAY_SIZE ( rx3715_devices ) ) ;
2005-04-16 15:20:36 -07:00
}
2005-11-01 19:44:28 +00:00
2005-04-16 15:20:36 -07:00
MACHINE_START ( RX3715 , " IPAQ-RX3715 " )
2010-05-07 09:24:05 +09:00
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
2011-07-05 22:38:17 -04:00
. atag_offset = 0x100 ,
2005-07-03 17:38:58 +01:00
. map_io = rx3715_map_io ,
2010-05-22 18:18:57 +01:00
. reserve = rx3715_reserve ,
2013-02-12 09:59:20 -08:00
. init_irq = s3c2440_init_irq ,
2005-07-03 17:38:58 +01:00
. init_machine = rx3715_init_machine ,
2014-05-09 05:49:19 +09:00
. init_time = rx3715_init_time ,
2005-04-16 15:20:36 -07:00
MACHINE_END