blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
/ *
* File : arch/ b l a c k f i n / m a c h - b f53 3 / h e a d . S
* Based o n :
* Author : Jeff D i o n n e < j e f f @uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
*
* Created : 1 9 9 8
* Description : bf5 3 3 s t a r t u p f i l e
*
* Modified :
* Copyright 2 0 0 4 - 2 0 0 6 A n a l o g D e v i c e s I n c .
*
* Bugs : Enter b u g s a t h t t p : / / b l a c k f i n . u c l i n u x . o r g /
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify
* it u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e a s p u b l i s h e d b y
* the F r e e S o f t w a r e F o u n d a t i o n ; either version 2 of the License, or
* ( at y o u r o p t i o n ) a n y l a t e r v e r s i o n .
*
* This p r o g r a m i s d i s t r i b u t e d i n t h e h o p e t h a t i t w i l l b e u s e f u l ,
* but W I T H O U T A N Y W A R R A N T Y ; without even the implied warranty of
* MERCHANTABILITY o r F I T N E S S F O R A P A R T I C U L A R P U R P O S E . S e e t h e
* GNU G e n e r a l P u b l i c L i c e n s e f o r m o r e d e t a i l s .
*
* You s h o u l d h a v e r e c e i v e d a c o p y o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* along w i t h t h i s p r o g r a m ; if not, see the file COPYING, or write
* to t h e F r e e S o f t w a r e F o u n d a t i o n , I n c . ,
* 5 1 Franklin S t , F i f t h F l o o r , B o s t o n , M A 0 2 1 1 0 - 1 3 0 1 U S A
* /
# include < l i n u x / l i n k a g e . h >
2007-06-11 15:31:30 +08:00
# include < l i n u x / i n i t . h >
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
# include < a s m / b l a c k f i n . h >
2007-06-21 16:34:08 +08:00
# include < a s m / t r a c e . h >
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
# if C O N F I G _ B F I N _ K E R N E L _ C L O C K
# include < a s m / m a c h / m e m _ i n i t . h >
# endif
# if C O N F I G _ D E B U G _ K E R N E L _ S T A R T
# include < a s m / m a c h - c o m m o n / d e f _ L P B l a c k f i n . h >
# endif
.global __rambase
.global __ramstart
.global __ramend
.extern ___bss_stop
.extern ___bss_start
.extern _bf53x_relocate_l1_mem
# define I N I T I A L _ S T A C K 0 x F F B 0 1 0 0 0
2007-06-11 15:31:30 +08:00
_ _ INIT
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
ENTRY( _ _ s t a r t )
/* R0: argument of command line string, passed from uboot, save it */
R7 = R 0 ;
2007-06-11 15:31:30 +08:00
/ * Set t h e S Y S C F G r e g i s t e r :
* Enable C y c l e C o u n t e r a n d N e s t i n g O f I n t e r r u p t s ( 3 r d B i t )
* /
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
R0 = 0 x36 ;
SYSCFG = R 0 ;
R0 = 0 ;
2007-06-11 15:31:30 +08:00
/* Clear Out All the data and pointer Registers */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
R1 = R 0 ;
R2 = R 0 ;
R3 = R 0 ;
R4 = R 0 ;
R5 = R 0 ;
R6 = R 0 ;
P0 = R 0 ;
P1 = R 0 ;
P2 = R 0 ;
P3 = R 0 ;
P4 = R 0 ;
P5 = R 0 ;
LC0 = r0 ;
LC1 = r0 ;
L0 = r0 ;
L1 = r0 ;
L2 = r0 ;
L3 = r0 ;
2007-06-11 15:31:30 +08:00
/* Clear Out All the DAG Registers */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
B0 = r0 ;
B1 = r0 ;
B2 = r0 ;
B3 = r0 ;
I0 = r0 ;
I1 = r0 ;
I2 = r0 ;
I3 = r0 ;
M0 = r0 ;
M1 = r0 ;
M2 = r0 ;
M3 = r0 ;
2007-06-21 16:34:08 +08:00
trace_ b u f f e r _ s t a r t ( p0 ,r0 ) ;
P0 = R 1 ;
R0 = R 1 ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
# if C O N F I G _ D E B U G _ K E R N E L _ S T A R T
/ *
* Set u p a t e m p o r a r y E v e n t V e c t o r T a b l e , s o i f s o m e t h i n g b a d h a p p e n s b e f o r e
* the k e r n e l i s f u l l y s t a r t e d , i t d o e s n ' t v e c t o r o f f i n t o t h e b o o t l o a d e r s
* table
* /
P0 . l = l o ( E V T 2 ) ;
P0 . h = h i ( E V T 2 ) ;
P1 . l = l o ( E V T 1 5 ) ;
P1 . h = h i ( E V T 1 5 ) ;
P2 . l = d e b u g _ k e r n e l _ s t a r t _ t r a p ;
P2 . h = d e b u g _ k e r n e l _ s t a r t _ t r a p ;
RTS = P 2 ;
RTI = P 2 ;
RTX = P 2 ;
RTN = P 2 ;
RTE = P 2 ;
.Lfill_temp_vector_table :
[ P0 + + ] = P 2 ; /* Core Event Vector Table */
CC = P 0 = = P 1 ;
if ! C C J U M P . L f i l l _ t e m p _ v e c t o r _ t a b l e
P0 = r0 ;
P1 = r0 ;
P2 = r0 ;
# endif
p0 . h = h i ( F I O _ M A S K A _ C ) ;
p0 . l = l o ( F I O _ M A S K A _ C ) ;
r0 = 0 x F F F F ( Z ) ;
w[ p0 ] = r0 . L ; /* Disable all interrupts */
ssync;
p0 . h = h i ( F I O _ M A S K B _ C ) ;
p0 . l = l o ( F I O _ M A S K B _ C ) ;
r0 = 0 x F F F F ( Z ) ;
w[ p0 ] = r0 . L ; /* Disable all interrupts */
ssync;
/* Turn off the icache */
p0 . l = ( I M E M _ C O N T R O L & 0 x F F F F ) ;
p0 . h = ( I M E M _ C O N T R O L > > 1 6 ) ;
R1 = [ p0 ] ;
R0 = ~ E N I C P L B ;
R0 = R 0 & R 1 ;
/* Anomaly 05000125 */
2007-07-25 11:19:14 +08:00
# if A N O M A L Y _ 0 5 0 0 0 1 2 5
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
CLI R 2 ;
SSYNC;
# endif
[ p0 ] = R 0 ;
SSYNC;
2007-07-25 11:19:14 +08:00
# if A N O M A L Y _ 0 5 0 0 0 1 2 5
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
STI R 2 ;
# endif
/* Turn off the dcache */
p0 . l = ( D M E M _ C O N T R O L & 0 x F F F F ) ;
p0 . h = ( D M E M _ C O N T R O L > > 1 6 ) ;
R1 = [ p0 ] ;
R0 = ~ E N D C P L B ;
R0 = R 0 & R 1 ;
/* Anomaly 05000125 */
2007-07-25 11:19:14 +08:00
# if A N O M A L Y _ 0 5 0 0 0 1 2 5
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
CLI R 2 ;
SSYNC;
# endif
[ p0 ] = R 0 ;
SSYNC;
2007-07-25 11:19:14 +08:00
# if A N O M A L Y _ 0 5 0 0 0 1 2 5
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
STI R 2 ;
# endif
2007-05-21 18:09:27 +08:00
/ * Initialise U A R T - w h e n b o o t i n g f r o m u - b o o t , t h e U A R T i s n o t d i s a b l e d
* so i f w e d o n t i n i t a l i z e h e r e , o u r s e r i a l c o n s o l e g e t s h o s e d * /
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
p0 . h = h i ( U A R T _ L C R ) ;
p0 . l = l o ( U A R T _ L C R ) ;
r0 = 0 x0 ( Z ) ;
w[ p0 ] = r0 . L ; /* To enable DLL writes */
ssync;
p0 . h = h i ( U A R T _ D L L ) ;
p0 . l = l o ( U A R T _ D L L ) ;
r0 = 0 x0 ( Z ) ;
w[ p0 ] = r0 . L ;
ssync;
p0 . h = h i ( U A R T _ D L H ) ;
p0 . l = l o ( U A R T _ D L H ) ;
r0 = 0 x00 ( Z ) ;
w[ p0 ] = r0 . L ;
ssync;
p0 . h = h i ( U A R T _ G C T L ) ;
p0 . l = l o ( U A R T _ G C T L ) ;
r0 = 0 x0 ( Z ) ;
w[ p0 ] = r0 . L ; /* To enable UART clock */
ssync;
/* Initialize stack pointer */
sp. l = l o ( I N I T I A L _ S T A C K ) ;
sp. h = h i ( I N I T I A L _ S T A C K ) ;
fp = s p ;
usp = s p ;
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
call _ b f53 x _ r e l o c a t e _ l 1 _ m e m ;
# if C O N F I G _ B F I N _ K E R N E L _ C L O C K
call _ s t a r t _ d m a _ c o d e ;
# endif
/* Code for initializing Async memory banks */
p2 . h = h i ( E B I U _ A M B C T L 1 ) ;
p2 . l = l o ( E B I U _ A M B C T L 1 ) ;
r0 . h = h i ( A M B C T L 1 V A L ) ;
r0 . l = l o ( A M B C T L 1 V A L ) ;
[ p2 ] = r0 ;
ssync;
p2 . h = h i ( E B I U _ A M B C T L 0 ) ;
p2 . l = l o ( E B I U _ A M B C T L 0 ) ;
r0 . h = h i ( A M B C T L 0 V A L ) ;
r0 . l = l o ( A M B C T L 0 V A L ) ;
[ p2 ] = r0 ;
ssync;
p2 . h = h i ( E B I U _ A M G C T L ) ;
p2 . l = l o ( E B I U _ A M G C T L ) ;
r0 = A M G C T L V A L ;
w[ p2 ] = r0 ;
ssync;
/ * This s e c t i o n k e e p s t h e p r o c e s s o r i n s u p e r v i s o r m o d e
* during k e r n e l b o o t . S w i t c h e s t o u s e r m o d e a t e n d o f b o o t .
* See p a g e 3 - 9 o f H a r d w a r e R e f e r e n c e m a n u a l f o r d o c u m e n t a t i o n .
* /
/* EVT15 = _real_start */
p0 . l = l o ( E V T 1 5 ) ;
p0 . h = h i ( E V T 1 5 ) ;
p1 . l = _ r e a l _ s t a r t ;
p1 . h = _ r e a l _ s t a r t ;
[ p0 ] = p1 ;
csync;
p0 . l = l o ( I M A S K ) ;
p0 . h = h i ( I M A S K ) ;
p1 . l = I M A S K _ I V G 1 5 ;
p1 . h = 0 x0 ;
[ p0 ] = p1 ;
csync;
raise 1 5 ;
p0 . l = . L W A I T _ H E R E ;
p0 . h = . L W A I T _ H E R E ;
reti = p0 ;
2007-07-25 11:19:14 +08:00
# if A N O M A L Y _ 0 5 0 0 0 2 8 1
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
nop; nop; nop;
# endif
rti;
.LWAIT_HERE :
jump . L W A I T _ H E R E ;
2007-06-11 15:31:30 +08:00
ENDPROC( _ _ s t a r t )
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
ENTRY( _ r e a l _ s t a r t )
[ - - sp ] = r e t i ;
p0 . l = l o ( W D O G _ C T L ) ;
p0 . h = h i ( W D O G _ C T L ) ;
r0 = 0 x A D 6 ( z ) ;
w[ p0 ] = r0 ; /* watchdog off for now */
ssync;
/ * Code u p d a t e f o r B S S s i z e = = 0
* Zero o u t t h e b s s r e g i o n .
* /
p1 . l = _ _ _ b s s _ s t a r t ;
p1 . h = _ _ _ b s s _ s t a r t ;
p2 . l = _ _ _ b s s _ s t o p ;
p2 . h = _ _ _ b s s _ s t o p ;
r0 = 0 ;
p2 - = p1 ;
lsetup ( . L _ c l e a r _ b s s , . L _ c l e a r _ b s s ) l c0 = p2 ;
.L_clear_bss :
B[ p1 + + ] = r0 ;
/ * In c a s e t h e r e i s a N U L L p o i n t e r r e f e r e n c e
* Zero o u t r e g i o n b e f o r e s t e x t
* /
p1 . l = 0 x0 ;
p1 . h = 0 x0 ;
r0 . l = _ _ s t e x t ;
r0 . h = _ _ s t e x t ;
r0 = r0 > > 1 ;
p2 = r0 ;
r0 = 0 ;
lsetup ( . L _ c l e a r _ z e r o , . L _ c l e a r _ z e r o ) l c0 = p2 ;
.L_clear_zero :
W[ p1 + + ] = r0 ;
2007-06-11 15:31:30 +08:00
/* pass the uboot arguments to the global value command line */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
R0 = R 7 ;
call _ c m d l i n e _ i n i t ;
p1 . l = _ _ r a m b a s e ;
p1 . h = _ _ r a m b a s e ;
r0 . l = _ _ s d a t a ;
r0 . h = _ _ s d a t a ;
[ p1 ] = r0 ;
p1 . l = _ _ r a m s t a r t ;
p1 . h = _ _ r a m s t a r t ;
p3 . l = _ _ _ b s s _ s t o p ;
p3 . h = _ _ _ b s s _ s t o p ;
r1 = p3 ;
[ p1 ] = r1 ;
/ *
2007-06-11 15:31:30 +08:00
* load t h e c u r r e n t t h r e a d p o i n t e r a n d s t a c k
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
* /
r1 . l = _ i n i t _ t h r e a d _ u n i o n ;
r1 . h = _ i n i t _ t h r e a d _ u n i o n ;
r2 . l = 0 x20 0 0 ;
r2 . h = 0 x00 0 0 ;
r1 = r1 + r2 ;
sp = r1 ;
usp = s p ;
fp = s p ;
2007-06-11 15:31:30 +08:00
jump. l _ s t a r t _ k e r n e l ;
ENDPROC( _ r e a l _ s t a r t )
_ _ FINIT
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
.section .l1 .text
# if C O N F I G _ B F I N _ K E R N E L _ C L O C K
ENTRY( _ s t a r t _ d m a _ c o d e )
p0 . h = h i ( S I C _ I W R ) ;
p0 . l = l o ( S I C _ I W R ) ;
r0 . l = 0 x1 ;
r0 . h = 0 x0 ;
[ p0 ] = r0 ;
SSYNC;
/ *
* Set P L L _ C T L
* - [ 14 : 0 9 ] = MSEL[ 5 : 0 ] : C L K I N / V C O m u l t i p l i c a t i o n f a c t o r s
* - [ 8 ] = BYPASS : B Y P A S S t h e P L L , r u n C L K I N i n t o C C L K / S C L K
* - [ 7 ] = output d e l a y ( a d d 2 0 0 p s o f d e l a y t o m e m s i g n a l s )
* - [ 6 ] = input d e l a y ( a d d 2 0 0 p s o f i n p u t d e l a y t o m e m s i g n a l s )
* - [ 5 ] = PDWN : 1 =All C l o c k s o f f
* - [ 3 ] = STOPCK : 1 =Core C l o c k o f f
* - [ 1 ] = PLL_ O F F : 1 =Disable P o w e r t o P L L
* - [ 0 ] = DF : 1 =Pass C L K I N / 2 t o P L L / 0 =Pass C L K I N t o P L L
* all o t h e r b i t s s e t t o z e r o
* /
p0 . h = h i ( P L L _ L O C K C N T ) ;
p0 . l = l o ( P L L _ L O C K C N T ) ;
r0 = 0 x30 0 ( Z ) ;
w[ p0 ] = r0 . l ;
ssync;
P2 . H = h i ( E B I U _ S D G C T L ) ;
P2 . L = l o ( E B I U _ S D G C T L ) ;
R0 = [ P 2 ] ;
BITSET ( R 0 , 2 4 ) ;
[ P2 ] = R 0 ;
SSYNC;
r0 = C O N F I G _ V C O _ M U L T & 6 3 ; /* Load the VCO multiplier */
r0 = r0 < < 9 ; /* Shift it over, */
r1 = C L K I N _ H A L F ; /* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0 ;
r1 = P L L _ B Y P A S S ; /* Bypass the PLL? */
r1 = r1 < < 8 ; /* Shift it over */
r0 = r1 | r0 ; /* add them all together */
p0 . h = h i ( P L L _ C T L ) ;
p0 . l = l o ( P L L _ C T L ) ; /* Load the address */
cli r2 ; /* Disable interrupts */
ssync;
w[ p0 ] = r0 . l ; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2 ; /* Enable interrupts */
.Lcheck_again :
p0 . h = h i ( P L L _ S T A T ) ;
p0 . l = l o ( P L L _ S T A T ) ;
R0 = W [ P 0 ] ( Z ) ;
CC = B I T T S T ( R 0 ,5 ) ;
if ! C C j u m p . L c h e c k _ a g a i n ;
/* Configure SCLK & CCLK Dividers */
r0 = ( C O N F I G _ C C L K _ A C T _ D I V | C O N F I G _ S C L K _ D I V ) ;
p0 . h = h i ( P L L _ D I V ) ;
p0 . l = l o ( P L L _ D I V ) ;
w[ p0 ] = r0 . l ;
ssync;
p0 . l = l o ( E B I U _ S D R R C ) ;
p0 . h = h i ( E B I U _ S D R R C ) ;
r0 = m e m _ S D R R C ;
w[ p0 ] = r0 . l ;
ssync;
p0 . l = ( E B I U _ S D B C T L & 0 x F F F F ) ;
p0 . h = ( E B I U _ S D B C T L > > 1 6 ) ; /* SDRAM Memory Bank Control Register */
r0 = m e m _ S D B C T L ;
w[ p0 ] = r0 . l ;
ssync;
P2 . H = h i ( E B I U _ S D G C T L ) ;
P2 . L = l o ( E B I U _ S D G C T L ) ;
R0 = [ P 2 ] ;
BITCLR ( R 0 , 2 4 ) ;
p0 . h = h i ( E B I U _ S D S T A T ) ;
p0 . l = l o ( E B I U _ S D S T A T ) ;
r2 . l = w [ p0 ] ;
cc = b i t t s t ( r2 ,3 ) ;
if ! c c j u m p . L s k i p ;
NOP;
BITSET ( R 0 , 2 3 ) ;
.Lskip :
[ P2 ] = R 0 ;
SSYNC;
R0 . L = l o ( m e m _ S D G C T L ) ;
R0 . H = h i ( m e m _ S D G C T L ) ;
R1 = [ p2 ] ;
R1 = R 1 | R 0 ;
[ P2 ] = R 1 ;
SSYNC;
p0 . h = h i ( S I C _ I W R ) ;
p0 . l = l o ( S I C _ I W R ) ;
2007-06-11 15:31:30 +08:00
r0 . l = l o ( I W R _ E N A B L E _ A L L ) ;
r0 . h = h i ( I W R _ E N A B L E _ A L L ) ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
[ p0 ] = r0 ;
SSYNC;
RTS;
2007-06-11 15:31:30 +08:00
ENDPROC( _ s t a r t _ d m a _ c o d e )
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
# endif / * C O N F I G _ B F I N _ K E R N E L _ C L O C K * /
ENTRY( _ b f i n _ r e s e t )
/* No more interrupts to be handled*/
CLI R 6 ;
SSYNC;
# if d e f i n e d ( C O N F I G _ B F I N _ S H A R E D _ F L A S H _ E N E T )
p0 . h = h i ( F I O _ I N E N ) ;
p0 . l = l o ( F I O _ I N E N ) ;
r0 . l = ~ ( 1 < < C O N F I G _ E N E T _ F L A S H _ P I N ) ;
w[ p0 ] = r0 . l ;
p0 . h = h i ( F I O _ D I R ) ;
p0 . l = l o ( F I O _ D I R ) ;
r0 . l = ( 1 < < C O N F I G _ E N E T _ F L A S H _ P I N ) ;
w[ p0 ] = r0 . l ;
p0 . h = h i ( F I O _ F L A G _ C ) ;
p0 . l = l o ( F I O _ F L A G _ C ) ;
r0 . l = ( 1 < < C O N F I G _ E N E T _ F L A S H _ P I N ) ;
w[ p0 ] = r0 . l ;
# endif
/* Clear the IMASK register */
p0 . h = h i ( I M A S K ) ;
p0 . l = l o ( I M A S K ) ;
r0 = 0 x0 ;
[ p0 ] = r0 ;
/* Clear the ILAT register */
p0 . h = h i ( I L A T ) ;
p0 . l = l o ( I L A T ) ;
r0 = [ p0 ] ;
[ p0 ] = r0 ;
SSYNC;
2007-05-21 18:09:26 +08:00
/* make sure SYSCR is set to use BMODE */
P0 . h = h i ( S Y S C R ) ;
P0 . l = l o ( S Y S C R ) ;
R0 . l = 0 x0 ;
W[ P 0 ] = R 0 . l ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
SSYNC;
2007-05-21 18:09:26 +08:00
/* issue a system soft reset */
P1 . h = h i ( S W R S T ) ;
P1 . l = l o ( S W R S T ) ;
R1 . l = 0 x00 0 7 ;
W[ P 1 ] = R 1 ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
SSYNC;
2007-05-21 18:09:26 +08:00
/* clear system soft reset */
R0 . l = 0 x00 0 0 ;
W[ P 0 ] = R 0 ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
SSYNC;
2007-05-21 18:09:26 +08:00
/* issue core reset */
raise 1 ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
RTS;
2007-05-21 18:09:26 +08:00
ENDPROC( _ b f i n _ r e s e t )
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 14:50:22 -07:00
# if C O N F I G _ D E B U G _ K E R N E L _ S T A R T
debug_kernel_start_trap :
/* Set up a temp stack in L1 - SDRAM might not be working */
P0 . L = l o ( L 1 _ D A T A _ A _ S T A R T + 0 x10 0 ) ;
P0 . H = h i ( L 1 _ D A T A _ A _ S T A R T + 0 x10 0 ) ;
SP = P 0 ;
/* Make sure the Clocks are the way I think they should be */
r0 = C O N F I G _ V C O _ M U L T & 6 3 ; /* Load the VCO multiplier */
r0 = r0 < < 9 ; /* Shift it over, */
r1 = C L K I N _ H A L F ; /* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0 ;
r1 = P L L _ B Y P A S S ; /* Bypass the PLL? */
r1 = r1 < < 8 ; /* Shift it over */
r0 = r1 | r0 ; /* add them all together */
p0 . h = h i ( P L L _ C T L ) ;
p0 . l = l o ( P L L _ C T L ) ; /* Load the address */
cli r2 ; /* Disable interrupts */
ssync;
w[ p0 ] = r0 . l ; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2 ; /* Enable interrupts */
.Lcheck_again1 :
p0 . h = h i ( P L L _ S T A T ) ;
p0 . l = l o ( P L L _ S T A T ) ;
R0 = W [ P 0 ] ( Z ) ;
CC = B I T T S T ( R 0 ,5 ) ;
if ! C C j u m p . L c h e c k _ a g a i n 1 ;
/* Configure SCLK & CCLK Dividers */
r0 = ( C O N F I G _ C C L K _ A C T _ D I V | C O N F I G _ S C L K _ D I V ) ;
p0 . h = h i ( P L L _ D I V ) ;
p0 . l = l o ( P L L _ D I V ) ;
w[ p0 ] = r0 . l ;
ssync;
/* Make sure UART is enabled - you can never be sure */
/ *
* Setup f o r c o n s o l e . A r g u m e n t c o m e s f r o m t h e m e n u c o n f i g
* /
# ifdef C O N F I G _ B A U D _ 9 6 0 0
# define C O N S O L E _ B A U D _ R A T E 9 6 0 0
# elif C O N F I G _ B A U D _ 1 9 2 0 0
# define C O N S O L E _ B A U D _ R A T E 1 9 2 0 0
# elif C O N F I G _ B A U D _ 3 8 4 0 0
# define C O N S O L E _ B A U D _ R A T E 3 8 4 0 0
# elif C O N F I G _ B A U D _ 5 7 6 0 0
# define C O N S O L E _ B A U D _ R A T E 5 7 6 0 0
# elif C O N F I G _ B A U D _ 1 1 5 2 0 0
# define C O N S O L E _ B A U D _ R A T E 1 1 5 2 0 0
# endif
p0 . h = h i ( U A R T _ G C T L ) ;
p0 . l = l o ( U A R T _ G C T L ) ;
r0 = 0 x00 ( Z ) ;
w[ p0 ] = r0 . L ; /* To Turn off UART clocks */
ssync;
p0 . h = h i ( U A R T _ L C R ) ;
p0 . l = l o ( U A R T _ L C R ) ;
r0 = 0 x83 ( Z ) ;
w[ p0 ] = r0 . L ; /* To enable DLL writes */
ssync;
R1 = ( ( ( C O N F I G _ C L K I N _ H Z * C O N F I G _ V C O _ M U L T ) / C O N F I G _ S C L K _ D I V ) / ( C O N S O L E _ B A U D _ R A T E * 1 6 ) ) ;
p0 . h = h i ( U A R T _ D L L ) ;
p0 . l = l o ( U A R T _ D L L ) ;
r0 = 0 x F F ( Z ) ;
r0 = R 1 & R 0 ;
w[ p0 ] = r0 . L ;
ssync;
p0 . h = h i ( U A R T _ D L H ) ;
p0 . l = l o ( U A R T _ D L H ) ;
r1 > > = 8 ;
w[ p0 ] = r1 . L ;
ssync;
p0 . h = h i ( U A R T _ G C T L ) ;
p0 . l = l o ( U A R T _ G C T L ) ;
r0 = 0 x0 ( Z ) ;
w[ p0 ] = r0 . L ; /* To enable UART clock */
ssync;
p0 . h = h i ( U A R T _ L C R ) ;
p0 . l = l o ( U A R T _ L C R ) ;
r0 = 0 x03 ( Z ) ;
w[ p0 ] = r0 . L ; /* To Turn on UART */
ssync;
p0 . h = h i ( U A R T _ G C T L ) ;
p0 . l = l o ( U A R T _ G C T L ) ;
r0 = 0 x01 ( Z ) ;
w[ p0 ] = r0 . L ; /* To Turn on UART Clocks */
ssync;
P0 . h = h i ( U A R T _ T H R ) ;
P0 . l = l o ( U A R T _ T H R ) ;
P1 . h = h i ( U A R T _ L S R ) ;
P1 . l = l o ( U A R T _ L S R ) ;
R0 . L = ' K ' ;
call . L w a i t _ c h a r ;
R0 . L = ' e ' ;
call . L w a i t _ c h a r ;
R0 . L = ' r ' ;
call . L w a i t _ c h a r ;
R0 . L = ' n '
call . L w a i t _ c h a r ;
R0 . L = ' e '
call . L w a i t _ c h a r ;
R0 . L = ' l ' ;
call . L w a i t _ c h a r ;
R0 . L = ' ' ;
call . L w a i t _ c h a r ;
R0 . L = ' c ' ;
call . L w a i t _ c h a r ;
R0 . L = ' r ' ;
call . L w a i t _ c h a r ;
R0 . L = ' a ' ;
call . L w a i t _ c h a r ;
R0 . L = ' s ' ;
call . L w a i t _ c h a r ;
R0 . L = ' h ' ;
call . L w a i t _ c h a r ;
R0 . L = ' \ r ' ;
call . L w a i t _ c h a r ;
R0 . L = ' \ n ' ;
call . L w a i t _ c h a r ;
R0 . L = ' S ' ;
call . L w a i t _ c h a r ;
R0 . L = ' E ' ;
call . L w a i t _ c h a r ;
R0 . L = ' Q '
call . L w a i t _ c h a r ;
R0 . L = ' S '
call . L w a i t _ c h a r ;
R0 . L = ' T ' ;
call . L w a i t _ c h a r ;
R0 . L = ' A ' ;
call . L w a i t _ c h a r ;
R0 . L = ' T ' ;
call . L w a i t _ c h a r ;
R0 . L = ' = ' ;
call . L w a i t _ c h a r ;
R2 = S E Q S T A T ;
call . L d u m p _ r e g ;
R0 . L = ' ' ;
call . L w a i t _ c h a r ;
R0 . L = ' R ' ;
call . L w a i t _ c h a r ;
R0 . L = ' E '
call . L w a i t _ c h a r ;
R0 . L = ' T '
call . L w a i t _ c h a r ;
R0 . L = ' X ' ;
call . L w a i t _ c h a r ;
R0 . L = ' = ' ;
call . L w a i t _ c h a r ;
R2 = R E T X ;
call . L d u m p _ r e g ;
R0 . L = ' \ r ' ;
call . L w a i t _ c h a r ;
R0 . L = ' \ n ' ;
call . L w a i t _ c h a r ;
.Ldebug_kernel_start_trap_done :
JUMP . L d e b u g _ k e r n e l _ s t a r t _ t r a p _ d o n e ;
.Ldump_reg :
R3 = 3 2 ;
R4 = 0 x0 F ;
R5 = ' : ' ; /* one past 9 */
.Ldump_reg2 :
R0 = R 2 ;
R3 + = - 4 ;
R0 > > > = R 3 ;
R0 = R 0 & R 4 ;
R0 + = 0 x30 ;
CC = R 0 < = R 5 ;
if C C J U M P . L d u m p _ r e g 1 ;
R0 + = 7 ;
.Ldump_reg1 :
R1 . l = W [ P 1 ] ;
CC = B I T T S T ( R 1 , 5 ) ;
if ! C C J U M P . L d u m p _ r e g 1 ;
W[ P 0 ] = r0 ;
CC = R 3 = = 0 ;
if ! C C J U M P . L d u m p _ r e g 2
RTS;
.Lwait_char :
R1 . l = W [ P 1 ] ;
CC = B I T T S T ( R 1 , 5 ) ;
if ! C C J U M P . L w a i t _ c h a r ;
W[ P 0 ] = r0 ;
RTS;
# endif / * C O N F I G _ D E B U G _ K E R N E L _ S T A R T * /
.data
/ *
* Set u p t h e u s a b l e o f R A M s t u f f . S i z e o f R A M i s d e t e r m i n e d t h e n
* an i n i t i a l s t a c k s e t u p a t t h e e n d .
* /
.align 4
__rambase :
.long 0
__ramstart :
.long 0
__ramend :
.long 0
