184 lines
4.2 KiB
C
184 lines
4.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* rt1017-sdca-sdw.h -- RT1017 SDCA ALSA SoC audio driver header
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*
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* Copyright(c) 2023 Realtek Semiconductor Corp.
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*/
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#ifndef __RT1017_SDW_H__
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#define __RT1017_SDW_H__
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#include <linux/regmap.h>
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#include <linux/soundwire/sdw.h>
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#include <linux/soundwire/sdw_type.h>
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#include <linux/soundwire/sdw_registers.h>
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#include <sound/soc.h>
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/* RT1017 SDCA Control - function number */
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#define FUNC_NUM_SMART_AMP 0x04
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/* RT1017 SDCA entity */
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#define RT1017_SDCA_ENT_PDE23 0x31
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#define RT1017_SDCA_ENT_PDE22 0x33
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#define RT1017_SDCA_ENT_CS21 0x21
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#define RT1017_SDCA_ENT_SAPU29 0x29
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#define RT1017_SDCA_ENT_XU22 0x22
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#define RT1017_SDCA_ENT_FU 0x03
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#define RT1017_SDCA_ENT_UDMPU21 0x02
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/* RT1017 SDCA control */
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#define RT1017_SDCA_CTL_FS_INDEX 0x10
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#define RT1017_SDCA_CTL_REQ_POWER_STATE 0x01
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#define RT1017_SDCA_CTL_PROT_STAT 0x11
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#define RT1017_SDCA_CTL_BYPASS 0x01
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#define RT1017_SDCA_CTL_FU_MUTE 0x01
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#define RT1017_SDCA_CTL_FU_VOLUME 0x02
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#define RT1017_SDCA_CTL_UDMPU_CLUSTER 0x10
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#define RT1017_CLASSD_INT_1 0xd300
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#define RT1017_PWM_TRIM_1 0xd370
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#define RT1017_PWM_FREQ_CTL_SRC_SEL_MASK (0x3 << 2)
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#define RT1017_PWM_FREQ_CTL_SRC_SEL_EFUSE (0x2 << 2)
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#define RT1017_PWM_FREQ_CTL_SRC_SEL_REG (0x0 << 2)
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enum {
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RT1017_SDCA_RATE_44100HZ = 0x8,
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RT1017_SDCA_RATE_48000HZ = 0x9,
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RT1017_SDCA_RATE_96000HZ = 0xb,
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RT1017_SDCA_RATE_192000HZ = 0xd,
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};
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struct rt1017_sdca_priv {
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struct snd_soc_component *component;
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struct regmap *regmap;
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struct sdw_slave *sdw_slave;
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struct sdw_bus_params params;
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bool hw_init;
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bool first_hw_init;
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};
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static const struct reg_default rt1017_sdca_reg_defaults[] = {
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{ 0x3206, 0x00 },
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{ 0xc001, 0x43 },
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{ 0xc030, 0x54 },
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{ 0xc104, 0x8a },
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{ 0xc10b, 0x2f },
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{ 0xc10c, 0x2f },
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{ 0xc110, 0x49 },
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{ 0xc112, 0x10 },
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{ 0xc300, 0xff },
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{ 0xc301, 0xdd },
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{ 0xc318, 0x40 },
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{ 0xc325, 0x00 },
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{ 0xc326, 0x00 },
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{ 0xc327, 0x00 },
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{ 0xc328, 0x02 },
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{ 0xc331, 0xb2 },
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{ 0xc340, 0x02 },
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{ 0xc350, 0x21 },
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{ 0xc500, 0x00 },
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{ 0xc502, 0x00 },
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{ 0xc504, 0x3f },
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{ 0xc507, 0x1f },
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{ 0xc509, 0x1f },
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{ 0xc510, 0x40 },
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{ 0xc512, 0x00 },
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{ 0xc518, 0x02 },
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{ 0xc51b, 0x7f },
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{ 0xc51d, 0x0f },
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{ 0xc520, 0x00 },
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{ 0xc540, 0x80 },
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{ 0xc541, 0x00 },
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{ 0xc542, 0x0a },
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{ 0xc550, 0x80 },
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{ 0xc551, 0x0f },
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{ 0xc552, 0xff },
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{ 0xc600, 0x10 },
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{ 0xc602, 0x83 },
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{ 0xc612, 0x40 },
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{ 0xc622, 0x40 },
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{ 0xc632, 0x40 },
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{ 0xc642, 0x40 },
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{ 0xc651, 0x00 },
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{ 0xca00, 0xc1 },
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{ 0xca09, 0x00 },
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{ 0xca0a, 0x51 },
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{ 0xca0b, 0xeb },
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{ 0xca0c, 0x85 },
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{ 0xca0e, 0x00 },
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{ 0xca0f, 0x10 },
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{ 0xca10, 0x62 },
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{ 0xca11, 0x4d },
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{ 0xca16, 0x0f },
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{ 0xca17, 0x00 },
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{ 0xcb00, 0x10 },
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{ 0xcc00, 0x10 },
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{ 0xcc02, 0x0b },
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{ 0xd017, 0x09 },
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{ 0xd01a, 0x00 },
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{ 0xd01b, 0x00 },
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{ 0xd01c, 0x00 },
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{ 0xd101, 0xa0 },
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{ 0xd20c, 0x14 },
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{ 0xd300, 0x0f },
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{ 0xd370, 0x18 },
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{ 0xd500, 0x00 },
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{ 0xd545, 0x0b },
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{ 0xd546, 0xf9 },
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{ 0xd547, 0xb2 },
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{ 0xd548, 0xa9 },
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{ 0xd5a5, 0x00 },
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{ 0xd5a6, 0x00 },
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{ 0xd5a7, 0x00 },
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{ 0xd5a8, 0x00 },
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{ 0xd5aa, 0x00 },
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{ 0xd5ab, 0x00 },
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{ 0xd5ac, 0x00 },
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{ 0xd5ad, 0x00 },
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{ 0xda04, 0x03 },
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{ 0xda05, 0x33 },
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{ 0xda06, 0x33 },
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{ 0xda07, 0x33 },
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{ 0xda09, 0x5d },
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{ 0xda0a, 0xc0 },
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{ 0xda0c, 0x00 },
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{ 0xda0d, 0x01 },
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{ 0xda0e, 0x5d },
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{ 0xda0f, 0x86 },
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{ 0xda11, 0x20 },
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{ 0xda12, 0x00 },
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{ 0xda13, 0x00 },
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{ 0xda14, 0x00 },
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{ 0xda16, 0x7f },
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{ 0xda17, 0xff },
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{ 0xda18, 0xff },
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{ 0xda19, 0xff },
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{ 0xdab6, 0x00 },
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{ 0xdab7, 0x01 },
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{ 0xdab8, 0x00 },
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{ 0xdab9, 0x01 },
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{ 0xdaba, 0x00 },
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{ 0xdabb, 0x01 },
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{ 0xdb09, 0x0f },
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{ 0xdb0a, 0xff },
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{ 0xdb14, 0x00 },
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{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_UDMPU21,
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RT1017_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 },
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{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_FU,
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RT1017_SDCA_CTL_FU_MUTE, 0x01), 0x01 },
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{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_XU22,
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RT1017_SDCA_CTL_BYPASS, 0), 0x01 },
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{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_CS21,
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RT1017_SDCA_CTL_FS_INDEX, 0), 0x09 },
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{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE23,
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RT1017_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
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{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE22,
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RT1017_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
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};
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#endif /* __RT1017_SDW_H__ */
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