linux/drivers/clk/meson/g12a.h

/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2016 Amlogic, Inc.
 * Author: Michael Turquette <mturquette@baylibre.com>
 *
 * Copyright (c) 2018 Amlogic, inc.
 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
 * Author: Jian Hu <jian.hu@amlogic.com>
 *
 */
#ifndef __G12A_H
#define __G12A_H

/*
 * Clock controller register offsets
 *
 * Register offsets from the data sheet must be multiplied by 4 before
 * adding them to the base address to get the right value.
 */
#define HHI_MIPI_CNTL0			0x000
#define HHI_MIPI_CNTL1			0x004
#define HHI_MIPI_CNTL2			0x008
#define HHI_MIPI_STS			0x00C
#define HHI_GP0_PLL_CNTL0		0x040
#define HHI_GP0_PLL_CNTL1		0x044
#define HHI_GP0_PLL_CNTL2		0x048
#define HHI_GP0_PLL_CNTL3		0x04C
#define HHI_GP0_PLL_CNTL4		0x050
#define HHI_GP0_PLL_CNTL5		0x054
#define HHI_GP0_PLL_CNTL6		0x058
#define HHI_GP0_PLL_STS			0x05C
#define HHI_GP1_PLL_CNTL0		0x060
#define HHI_GP1_PLL_CNTL1		0x064
#define HHI_GP1_PLL_CNTL2		0x068
#define HHI_GP1_PLL_CNTL3		0x06C
#define HHI_GP1_PLL_CNTL4		0x070
#define HHI_GP1_PLL_CNTL5		0x074
#define HHI_GP1_PLL_CNTL6		0x078
#define HHI_GP1_PLL_STS			0x07C
#define HHI_PCIE_PLL_CNTL0		0x098
#define HHI_PCIE_PLL_CNTL1		0x09C
#define HHI_PCIE_PLL_CNTL2		0x0A0
#define HHI_PCIE_PLL_CNTL3		0x0A4
#define HHI_PCIE_PLL_CNTL4		0x0A8
#define HHI_PCIE_PLL_CNTL5		0x0AC
#define HHI_PCIE_PLL_STS		0x0B8
#define HHI_HIFI_PLL_CNTL0		0x0D8
#define HHI_HIFI_PLL_CNTL1		0x0DC
#define HHI_HIFI_PLL_CNTL2		0x0E0
#define HHI_HIFI_PLL_CNTL3		0x0E4
#define HHI_HIFI_PLL_CNTL4		0x0E8
#define HHI_HIFI_PLL_CNTL5		0x0EC
#define HHI_HIFI_PLL_CNTL6		0x0F0
#define HHI_VIID_CLK_DIV		0x128
#define HHI_VIID_CLK_CNTL		0x12C
#define HHI_GCLK_MPEG0			0x140
#define HHI_GCLK_MPEG1			0x144
#define HHI_GCLK_MPEG2			0x148
#define HHI_GCLK_OTHER			0x150
#define HHI_GCLK_OTHER2			0x154
#define HHI_SYS_CPU_CLK_CNTL1		0x15c
#define HHI_VID_CLK_DIV			0x164
#define HHI_MPEG_CLK_CNTL		0x174
#define HHI_AUD_CLK_CNTL		0x178
#define HHI_VID_CLK_CNTL		0x17c
#define HHI_TS_CLK_CNTL			0x190
#define HHI_VID_CLK_CNTL2		0x194
#define HHI_SYS_CPU_CLK_CNTL0		0x19c
#define HHI_VID_PLL_CLK_DIV		0x1A0
#define HHI_MALI_CLK_CNTL		0x1b0
#define HHI_VPU_CLKC_CNTL		0x1b4
#define HHI_VPU_CLK_CNTL		0x1bC
#define HHI_NNA_CLK_CNTL		0x1C8
#define HHI_HDMI_CLK_CNTL		0x1CC
#define HHI_VDEC_CLK_CNTL		0x1E0
#define HHI_VDEC2_CLK_CNTL		0x1E4
#define HHI_VDEC3_CLK_CNTL		0x1E8
#define HHI_VDEC4_CLK_CNTL		0x1EC
#define HHI_HDCP22_CLK_CNTL		0x1F0
#define HHI_VAPBCLK_CNTL		0x1F4
#define HHI_SYS_CPUB_CLK_CNTL1		0x200
#define HHI_SYS_CPUB_CLK_CNTL		0x208
#define HHI_VPU_CLKB_CNTL		0x20C
#define HHI_SYS_CPU_CLK_CNTL2		0x210
#define HHI_SYS_CPU_CLK_CNTL3		0x214
#define HHI_SYS_CPU_CLK_CNTL4		0x218
#define HHI_SYS_CPU_CLK_CNTL5		0x21c
#define HHI_SYS_CPU_CLK_CNTL6		0x220
#define HHI_GEN_CLK_CNTL		0x228
#define HHI_VDIN_MEAS_CLK_CNTL		0x250
#define HHI_MIPIDSI_PHY_CLK_CNTL	0x254
#define HHI_NAND_CLK_CNTL		0x25C
#define HHI_SD_EMMC_CLK_CNTL		0x264
#define HHI_MPLL_CNTL0			0x278
#define HHI_MPLL_CNTL1			0x27C
#define HHI_MPLL_CNTL2			0x280
#define HHI_MPLL_CNTL3			0x284
#define HHI_MPLL_CNTL4			0x288
#define HHI_MPLL_CNTL5			0x28c
#define HHI_MPLL_CNTL6			0x290
#define HHI_MPLL_CNTL7			0x294
#define HHI_MPLL_CNTL8			0x298
#define HHI_FIX_PLL_CNTL0		0x2A0
#define HHI_FIX_PLL_CNTL1		0x2A4
#define HHI_FIX_PLL_CNTL3		0x2AC
#define HHI_SYS_PLL_CNTL0		0x2f4
#define HHI_SYS_PLL_CNTL1		0x2f8
#define HHI_SYS_PLL_CNTL2		0x2fc
#define HHI_SYS_PLL_CNTL3		0x300
#define HHI_SYS_PLL_CNTL4		0x304
#define HHI_SYS_PLL_CNTL5		0x308
#define HHI_SYS_PLL_CNTL6		0x30c
#define HHI_HDMI_PLL_CNTL0		0x320
#define HHI_HDMI_PLL_CNTL1		0x324
#define HHI_HDMI_PLL_CNTL2		0x328
#define HHI_HDMI_PLL_CNTL3		0x32c
#define HHI_HDMI_PLL_CNTL4		0x330
#define HHI_HDMI_PLL_CNTL5		0x334
#define HHI_HDMI_PLL_CNTL6		0x338
#define HHI_SPICC_CLK_CNTL		0x3dc
#define HHI_SYS1_PLL_CNTL0		0x380
#define HHI_SYS1_PLL_CNTL1		0x384
#define HHI_SYS1_PLL_CNTL2		0x388
#define HHI_SYS1_PLL_CNTL3		0x38c
#define HHI_SYS1_PLL_CNTL4		0x390
#define HHI_SYS1_PLL_CNTL5		0x394
#define HHI_SYS1_PLL_CNTL6		0x398

#endif /* __G12A_H */
clk: meson: g12a: add peripheral clock controller Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com 2019-02-01 17:53:44 +03:00			`/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */`
			`/*`
			`* Copyright (c) 2016 Amlogic, Inc.`
			`* Author: Michael Turquette <mturquette@baylibre.com>`
			`*`
			`* Copyright (c) 2018 Amlogic, inc.`
			`* Author: Qiufang Dai <qiufang.dai@amlogic.com>`
			`* Author: Jian Hu <jian.hu@amlogic.com>`
			`*`
			`*/`
			`#ifndef __G12A_H`
			`#define __G12A_H`

			`/*`
			`* Clock controller register offsets`
			`*`
			`* Register offsets from the data sheet must be multiplied by 4 before`
			`* adding them to the base address to get the right value.`
			`*/`
			`#define HHI_MIPI_CNTL0 0x000`
			`#define HHI_MIPI_CNTL1 0x004`
			`#define HHI_MIPI_CNTL2 0x008`
			`#define HHI_MIPI_STS 0x00C`
			`#define HHI_GP0_PLL_CNTL0 0x040`
			`#define HHI_GP0_PLL_CNTL1 0x044`
			`#define HHI_GP0_PLL_CNTL2 0x048`
			`#define HHI_GP0_PLL_CNTL3 0x04C`
			`#define HHI_GP0_PLL_CNTL4 0x050`
			`#define HHI_GP0_PLL_CNTL5 0x054`
			`#define HHI_GP0_PLL_CNTL6 0x058`
			`#define HHI_GP0_PLL_STS 0x05C`
clk: meson: g12a: add support for SM1 GP1 PLL Add the new GP1 PLL for the Amlogic SM1 SoC, used to feed the new DynamIQ Shared Unit of the ARM Cores Complex. This also adds a dedicated set of clock and compatible for SM1. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> 2019-08-26 10:25:36 +03:00			`#define HHI_GP1_PLL_CNTL0 0x060`
			`#define HHI_GP1_PLL_CNTL1 0x064`
			`#define HHI_GP1_PLL_CNTL2 0x068`
			`#define HHI_GP1_PLL_CNTL3 0x06C`
			`#define HHI_GP1_PLL_CNTL4 0x070`
			`#define HHI_GP1_PLL_CNTL5 0x074`
			`#define HHI_GP1_PLL_CNTL6 0x078`
			`#define HHI_GP1_PLL_STS 0x07C`
clk: meson: g12a: add peripheral clock controller Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com 2019-02-01 17:53:44 +03:00			`#define HHI_PCIE_PLL_CNTL0 0x098`
			`#define HHI_PCIE_PLL_CNTL1 0x09C`
			`#define HHI_PCIE_PLL_CNTL2 0x0A0`
			`#define HHI_PCIE_PLL_CNTL3 0x0A4`
			`#define HHI_PCIE_PLL_CNTL4 0x0A8`
			`#define HHI_PCIE_PLL_CNTL5 0x0AC`
			`#define HHI_PCIE_PLL_STS 0x0B8`
			`#define HHI_HIFI_PLL_CNTL0 0x0D8`
			`#define HHI_HIFI_PLL_CNTL1 0x0DC`
			`#define HHI_HIFI_PLL_CNTL2 0x0E0`
			`#define HHI_HIFI_PLL_CNTL3 0x0E4`
			`#define HHI_HIFI_PLL_CNTL4 0x0E8`
			`#define HHI_HIFI_PLL_CNTL5 0x0EC`
			`#define HHI_HIFI_PLL_CNTL6 0x0F0`
			`#define HHI_VIID_CLK_DIV 0x128`
			`#define HHI_VIID_CLK_CNTL 0x12C`
			`#define HHI_GCLK_MPEG0 0x140`
			`#define HHI_GCLK_MPEG1 0x144`
			`#define HHI_GCLK_MPEG2 0x148`
			`#define HHI_GCLK_OTHER 0x150`
			`#define HHI_GCLK_OTHER2 0x154`
clk: meson: g12a: add cpu clocks Add the Amlogic G12A Family CPU Clock tree in read/only for now. The CPU clock can either use the SYS_PLL for > 1GHz frequencies or use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch muxes. Proper DVFS support will come in a second time. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: fixed cpu clocks namings] Link: https://lkml.kernel.org/r/20190304131129.7762-3-narmstrong@baylibre.com 2019-03-04 16:11:29 +03:00			`#define HHI_SYS_CPU_CLK_CNTL1 0x15c`
clk: meson: g12a: add peripheral clock controller Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com 2019-02-01 17:53:44 +03:00			`#define HHI_VID_CLK_DIV 0x164`
			`#define HHI_MPEG_CLK_CNTL 0x174`
			`#define HHI_AUD_CLK_CNTL 0x178`
			`#define HHI_VID_CLK_CNTL 0x17c`
			`#define HHI_TS_CLK_CNTL 0x190`
			`#define HHI_VID_CLK_CNTL2 0x194`
			`#define HHI_SYS_CPU_CLK_CNTL0 0x19c`
			`#define HHI_VID_PLL_CLK_DIV 0x1A0`
			`#define HHI_MALI_CLK_CNTL 0x1b0`
			`#define HHI_VPU_CLKC_CNTL 0x1b4`
			`#define HHI_VPU_CLK_CNTL 0x1bC`
clk: meson: g12a: Add support for NNA CLK source clocks This adds the Neural Network Accelerator source clocks hierarchy, it's 2 simple composite clocks to feed the AXI interface and the Core of the Neural Network Accelerator IP. This IP is only present on the Amlogic SM1 SoCs family. Signed-off-by: Dmitry Shmidt <dimitrysh@google.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200610083012.5024-3-narmstrong@baylibre.com 2020-06-10 11:30:12 +03:00			`#define HHI_NNA_CLK_CNTL 0x1C8`
clk: meson: g12a: add peripheral clock controller Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com 2019-02-01 17:53:44 +03:00			`#define HHI_HDMI_CLK_CNTL 0x1CC`
			`#define HHI_VDEC_CLK_CNTL 0x1E0`
			`#define HHI_VDEC2_CLK_CNTL 0x1E4`
			`#define HHI_VDEC3_CLK_CNTL 0x1E8`
			`#define HHI_VDEC4_CLK_CNTL 0x1EC`
			`#define HHI_HDCP22_CLK_CNTL 0x1F0`
			`#define HHI_VAPBCLK_CNTL 0x1F4`
clk: meson: g12a: Add support for G12B CPUB clocks Update the Meson G12A Clock driver to support the Amlogic G12B SoC. G12B clock driver is very close, the main differences are : - the clock tree is duplicated for the both clusters, and the SYS_PLL are swapped between the clusters - G12B has additional clocks like for CSI an other components Here only the cpu clock tree is handled. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> 2019-05-28 11:07:57 +03:00			`#define HHI_SYS_CPUB_CLK_CNTL1 0x200`
			`#define HHI_SYS_CPUB_CLK_CNTL 0x208`
clk: meson: g12a: add peripheral clock controller Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com 2019-02-01 17:53:44 +03:00			`#define HHI_VPU_CLKB_CNTL 0x20C`
clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to the CPU clock tree with a supplementaty mux to select the CPU0 clock instead. Leave this as read-only since it's set up by the early boot stages. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> 2019-08-26 10:25:37 +03:00			`#define HHI_SYS_CPU_CLK_CNTL2 0x210`
			`#define HHI_SYS_CPU_CLK_CNTL3 0x214`
			`#define HHI_SYS_CPU_CLK_CNTL4 0x218`
			`#define HHI_SYS_CPU_CLK_CNTL5 0x21c`
			`#define HHI_SYS_CPU_CLK_CNTL6 0x220`
clk: meson: g12a: add peripheral clock controller Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com 2019-02-01 17:53:44 +03:00			`#define HHI_GEN_CLK_CNTL 0x228`
			`#define HHI_VDIN_MEAS_CLK_CNTL 0x250`
			`#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254`
			`#define HHI_NAND_CLK_CNTL 0x25C`
			`#define HHI_SD_EMMC_CLK_CNTL 0x264`
			`#define HHI_MPLL_CNTL0 0x278`
			`#define HHI_MPLL_CNTL1 0x27C`
			`#define HHI_MPLL_CNTL2 0x280`
			`#define HHI_MPLL_CNTL3 0x284`
			`#define HHI_MPLL_CNTL4 0x288`
			`#define HHI_MPLL_CNTL5 0x28c`
			`#define HHI_MPLL_CNTL6 0x290`
			`#define HHI_MPLL_CNTL7 0x294`
			`#define HHI_MPLL_CNTL8 0x298`
			`#define HHI_FIX_PLL_CNTL0 0x2A0`
			`#define HHI_FIX_PLL_CNTL1 0x2A4`
			`#define HHI_FIX_PLL_CNTL3 0x2AC`
			`#define HHI_SYS_PLL_CNTL0 0x2f4`
			`#define HHI_SYS_PLL_CNTL1 0x2f8`
			`#define HHI_SYS_PLL_CNTL2 0x2fc`
			`#define HHI_SYS_PLL_CNTL3 0x300`
			`#define HHI_SYS_PLL_CNTL4 0x304`
			`#define HHI_SYS_PLL_CNTL5 0x308`
			`#define HHI_SYS_PLL_CNTL6 0x30c`
			`#define HHI_HDMI_PLL_CNTL0 0x320`
			`#define HHI_HDMI_PLL_CNTL1 0x324`
			`#define HHI_HDMI_PLL_CNTL2 0x328`
			`#define HHI_HDMI_PLL_CNTL3 0x32c`
			`#define HHI_HDMI_PLL_CNTL4 0x330`
			`#define HHI_HDMI_PLL_CNTL5 0x334`
			`#define HHI_HDMI_PLL_CNTL6 0x338`
			`#define HHI_SPICC_CLK_CNTL 0x3dc`
clk: meson: g12a: Add support for G12B CPUB clocks Update the Meson G12A Clock driver to support the Amlogic G12B SoC. G12B clock driver is very close, the main differences are : - the clock tree is duplicated for the both clusters, and the SYS_PLL are swapped between the clusters - G12B has additional clocks like for CSI an other components Here only the cpu clock tree is handled. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> 2019-05-28 11:07:57 +03:00			`#define HHI_SYS1_PLL_CNTL0 0x380`
			`#define HHI_SYS1_PLL_CNTL1 0x384`
			`#define HHI_SYS1_PLL_CNTL2 0x388`
			`#define HHI_SYS1_PLL_CNTL3 0x38c`
			`#define HHI_SYS1_PLL_CNTL4 0x390`
			`#define HHI_SYS1_PLL_CNTL5 0x394`
			`#define HHI_SYS1_PLL_CNTL6 0x398`
clk: meson: g12a: add peripheral clock controller Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com 2019-02-01 17:53:44 +03:00
			`#endif /* __G12A_H */`