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/*
* Copyright ( C ) 2008 Nokia Corporation
* Author : Tomi Valkeinen < tomi . valkeinen @ nokia . com >
*
* This program is free software ; you can redistribute it and / or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation .
*
* This program is distributed in the hope that it will be useful , but WITHOUT
* ANY WARRANTY ; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE . See the GNU General Public License for
* more details .
*
* You should have received a copy of the GNU General Public License along with
* this program . If not , see < http : //www.gnu.org/licenses/>.
*/
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# ifndef __OMAP_OMAPDSS_H
# define __OMAP_OMAPDSS_H
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# include <linux/list.h>
# include <linux/kobject.h>
# include <linux/device.h>
# define DISPC_IRQ_FRAMEDONE (1 << 0)
# define DISPC_IRQ_VSYNC (1 << 1)
# define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
# define DISPC_IRQ_EVSYNC_ODD (1 << 3)
# define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
# define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
# define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
# define DISPC_IRQ_GFX_END_WIN (1 << 7)
# define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
# define DISPC_IRQ_OCP_ERR (1 << 9)
# define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
# define DISPC_IRQ_VID1_END_WIN (1 << 11)
# define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
# define DISPC_IRQ_VID2_END_WIN (1 << 13)
# define DISPC_IRQ_SYNC_LOST (1 << 14)
# define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
# define DISPC_IRQ_WAKEUP (1 << 16)
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# define DISPC_IRQ_SYNC_LOST2 (1 << 17)
# define DISPC_IRQ_VSYNC2 (1 << 18)
# define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
# define DISPC_IRQ_FRAMEDONE2 (1 << 22)
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# define DISPC_IRQ_FRAMEDONEWB (1 << 23)
# define DISPC_IRQ_FRAMEDONETV (1 << 24)
# define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
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struct omap_dss_device ;
struct omap_overlay_manager ;
enum omap_display_type {
OMAP_DISPLAY_TYPE_NONE = 0 ,
OMAP_DISPLAY_TYPE_DPI = 1 < < 0 ,
OMAP_DISPLAY_TYPE_DBI = 1 < < 1 ,
OMAP_DISPLAY_TYPE_SDI = 1 < < 2 ,
OMAP_DISPLAY_TYPE_DSI = 1 < < 3 ,
OMAP_DISPLAY_TYPE_VENC = 1 < < 4 ,
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OMAP_DISPLAY_TYPE_HDMI = 1 < < 5 ,
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} ;
enum omap_plane {
OMAP_DSS_GFX = 0 ,
OMAP_DSS_VIDEO1 = 1 ,
OMAP_DSS_VIDEO2 = 2
} ;
enum omap_channel {
OMAP_DSS_CHANNEL_LCD = 0 ,
OMAP_DSS_CHANNEL_DIGIT = 1 ,
OMAP: DSS2: Represent DISPC register defines with channel as parameter
On OMAP4, we have a new DISPC channel for Overlay Manager LCD2. There is a set
of regsiters for LCD2 channel similar to the existing LCD channel, like
DISPC_CONTROL2, DISPC_DIVISOR2, DISPC_CONFIG2 and so on.
Introduce new enum members for LCD2 Channel and corresponding Overlay Manager
in display.h.
Represent the following DISPC register defines with channel as a parameter
to differentiate between LCD and LCD2 registers (and also DIGIT in some cases):
DISPC_DEFAULT_COLOR, DISPC_TRANS_COLOR, DISPC_TIMING_H, DISPC_TIMING_V,
DISPC_POL_FREQ, DISPC_DIVISOR, DISPC_SIZE_LCD, DISPC_DATA_CYCLEk,
DISPC_CPR_COEF_R, DISPC_CPR_COEF_G and DISPC_CPR_COEF_B
This parametrization helps in reducing the number of register defines for DISPC.
Replace the existing reads/writes to these registers in this new way.
Also, Introduce defines for registers DISPC_CONTROL2 and DISPC_CONFIG2 which
are used exclusively for LCD2 channel.
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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OMAP_DSS_CHANNEL_LCD2 = 2 ,
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} ;
enum omap_color_mode {
OMAP_DSS_COLOR_CLUT1 = 1 < < 0 , /* BITMAP 1 */
OMAP_DSS_COLOR_CLUT2 = 1 < < 1 , /* BITMAP 2 */
OMAP_DSS_COLOR_CLUT4 = 1 < < 2 , /* BITMAP 4 */
OMAP_DSS_COLOR_CLUT8 = 1 < < 3 , /* BITMAP 8 */
OMAP_DSS_COLOR_RGB12U = 1 < < 4 , /* RGB12, 16-bit container */
OMAP_DSS_COLOR_ARGB16 = 1 < < 5 , /* ARGB16 */
OMAP_DSS_COLOR_RGB16 = 1 < < 6 , /* RGB16 */
OMAP_DSS_COLOR_RGB24U = 1 < < 7 , /* RGB24, 32-bit container */
OMAP_DSS_COLOR_RGB24P = 1 < < 8 , /* RGB24, 24-bit container */
OMAP_DSS_COLOR_YUV2 = 1 < < 9 , /* YUV2 4:2:2 co-sited */
OMAP_DSS_COLOR_UYVY = 1 < < 10 , /* UYVY 4:2:2 co-sited */
OMAP_DSS_COLOR_ARGB32 = 1 < < 11 , /* ARGB32 */
OMAP_DSS_COLOR_RGBA32 = 1 < < 12 , /* RGBA32 */
OMAP_DSS_COLOR_RGBX32 = 1 < < 13 , /* RGBx32 */
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OMAP_DSS_COLOR_NV12 = 1 < < 14 , /* NV12 format: YUV 4:2:0 */
OMAP_DSS_COLOR_RGBA16 = 1 < < 15 , /* RGBA16 - 4444 */
OMAP_DSS_COLOR_RGBX16 = 1 < < 16 , /* RGBx16 - 4444 */
OMAP_DSS_COLOR_ARGB16_1555 = 1 < < 17 , /* ARGB16 - 1555 */
OMAP_DSS_COLOR_XRGB16_1555 = 1 < < 18 , /* xRGB16 - 1555 */
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} ;
enum omap_lcd_display_type {
OMAP_DSS_LCD_DISPLAY_STN ,
OMAP_DSS_LCD_DISPLAY_TFT ,
} ;
enum omap_dss_load_mode {
OMAP_DSS_LOAD_CLUT_AND_FRAME = 0 ,
OMAP_DSS_LOAD_CLUT_ONLY = 1 ,
OMAP_DSS_LOAD_FRAME_ONLY = 2 ,
OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3 ,
} ;
enum omap_dss_trans_key_type {
OMAP_DSS_COLOR_KEY_GFX_DST = 0 ,
OMAP_DSS_COLOR_KEY_VID_SRC = 1 ,
} ;
enum omap_rfbi_te_mode {
OMAP_DSS_RFBI_TE_MODE_1 = 1 ,
OMAP_DSS_RFBI_TE_MODE_2 = 2 ,
} ;
enum omap_panel_config {
OMAP_DSS_LCD_IVS = 1 < < 0 ,
OMAP_DSS_LCD_IHS = 1 < < 1 ,
OMAP_DSS_LCD_IPC = 1 < < 2 ,
OMAP_DSS_LCD_IEO = 1 < < 3 ,
OMAP_DSS_LCD_RF = 1 < < 4 ,
OMAP_DSS_LCD_ONOFF = 1 < < 5 ,
OMAP_DSS_LCD_TFT = 1 < < 20 ,
} ;
enum omap_dss_venc_type {
OMAP_DSS_VENC_TYPE_COMPOSITE ,
OMAP_DSS_VENC_TYPE_SVIDEO ,
} ;
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enum omap_dss_dsi_pixel_format {
OMAP_DSS_DSI_FMT_RGB888 ,
OMAP_DSS_DSI_FMT_RGB666 ,
OMAP_DSS_DSI_FMT_RGB666_PACKED ,
OMAP_DSS_DSI_FMT_RGB565 ,
} ;
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enum omap_dss_dsi_mode {
OMAP_DSS_DSI_CMD_MODE = 0 ,
OMAP_DSS_DSI_VIDEO_MODE ,
} ;
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enum omap_display_caps {
OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 < < 0 ,
OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 < < 1 ,
} ;
enum omap_dss_display_state {
OMAP_DSS_DISPLAY_DISABLED = 0 ,
OMAP_DSS_DISPLAY_ACTIVE ,
OMAP_DSS_DISPLAY_SUSPENDED ,
} ;
/* XXX perhaps this should be removed */
enum omap_dss_overlay_managers {
OMAP_DSS_OVL_MGR_LCD ,
OMAP_DSS_OVL_MGR_TV ,
OMAP: DSS2: Represent DISPC register defines with channel as parameter
On OMAP4, we have a new DISPC channel for Overlay Manager LCD2. There is a set
of regsiters for LCD2 channel similar to the existing LCD channel, like
DISPC_CONTROL2, DISPC_DIVISOR2, DISPC_CONFIG2 and so on.
Introduce new enum members for LCD2 Channel and corresponding Overlay Manager
in display.h.
Represent the following DISPC register defines with channel as a parameter
to differentiate between LCD and LCD2 registers (and also DIGIT in some cases):
DISPC_DEFAULT_COLOR, DISPC_TRANS_COLOR, DISPC_TIMING_H, DISPC_TIMING_V,
DISPC_POL_FREQ, DISPC_DIVISOR, DISPC_SIZE_LCD, DISPC_DATA_CYCLEk,
DISPC_CPR_COEF_R, DISPC_CPR_COEF_G and DISPC_CPR_COEF_B
This parametrization helps in reducing the number of register defines for DISPC.
Replace the existing reads/writes to these registers in this new way.
Also, Introduce defines for registers DISPC_CONTROL2 and DISPC_CONFIG2 which
are used exclusively for LCD2 channel.
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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OMAP_DSS_OVL_MGR_LCD2 ,
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} ;
enum omap_dss_rotation_type {
OMAP_DSS_ROT_DMA = 0 ,
OMAP_DSS_ROT_VRFB = 1 ,
} ;
/* clockwise rotation angle */
enum omap_dss_rotation_angle {
OMAP_DSS_ROT_0 = 0 ,
OMAP_DSS_ROT_90 = 1 ,
OMAP_DSS_ROT_180 = 2 ,
OMAP_DSS_ROT_270 = 3 ,
} ;
enum omap_overlay_caps {
OMAP_DSS_OVL_CAP_SCALE = 1 < < 0 ,
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OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 < < 1 ,
OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 < < 2 ,
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} ;
enum omap_overlay_manager_caps {
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OMAP_DSS_DUMMY_VALUE , /* add a dummy value to prevent compiler error */
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} ;
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enum omap_dss_clk_source {
OMAP_DSS_CLK_SRC_FCK = 0 , /* OMAP2/3: DSS1_ALWON_FCLK
* OMAP4 : DSS_FCLK */
OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC , /* OMAP3: DSI1_PLL_FCLK
* OMAP4 : PLL1_CLK1 */
OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI , /* OMAP3: DSI2_PLL_FCLK
* OMAP4 : PLL1_CLK2 */
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OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC , /* OMAP4: PLL2_CLK1 */
OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI , /* OMAP4: PLL2_CLK2 */
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} ;
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/* RFBI */
struct rfbi_timings {
int cs_on_time ;
int cs_off_time ;
int we_on_time ;
int we_off_time ;
int re_on_time ;
int re_off_time ;
int we_cycle_time ;
int re_cycle_time ;
int cs_pulse_width ;
int access_time ;
int clk_div ;
u32 tim [ 5 ] ; /* set by rfbi_convert_timings() */
int converted ;
} ;
void omap_rfbi_write_command ( const void * buf , u32 len ) ;
void omap_rfbi_read_data ( void * buf , u32 len ) ;
void omap_rfbi_write_data ( const void * buf , u32 len ) ;
void omap_rfbi_write_pixels ( const void __iomem * buf , int scr_width ,
u16 x , u16 y ,
u16 w , u16 h ) ;
int omap_rfbi_enable_te ( bool enable , unsigned line ) ;
int omap_rfbi_setup_te ( enum omap_rfbi_te_mode mode ,
unsigned hs_pulse_time , unsigned vs_pulse_time ,
int hs_pol_inv , int vs_pol_inv , int extif_div ) ;
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void rfbi_bus_lock ( void ) ;
void rfbi_bus_unlock ( void ) ;
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/* DSI */
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struct omap_dss_dsi_videomode_data {
/* DSI video mode blanking data */
/* Unit: byte clock cycles */
u16 hsa ;
u16 hfp ;
u16 hbp ;
/* Unit: line clocks */
u16 vsa ;
u16 vfp ;
u16 vbp ;
/* DSI blanking modes */
int blanking_mode ;
int hsa_blanking_mode ;
int hbp_blanking_mode ;
int hfp_blanking_mode ;
/* Video port sync events */
int vp_de_pol ;
int vp_hsync_pol ;
int vp_vsync_pol ;
bool vp_vsync_end ;
bool vp_hsync_end ;
bool ddr_clk_always_on ;
int window_sync ;
} ;
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void dsi_bus_lock ( struct omap_dss_device * dssdev ) ;
void dsi_bus_unlock ( struct omap_dss_device * dssdev ) ;
int dsi_vc_dcs_write ( struct omap_dss_device * dssdev , int channel , u8 * data ,
int len ) ;
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int dsi_vc_generic_write ( struct omap_dss_device * dssdev , int channel , u8 * data ,
int len ) ;
int dsi_vc_dcs_write_0 ( struct omap_dss_device * dssdev , int channel , u8 dcs_cmd ) ;
int dsi_vc_generic_write_0 ( struct omap_dss_device * dssdev , int channel ) ;
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int dsi_vc_dcs_write_1 ( struct omap_dss_device * dssdev , int channel , u8 dcs_cmd ,
u8 param ) ;
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int dsi_vc_generic_write_1 ( struct omap_dss_device * dssdev , int channel ,
u8 param ) ;
int dsi_vc_generic_write_2 ( struct omap_dss_device * dssdev , int channel ,
u8 param1 , u8 param2 ) ;
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int dsi_vc_dcs_write_nosync ( struct omap_dss_device * dssdev , int channel ,
u8 * data , int len ) ;
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int dsi_vc_generic_write_nosync ( struct omap_dss_device * dssdev , int channel ,
u8 * data , int len ) ;
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int dsi_vc_dcs_read ( struct omap_dss_device * dssdev , int channel , u8 dcs_cmd ,
u8 * buf , int buflen ) ;
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int dsi_vc_generic_read_0 ( struct omap_dss_device * dssdev , int channel , u8 * buf ,
int buflen ) ;
int dsi_vc_generic_read_1 ( struct omap_dss_device * dssdev , int channel , u8 param ,
u8 * buf , int buflen ) ;
int dsi_vc_generic_read_2 ( struct omap_dss_device * dssdev , int channel ,
u8 param1 , u8 param2 , u8 * buf , int buflen ) ;
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int dsi_vc_set_max_rx_packet_size ( struct omap_dss_device * dssdev , int channel ,
u16 len ) ;
int dsi_vc_send_null ( struct omap_dss_device * dssdev , int channel ) ;
int dsi_vc_send_bta_sync ( struct omap_dss_device * dssdev , int channel ) ;
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int dsi_video_mode_enable ( struct omap_dss_device * dssdev , int channel ) ;
void dsi_video_mode_disable ( struct omap_dss_device * dssdev , int channel ) ;
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/* Board specific data */
struct omap_dss_board_info {
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int ( * get_context_loss_count ) ( struct device * dev ) ;
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int num_devices ;
struct omap_dss_device * * devices ;
struct omap_dss_device * default_device ;
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int ( * dsi_enable_pads ) ( int dsi_id , unsigned lane_mask ) ;
void ( * dsi_disable_pads ) ( int dsi_id , unsigned lane_mask ) ;
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} ;
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# if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
/* Init with the board info */
extern int omap_display_init ( struct omap_dss_board_info * board_data ) ;
# else
static inline int omap_display_init ( struct omap_dss_board_info * board_data )
{
return 0 ;
}
# endif
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struct omap_display_platform_data {
struct omap_dss_board_info * board_data ;
/* TODO: Additional members to be added when PM is considered */
} ;
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struct omap_video_timings {
/* Unit: pixels */
u16 x_res ;
/* Unit: pixels */
u16 y_res ;
/* Unit: KHz */
u32 pixel_clock ;
/* Unit: pixel clocks */
u16 hsw ; /* Horizontal synchronization pulse width */
/* Unit: pixel clocks */
u16 hfp ; /* Horizontal front porch */
/* Unit: pixel clocks */
u16 hbp ; /* Horizontal back porch */
/* Unit: line clocks */
u16 vsw ; /* Vertical synchronization pulse width */
/* Unit: line clocks */
u16 vfp ; /* Vertical front porch */
/* Unit: line clocks */
u16 vbp ; /* Vertical back porch */
} ;
# ifdef CONFIG_OMAP2_DSS_VENC
/* Hardcoded timings for tv modes. Venc only uses these to
* identify the mode , and does not actually use the configs
* itself . However , the configs should be something that
* a normal monitor can also show */
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extern const struct omap_video_timings omap_dss_pal_timings ;
extern const struct omap_video_timings omap_dss_ntsc_timings ;
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# endif
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struct omap_dss_cpr_coefs {
s16 rr , rg , rb ;
s16 gr , gg , gb ;
s16 br , bg , bb ;
} ;
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struct omap_overlay_info {
bool enabled ;
u32 paddr ;
void __iomem * vaddr ;
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u32 p_uv_addr ; /* for NV12 format */
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u16 screen_width ;
u16 width ;
u16 height ;
enum omap_color_mode color_mode ;
u8 rotation ;
enum omap_dss_rotation_type rotation_type ;
bool mirror ;
u16 pos_x ;
u16 pos_y ;
u16 out_width ; /* if 0, out_width == width */
u16 out_height ; /* if 0, out_height == height */
u8 global_alpha ;
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u8 pre_mult_alpha ;
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} ;
struct omap_overlay {
struct kobject kobj ;
struct list_head list ;
/* static fields */
const char * name ;
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enum omap_plane id ;
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enum omap_color_mode supported_modes ;
enum omap_overlay_caps caps ;
/* dynamic fields */
struct omap_overlay_manager * manager ;
struct omap_overlay_info info ;
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bool manager_changed ;
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/* if true, info has been changed, but not applied() yet */
bool info_dirty ;
int ( * set_manager ) ( struct omap_overlay * ovl ,
struct omap_overlay_manager * mgr ) ;
int ( * unset_manager ) ( struct omap_overlay * ovl ) ;
int ( * set_overlay_info ) ( struct omap_overlay * ovl ,
struct omap_overlay_info * info ) ;
void ( * get_overlay_info ) ( struct omap_overlay * ovl ,
struct omap_overlay_info * info ) ;
int ( * wait_for_go ) ( struct omap_overlay * ovl ) ;
} ;
struct omap_overlay_manager_info {
u32 default_color ;
enum omap_dss_trans_key_type trans_key_type ;
u32 trans_key ;
bool trans_enabled ;
bool alpha_enabled ;
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bool cpr_enable ;
struct omap_dss_cpr_coefs cpr_coefs ;
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} ;
struct omap_overlay_manager {
struct kobject kobj ;
struct list_head list ;
/* static fields */
const char * name ;
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enum omap_channel id ;
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enum omap_overlay_manager_caps caps ;
int num_overlays ;
struct omap_overlay * * overlays ;
enum omap_display_type supported_displays ;
/* dynamic fields */
struct omap_dss_device * device ;
struct omap_overlay_manager_info info ;
bool device_changed ;
/* if true, info has been changed but not applied() yet */
bool info_dirty ;
int ( * set_device ) ( struct omap_overlay_manager * mgr ,
struct omap_dss_device * dssdev ) ;
int ( * unset_device ) ( struct omap_overlay_manager * mgr ) ;
int ( * set_manager_info ) ( struct omap_overlay_manager * mgr ,
struct omap_overlay_manager_info * info ) ;
void ( * get_manager_info ) ( struct omap_overlay_manager * mgr ,
struct omap_overlay_manager_info * info ) ;
int ( * apply ) ( struct omap_overlay_manager * mgr ) ;
int ( * wait_for_go ) ( struct omap_overlay_manager * mgr ) ;
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int ( * wait_for_vsync ) ( struct omap_overlay_manager * mgr ) ;
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int ( * enable ) ( struct omap_overlay_manager * mgr ) ;
int ( * disable ) ( struct omap_overlay_manager * mgr ) ;
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} ;
struct omap_dss_device {
struct device dev ;
enum omap_display_type type ;
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enum omap_channel channel ;
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union {
struct {
u8 data_lines ;
} dpi ;
struct {
u8 channel ;
u8 data_lines ;
} rfbi ;
struct {
u8 datapairs ;
} sdi ;
struct {
u8 clk_lane ;
u8 clk_pol ;
u8 data1_lane ;
u8 data1_pol ;
u8 data2_lane ;
u8 data2_pol ;
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u8 data3_lane ;
u8 data3_pol ;
u8 data4_lane ;
u8 data4_pol ;
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int module ;
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bool ext_te ;
u8 ext_te_gpio ;
} dsi ;
struct {
enum omap_dss_venc_type type ;
bool invert_polarity ;
} venc ;
} phy ;
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struct {
struct {
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struct {
u16 lck_div ;
u16 pck_div ;
enum omap_dss_clk_source lcd_clk_src ;
} channel ;
enum omap_dss_clk_source dispc_fclk_src ;
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} dispc ;
struct {
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/* regn is one greater than TRM's REGN value */
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u16 regn ;
u16 regm ;
u16 regm_dispc ;
u16 regm_dsi ;
u16 lp_clk_div ;
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enum omap_dss_clk_source dsi_fclk_src ;
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} dsi ;
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struct {
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/* regn is one greater than TRM's REGN value */
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u16 regn ;
u16 regm2 ;
} hdmi ;
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} clocks ;
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struct {
struct omap_video_timings timings ;
int acbi ; /* ac-bias pin transitions per interrupt */
/* Unit: line clocks */
int acb ; /* ac-bias pin frequency */
enum omap_panel_config config ;
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enum omap_dss_dsi_pixel_format dsi_pix_fmt ;
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enum omap_dss_dsi_mode dsi_mode ;
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struct omap_dss_dsi_videomode_data dsi_vm_data ;
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} panel ;
struct {
u8 pixel_size ;
struct rfbi_timings rfbi_timings ;
} ctrl ;
int reset_gpio ;
int max_backlight_level ;
const char * name ;
/* used to match device to driver */
const char * driver_name ;
void * data ;
struct omap_dss_driver * driver ;
/* helper variable for driver suspend/resume */
bool activate_after_resume ;
enum omap_display_caps caps ;
struct omap_overlay_manager * manager ;
enum omap_dss_display_state state ;
/* platform specific */
int ( * platform_enable ) ( struct omap_dss_device * dssdev ) ;
void ( * platform_disable ) ( struct omap_dss_device * dssdev ) ;
int ( * set_backlight ) ( struct omap_dss_device * dssdev , int level ) ;
int ( * get_backlight ) ( struct omap_dss_device * dssdev ) ;
} ;
struct omap_dss_driver {
struct device_driver driver ;
int ( * probe ) ( struct omap_dss_device * ) ;
void ( * remove ) ( struct omap_dss_device * ) ;
int ( * enable ) ( struct omap_dss_device * display ) ;
void ( * disable ) ( struct omap_dss_device * display ) ;
int ( * suspend ) ( struct omap_dss_device * display ) ;
int ( * resume ) ( struct omap_dss_device * display ) ;
int ( * run_test ) ( struct omap_dss_device * display , int test ) ;
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int ( * update ) ( struct omap_dss_device * dssdev ,
u16 x , u16 y , u16 w , u16 h ) ;
int ( * sync ) ( struct omap_dss_device * dssdev ) ;
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int ( * enable_te ) ( struct omap_dss_device * dssdev , bool enable ) ;
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int ( * get_te ) ( struct omap_dss_device * dssdev ) ;
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u8 ( * get_rotate ) ( struct omap_dss_device * dssdev ) ;
int ( * set_rotate ) ( struct omap_dss_device * dssdev , u8 rotate ) ;
bool ( * get_mirror ) ( struct omap_dss_device * dssdev ) ;
int ( * set_mirror ) ( struct omap_dss_device * dssdev , bool enable ) ;
int ( * memory_read ) ( struct omap_dss_device * dssdev ,
void * buf , size_t size ,
u16 x , u16 y , u16 w , u16 h ) ;
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void ( * get_resolution ) ( struct omap_dss_device * dssdev ,
u16 * xres , u16 * yres ) ;
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void ( * get_dimensions ) ( struct omap_dss_device * dssdev ,
u32 * width , u32 * height ) ;
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int ( * get_recommended_bpp ) ( struct omap_dss_device * dssdev ) ;
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int ( * check_timings ) ( struct omap_dss_device * dssdev ,
struct omap_video_timings * timings ) ;
void ( * set_timings ) ( struct omap_dss_device * dssdev ,
struct omap_video_timings * timings ) ;
void ( * get_timings ) ( struct omap_dss_device * dssdev ,
struct omap_video_timings * timings ) ;
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int ( * set_wss ) ( struct omap_dss_device * dssdev , u32 wss ) ;
u32 ( * get_wss ) ( struct omap_dss_device * dssdev ) ;
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} ;
int omap_dss_register_driver ( struct omap_dss_driver * ) ;
void omap_dss_unregister_driver ( struct omap_dss_driver * ) ;
void omap_dss_get_device ( struct omap_dss_device * dssdev ) ;
void omap_dss_put_device ( struct omap_dss_device * dssdev ) ;
# define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
struct omap_dss_device * omap_dss_get_next_device ( struct omap_dss_device * from ) ;
struct omap_dss_device * omap_dss_find_device ( void * data ,
int ( * match ) ( struct omap_dss_device * dssdev , void * data ) ) ;
int omap_dss_start_device ( struct omap_dss_device * dssdev ) ;
void omap_dss_stop_device ( struct omap_dss_device * dssdev ) ;
int omap_dss_get_num_overlay_managers ( void ) ;
struct omap_overlay_manager * omap_dss_get_overlay_manager ( int num ) ;
int omap_dss_get_num_overlays ( void ) ;
struct omap_overlay * omap_dss_get_overlay ( int num ) ;
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void omapdss_default_get_resolution ( struct omap_dss_device * dssdev ,
u16 * xres , u16 * yres ) ;
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int omapdss_default_get_recommended_bpp ( struct omap_dss_device * dssdev ) ;
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typedef void ( * omap_dispc_isr_t ) ( void * arg , u32 mask ) ;
int omap_dispc_register_isr ( omap_dispc_isr_t isr , void * arg , u32 mask ) ;
int omap_dispc_unregister_isr ( omap_dispc_isr_t isr , void * arg , u32 mask ) ;
int omap_dispc_wait_for_irq_timeout ( u32 irqmask , unsigned long timeout ) ;
int omap_dispc_wait_for_irq_interruptible_timeout ( u32 irqmask ,
unsigned long timeout ) ;
# define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
# define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
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void omapdss_dsi_vc_enable_hs ( struct omap_dss_device * dssdev , int channel ,
bool enable ) ;
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int omapdss_dsi_enable_te ( struct omap_dss_device * dssdev , bool enable ) ;
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int omap_dsi_prepare_update ( struct omap_dss_device * dssdev ,
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u16 * x , u16 * y , u16 * w , u16 * h ,
bool enlarge_update_area ) ;
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int omap_dsi_update ( struct omap_dss_device * dssdev ,
int channel ,
u16 x , u16 y , u16 w , u16 h ,
void ( * callback ) ( int , void * ) , void * data ) ;
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int omap_dsi_request_vc ( struct omap_dss_device * dssdev , int * channel ) ;
int omap_dsi_set_vc_id ( struct omap_dss_device * dssdev , int channel , int vc_id ) ;
void omap_dsi_release_vc ( struct omap_dss_device * dssdev , int channel ) ;
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int omapdss_dsi_display_enable ( struct omap_dss_device * dssdev ) ;
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void omapdss_dsi_display_disable ( struct omap_dss_device * dssdev ,
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bool disconnect_lanes , bool enter_ulps ) ;
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int omapdss_dpi_display_enable ( struct omap_dss_device * dssdev ) ;
void omapdss_dpi_display_disable ( struct omap_dss_device * dssdev ) ;
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void dpi_set_timings ( struct omap_dss_device * dssdev ,
struct omap_video_timings * timings ) ;
int dpi_check_timings ( struct omap_dss_device * dssdev ,
struct omap_video_timings * timings ) ;
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int omapdss_sdi_display_enable ( struct omap_dss_device * dssdev ) ;
void omapdss_sdi_display_disable ( struct omap_dss_device * dssdev ) ;
int omapdss_rfbi_display_enable ( struct omap_dss_device * dssdev ) ;
void omapdss_rfbi_display_disable ( struct omap_dss_device * dssdev ) ;
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int omap_rfbi_prepare_update ( struct omap_dss_device * dssdev ,
u16 * x , u16 * y , u16 * w , u16 * h ) ;
int omap_rfbi_update ( struct omap_dss_device * dssdev ,
u16 x , u16 y , u16 w , u16 h ,
void ( * callback ) ( void * ) , void * data ) ;
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int omap_rfbi_configure ( struct omap_dss_device * dssdev , int pixel_size ,
int data_lines ) ;
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# endif