linux/arch/arm/mach-imx/iim.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 */

#ifndef __ASM_ARCH_MXC_IIM_H__
#define __ASM_ARCH_MXC_IIM_H__

/* Register offsets */
#define MXC_IIMSTAT             0x0000
#define MXC_IIMSTATM            0x0004
#define MXC_IIMERR              0x0008
#define MXC_IIMEMASK            0x000C
#define MXC_IIMFCTL             0x0010
#define MXC_IIMUA               0x0014
#define MXC_IIMLA               0x0018
#define MXC_IIMSDAT             0x001C
#define MXC_IIMPREV             0x0020
#define MXC_IIMSREV             0x0024
#define MXC_IIMPRG_P            0x0028
#define MXC_IIMSCS0             0x002C
#define MXC_IIMSCS1             0x0030
#define MXC_IIMSCS2             0x0034
#define MXC_IIMSCS3             0x0038
#define MXC_IIMFBAC0            0x0800
#define MXC_IIMJAC              0x0804
#define MXC_IIMHWV1             0x0808
#define MXC_IIMHWV2             0x080C
#define MXC_IIMHAB0             0x0810
#define MXC_IIMHAB1             0x0814
/* Definitions for i.MX27 TO2 */
#define MXC_IIMMAC              0x0814
#define MXC_IIMPREV_FUSE        0x0818
#define MXC_IIMSREV_FUSE        0x081C
#define MXC_IIMSJC_CHALL_0      0x0820
#define MXC_IIMSJC_CHALL_7      0x083C
#define MXC_IIMFB0UC17          0x0840
#define MXC_IIMFB0UC255         0x0BFC
#define MXC_IIMFBAC1            0x0C00
/* Definitions for i.MX27 TO2 */
#define MXC_IIMSUID             0x0C04
#define MXC_IIMKEY0             0x0C04
#define MXC_IIMKEY20            0x0C54
#define MXC_IIMSJC_RESP_0       0x0C58
#define MXC_IIMSJC_RESP_7       0x0C74
#define MXC_IIMFB1UC30          0x0C78
#define MXC_IIMFB1UC255         0x0FFC

/* Bit definitions */

#define MXC_IIMHWV1_WLOCK               (0x1 << 7)
#define MXC_IIMHWV1_MCU_ENDIAN          (0x1 << 6)
#define MXC_IIMHWV1_DSP_ENDIAN          (0x1 << 5)
#define MXC_IIMHWV1_BOOT_INT            (0x1 << 4)
#define MXC_IIMHWV1_SCC_DISABLE         (0x1 << 3)
#define MXC_IIMHWV1_HANTRO_DISABLE      (0x1 << 2)
#define MXC_IIMHWV1_MEMSTICK_DIS        (0x1 << 1)

#define MXC_IIMHWV2_WLOCK               (0x1 << 7)
#define MXC_IIMHWV2_BP_SDMA             (0x1 << 6)
#define MXC_IIMHWV2_SCM_DCM             (0x1 << 5)

#endif /* __ASM_ARCH_MXC_IIM_H__ */
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option [no]_[pad]_[ctrl] any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 176 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154040.652910950@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-19 15:51:31 +02:00			`/* SPDX-License-Identifier: GPL-2.0-or-later */`
i.MX2 family: Add basic mach support (headers) This patch adds basic mach support for the mx2 processor family, based on the original freescale code and adapted to mainline kernel coding style. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> 2008-07-05 10:02:56 +02:00			`/*`
			`* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.`
			`* Copyright 2008 Juergen Beisert, kernel@pengutronix.de`
			`*/`

			`#ifndef __ASM_ARCH_MXC_IIM_H__`
			`#define __ASM_ARCH_MXC_IIM_H__`

			`/* Register offsets */`
			`#define MXC_IIMSTAT 0x0000`
			`#define MXC_IIMSTATM 0x0004`
			`#define MXC_IIMERR 0x0008`
			`#define MXC_IIMEMASK 0x000C`
			`#define MXC_IIMFCTL 0x0010`
			`#define MXC_IIMUA 0x0014`
			`#define MXC_IIMLA 0x0018`
			`#define MXC_IIMSDAT 0x001C`
			`#define MXC_IIMPREV 0x0020`
			`#define MXC_IIMSREV 0x0024`
			`#define MXC_IIMPRG_P 0x0028`
			`#define MXC_IIMSCS0 0x002C`
			`#define MXC_IIMSCS1 0x0030`
			`#define MXC_IIMSCS2 0x0034`
			`#define MXC_IIMSCS3 0x0038`
			`#define MXC_IIMFBAC0 0x0800`
			`#define MXC_IIMJAC 0x0804`
			`#define MXC_IIMHWV1 0x0808`
			`#define MXC_IIMHWV2 0x080C`
			`#define MXC_IIMHAB0 0x0810`
			`#define MXC_IIMHAB1 0x0814`
			`/* Definitions for i.MX27 TO2 */`
			`#define MXC_IIMMAC 0x0814`
			`#define MXC_IIMPREV_FUSE 0x0818`
			`#define MXC_IIMSREV_FUSE 0x081C`
			`#define MXC_IIMSJC_CHALL_0 0x0820`
			`#define MXC_IIMSJC_CHALL_7 0x083C`
			`#define MXC_IIMFB0UC17 0x0840`
			`#define MXC_IIMFB0UC255 0x0BFC`
			`#define MXC_IIMFBAC1 0x0C00`
			`/* Definitions for i.MX27 TO2 */`
			`#define MXC_IIMSUID 0x0C04`
			`#define MXC_IIMKEY0 0x0C04`
			`#define MXC_IIMKEY20 0x0C54`
			`#define MXC_IIMSJC_RESP_0 0x0C58`
			`#define MXC_IIMSJC_RESP_7 0x0C74`
			`#define MXC_IIMFB1UC30 0x0C78`
			`#define MXC_IIMFB1UC255 0x0FFC`

			`/* Bit definitions */`

			`#define MXC_IIMHWV1_WLOCK (0x1 << 7)`
			`#define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6)`
			`#define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5)`
			`#define MXC_IIMHWV1_BOOT_INT (0x1 << 4)`
			`#define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3)`
			`#define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2)`
			`#define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1)`

			`#define MXC_IIMHWV2_WLOCK (0x1 << 7)`
			`#define MXC_IIMHWV2_BP_SDMA (0x1 << 6)`
			`#define MXC_IIMHWV2_SCM_DCM (0x1 << 5)`

			`#endif /* __ASM_ARCH_MXC_IIM_H__ */`