2019-06-04 11:11:33 +03:00
// SPDX-License-Identifier: GPL-2.0-only
2013-05-03 13:58:00 +04:00
/*
* Copyright ( C ) 2013 Oskar Andero < oskar . andero @ gmail . com >
2014-10-08 22:42:00 +04:00
* Copyright ( C ) 2014 Rose Technology
* Allan Bendorff Jensen < abj @ rosetechnology . dk >
* Soren Andersen < san @ rosetechnology . dk >
*
* Driver for following ADC chips from Microchip Technology ' s :
* 10 Bit converter
* MCP3001
* MCP3002
* MCP3004
* MCP3008
* - - - - - - - - - - - -
* 12 bit converter
* MCP3201
* MCP3202
* MCP3204
* MCP3208
* - - - - - - - - - - - -
2017-08-22 16:33:00 +03:00
* 13 bit converter
* MCP3301
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
* - - - - - - - - - - - -
* 22 bit converter
* MCP3550
* MCP3551
* MCP3553
2013-05-03 13:58:00 +04:00
*
* Datasheet can be found here :
2014-10-08 22:42:00 +04:00
* http : //ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf mcp3001
* http : //ww1.microchip.com/downloads/en/DeviceDoc/21294E.pdf mcp3002
* http : //ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf mcp3004/08
* http : //ww1.microchip.com/downloads/en/DeviceDoc/21290D.pdf mcp3201
* http : //ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf mcp3202
* http : //ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf mcp3204/08
2015-07-14 16:36:21 +03:00
* http : //ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf mcp3301
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
* http : //ww1.microchip.com/downloads/en/DeviceDoc/21950D.pdf mcp3550/1/3
2013-05-03 13:58:00 +04:00
*/
# include <linux/err.h>
2014-10-08 22:42:00 +04:00
# include <linux/delay.h>
2013-05-03 13:58:00 +04:00
# include <linux/spi/spi.h>
# include <linux/module.h>
# include <linux/iio/iio.h>
# include <linux/regulator/consumer.h>
enum {
2014-10-08 22:42:00 +04:00
mcp3001 ,
mcp3002 ,
mcp3004 ,
mcp3008 ,
mcp3201 ,
mcp3202 ,
2013-05-03 13:58:00 +04:00
mcp3204 ,
mcp3208 ,
2015-07-14 16:36:21 +03:00
mcp3301 ,
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
mcp3550_50 ,
mcp3550_60 ,
mcp3551 ,
mcp3553 ,
2013-05-03 13:58:00 +04:00
} ;
2014-10-08 22:42:00 +04:00
struct mcp320x_chip_info {
const struct iio_chan_spec * channels ;
unsigned int num_channels ;
unsigned int resolution ;
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
unsigned int conv_time ; /* usec */
2014-10-08 22:42:00 +04:00
} ;
2017-09-09 21:32:41 +03:00
/**
* struct mcp320x - Microchip SPI ADC instance
* @ spi : SPI slave ( parent of the IIO device )
* @ msg : SPI message to select a channel and receive a value from the ADC
* @ transfer : SPI transfers used by @ msg
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
* @ start_conv_msg : SPI message to start a conversion by briefly asserting CS
* @ start_conv_transfer : SPI transfer used by @ start_conv_msg
2017-09-09 21:32:41 +03:00
* @ reg : regulator generating Vref
* @ lock : protects read sequences
* @ chip_info : ADC properties
* @ tx_buf : buffer for @ transfer [ 0 ] ( not used on single - channel converters )
* @ rx_buf : buffer for @ transfer [ 1 ]
*/
2013-05-03 13:58:00 +04:00
struct mcp320x {
struct spi_device * spi ;
struct spi_message msg ;
struct spi_transfer transfer [ 2 ] ;
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
struct spi_message start_conv_msg ;
struct spi_transfer start_conv_transfer ;
2013-05-03 13:58:00 +04:00
struct regulator * reg ;
struct mutex lock ;
2014-10-08 22:42:00 +04:00
const struct mcp320x_chip_info * chip_info ;
2015-05-06 19:49:17 +03:00
u8 tx_buf ____cacheline_aligned ;
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
u8 rx_buf [ 4 ] ;
2013-05-03 13:58:00 +04:00
} ;
2014-10-08 22:42:00 +04:00
static int mcp320x_channel_to_tx_data ( int device_index ,
const unsigned int channel , bool differential )
{
int start_bit = 1 ;
switch ( device_index ) {
case mcp3002 :
case mcp3202 :
return ( ( start_bit < < 4 ) | ( ! differential < < 3 ) |
( channel < < 2 ) ) ;
case mcp3004 :
case mcp3204 :
case mcp3008 :
case mcp3208 :
return ( ( start_bit < < 6 ) | ( ! differential < < 5 ) |
( channel < < 2 ) ) ;
default :
return - EINVAL ;
}
}
static int mcp320x_adc_conversion ( struct mcp320x * adc , u8 channel ,
2017-08-22 16:33:00 +03:00
bool differential , int device_index , int * val )
2013-05-03 13:58:00 +04:00
{
int ret ;
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
if ( adc - > chip_info - > conv_time ) {
ret = spi_sync ( adc - > spi , & adc - > start_conv_msg ) ;
if ( ret < 0 )
return ret ;
usleep_range ( adc - > chip_info - > conv_time ,
adc - > chip_info - > conv_time + 100 ) ;
}
2017-09-09 21:32:41 +03:00
memset ( & adc - > rx_buf , 0 , sizeof ( adc - > rx_buf ) ) ;
if ( adc - > chip_info - > num_channels > 1 )
adc - > tx_buf = mcp320x_channel_to_tx_data ( device_index , channel ,
differential ) ;
2014-10-08 22:42:00 +04:00
2017-09-09 21:32:41 +03:00
ret = spi_sync ( adc - > spi , & adc - > msg ) ;
if ( ret < 0 )
return ret ;
2013-05-03 13:58:00 +04:00
2014-10-08 22:42:00 +04:00
switch ( device_index ) {
case mcp3001 :
2017-08-22 16:33:00 +03:00
* val = ( adc - > rx_buf [ 0 ] < < 5 | adc - > rx_buf [ 1 ] > > 3 ) ;
return 0 ;
2014-10-08 22:42:00 +04:00
case mcp3002 :
case mcp3004 :
case mcp3008 :
2017-08-22 16:33:00 +03:00
* val = ( adc - > rx_buf [ 0 ] < < 2 | adc - > rx_buf [ 1 ] > > 6 ) ;
return 0 ;
2014-10-08 22:42:00 +04:00
case mcp3201 :
2017-08-22 16:33:00 +03:00
* val = ( adc - > rx_buf [ 0 ] < < 7 | adc - > rx_buf [ 1 ] > > 1 ) ;
return 0 ;
2014-10-08 22:42:00 +04:00
case mcp3202 :
case mcp3204 :
case mcp3208 :
2017-08-22 16:33:00 +03:00
* val = ( adc - > rx_buf [ 0 ] < < 4 | adc - > rx_buf [ 1 ] > > 4 ) ;
return 0 ;
2015-07-14 16:36:21 +03:00
case mcp3301 :
2017-08-22 16:33:00 +03:00
* val = sign_extend32 ( ( adc - > rx_buf [ 0 ] & 0x1f ) < < 8
| adc - > rx_buf [ 1 ] , 12 ) ;
return 0 ;
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
case mcp3550_50 :
case mcp3550_60 :
case mcp3551 :
case mcp3553 : {
2019-10-13 12:05:42 +03:00
u32 raw = be32_to_cpup ( ( __be32 * ) adc - > rx_buf ) ;
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
if ( ! ( adc - > spi - > mode & SPI_CPOL ) )
raw < < = 1 ; /* strip Data Ready bit in SPI mode 0,0 */
/*
* If the input is within - vref and vref , bit 21 is the sign .
* Up to 12 % overrange or underrange are allowed , in which case
* bit 23 is the sign and bit 0 to 21 is the value .
*/
raw > > = 8 ;
if ( raw & BIT ( 22 ) & & raw & BIT ( 23 ) )
return - EIO ; /* cannot have overrange AND underrange */
else if ( raw & BIT ( 22 ) )
raw & = ~ BIT ( 22 ) ; /* overrange */
else if ( raw & BIT ( 23 ) | | raw & BIT ( 21 ) )
raw | = GENMASK ( 31 , 22 ) ; /* underrange or negative */
* val = ( s32 ) raw ;
return 0 ;
}
2014-10-08 22:42:00 +04:00
default :
return - EINVAL ;
}
2013-05-03 13:58:00 +04:00
}
static int mcp320x_read_raw ( struct iio_dev * indio_dev ,
struct iio_chan_spec const * channel , int * val ,
int * val2 , long mask )
{
struct mcp320x * adc = iio_priv ( indio_dev ) ;
int ret = - EINVAL ;
2014-10-08 22:42:00 +04:00
int device_index = 0 ;
2013-05-03 13:58:00 +04:00
mutex_lock ( & adc - > lock ) ;
2014-10-08 22:42:00 +04:00
device_index = spi_get_device_id ( adc - > spi ) - > driver_data ;
2013-05-03 13:58:00 +04:00
switch ( mask ) {
case IIO_CHAN_INFO_RAW :
2014-10-08 22:42:00 +04:00
ret = mcp320x_adc_conversion ( adc , channel - > address ,
2017-08-22 16:33:00 +03:00
channel - > differential , device_index , val ) ;
2013-05-03 13:58:00 +04:00
if ( ret < 0 )
goto out ;
ret = IIO_VAL_INT ;
break ;
case IIO_CHAN_INFO_SCALE :
ret = regulator_get_voltage ( adc - > reg ) ;
if ( ret < 0 )
goto out ;
2014-10-08 22:42:00 +04:00
/* convert regulator output voltage to mV */
2013-05-03 13:58:00 +04:00
* val = ret / 1000 ;
2014-10-08 22:42:00 +04:00
* val2 = adc - > chip_info - > resolution ;
2013-05-03 13:58:00 +04:00
ret = IIO_VAL_FRACTIONAL_LOG2 ;
break ;
}
out :
mutex_unlock ( & adc - > lock ) ;
return ret ;
}
# define MCP320X_VOLTAGE_CHANNEL(num) \
{ \
. type = IIO_VOLTAGE , \
. indexed = 1 , \
. channel = ( num ) , \
. address = ( num ) , \
. info_mask_separate = BIT ( IIO_CHAN_INFO_RAW ) , \
. info_mask_shared_by_type = BIT ( IIO_CHAN_INFO_SCALE ) \
}
iio: adc: mcp320x: support more differential voltage measurement
mcp320x driver supports the pseudo-differential mode by
in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (0, 1), (2, 3), ...
mcp320x chips except MCP3X01 can also select swapped IN+ and IN-
pairs in the pseudo-differential mode.
i.e. in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (1, 0),
(3, 2), ...
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. So it is useful to provide these, too.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Oskar Andero <oskar.andero@gmail.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Hartmut Knaack <knaack.h@gmx.de>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Peter Meerwald <pmeerw@pmeerw.net>
Cc: linux-iio@vger.kernel.org
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2016-01-07 18:40:30 +03:00
# define MCP320X_VOLTAGE_CHANNEL_DIFF(chan1, chan2) \
2013-05-03 13:58:00 +04:00
{ \
. type = IIO_VOLTAGE , \
. indexed = 1 , \
iio: adc: mcp320x: support more differential voltage measurement
mcp320x driver supports the pseudo-differential mode by
in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (0, 1), (2, 3), ...
mcp320x chips except MCP3X01 can also select swapped IN+ and IN-
pairs in the pseudo-differential mode.
i.e. in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (1, 0),
(3, 2), ...
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. So it is useful to provide these, too.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Oskar Andero <oskar.andero@gmail.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Hartmut Knaack <knaack.h@gmx.de>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Peter Meerwald <pmeerw@pmeerw.net>
Cc: linux-iio@vger.kernel.org
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2016-01-07 18:40:30 +03:00
. channel = ( chan1 ) , \
. channel2 = ( chan2 ) , \
. address = ( chan1 ) , \
2013-05-03 13:58:00 +04:00
. differential = 1 , \
. info_mask_separate = BIT ( IIO_CHAN_INFO_RAW ) , \
. info_mask_shared_by_type = BIT ( IIO_CHAN_INFO_SCALE ) \
}
2014-10-08 22:42:00 +04:00
static const struct iio_chan_spec mcp3201_channels [ ] = {
iio: adc: mcp320x: support more differential voltage measurement
mcp320x driver supports the pseudo-differential mode by
in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (0, 1), (2, 3), ...
mcp320x chips except MCP3X01 can also select swapped IN+ and IN-
pairs in the pseudo-differential mode.
i.e. in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (1, 0),
(3, 2), ...
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. So it is useful to provide these, too.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Oskar Andero <oskar.andero@gmail.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Hartmut Knaack <knaack.h@gmx.de>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Peter Meerwald <pmeerw@pmeerw.net>
Cc: linux-iio@vger.kernel.org
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2016-01-07 18:40:30 +03:00
MCP320X_VOLTAGE_CHANNEL_DIFF ( 0 , 1 ) ,
2014-10-08 22:42:00 +04:00
} ;
static const struct iio_chan_spec mcp3202_channels [ ] = {
MCP320X_VOLTAGE_CHANNEL ( 0 ) ,
MCP320X_VOLTAGE_CHANNEL ( 1 ) ,
iio: adc: mcp320x: support more differential voltage measurement
mcp320x driver supports the pseudo-differential mode by
in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (0, 1), (2, 3), ...
mcp320x chips except MCP3X01 can also select swapped IN+ and IN-
pairs in the pseudo-differential mode.
i.e. in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (1, 0),
(3, 2), ...
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. So it is useful to provide these, too.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Oskar Andero <oskar.andero@gmail.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Hartmut Knaack <knaack.h@gmx.de>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Peter Meerwald <pmeerw@pmeerw.net>
Cc: linux-iio@vger.kernel.org
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2016-01-07 18:40:30 +03:00
MCP320X_VOLTAGE_CHANNEL_DIFF ( 0 , 1 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 1 , 0 ) ,
2014-10-08 22:42:00 +04:00
} ;
2013-05-03 13:58:00 +04:00
static const struct iio_chan_spec mcp3204_channels [ ] = {
MCP320X_VOLTAGE_CHANNEL ( 0 ) ,
MCP320X_VOLTAGE_CHANNEL ( 1 ) ,
MCP320X_VOLTAGE_CHANNEL ( 2 ) ,
MCP320X_VOLTAGE_CHANNEL ( 3 ) ,
iio: adc: mcp320x: support more differential voltage measurement
mcp320x driver supports the pseudo-differential mode by
in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (0, 1), (2, 3), ...
mcp320x chips except MCP3X01 can also select swapped IN+ and IN-
pairs in the pseudo-differential mode.
i.e. in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (1, 0),
(3, 2), ...
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. So it is useful to provide these, too.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Oskar Andero <oskar.andero@gmail.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Hartmut Knaack <knaack.h@gmx.de>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Peter Meerwald <pmeerw@pmeerw.net>
Cc: linux-iio@vger.kernel.org
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2016-01-07 18:40:30 +03:00
MCP320X_VOLTAGE_CHANNEL_DIFF ( 0 , 1 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 1 , 0 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 2 , 3 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 3 , 2 ) ,
2013-05-03 13:58:00 +04:00
} ;
static const struct iio_chan_spec mcp3208_channels [ ] = {
MCP320X_VOLTAGE_CHANNEL ( 0 ) ,
MCP320X_VOLTAGE_CHANNEL ( 1 ) ,
MCP320X_VOLTAGE_CHANNEL ( 2 ) ,
MCP320X_VOLTAGE_CHANNEL ( 3 ) ,
MCP320X_VOLTAGE_CHANNEL ( 4 ) ,
MCP320X_VOLTAGE_CHANNEL ( 5 ) ,
MCP320X_VOLTAGE_CHANNEL ( 6 ) ,
MCP320X_VOLTAGE_CHANNEL ( 7 ) ,
iio: adc: mcp320x: support more differential voltage measurement
mcp320x driver supports the pseudo-differential mode by
in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (0, 1), (2, 3), ...
mcp320x chips except MCP3X01 can also select swapped IN+ and IN-
pairs in the pseudo-differential mode.
i.e. in_voltage'IN+'-voltage'IN-'_raw where (IN+, IN-) = (1, 0),
(3, 2), ...
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. So it is useful to provide these, too.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Oskar Andero <oskar.andero@gmail.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Hartmut Knaack <knaack.h@gmx.de>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Peter Meerwald <pmeerw@pmeerw.net>
Cc: linux-iio@vger.kernel.org
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2016-01-07 18:40:30 +03:00
MCP320X_VOLTAGE_CHANNEL_DIFF ( 0 , 1 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 1 , 0 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 2 , 3 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 3 , 2 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 4 , 5 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 5 , 4 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 6 , 7 ) ,
MCP320X_VOLTAGE_CHANNEL_DIFF ( 7 , 6 ) ,
2013-05-03 13:58:00 +04:00
} ;
static const struct iio_info mcp320x_info = {
. read_raw = mcp320x_read_raw ,
} ;
2014-10-08 22:42:00 +04:00
static const struct mcp320x_chip_info mcp320x_chip_infos [ ] = {
[ mcp3001 ] = {
. channels = mcp3201_channels ,
. num_channels = ARRAY_SIZE ( mcp3201_channels ) ,
. resolution = 10
} ,
[ mcp3002 ] = {
. channels = mcp3202_channels ,
. num_channels = ARRAY_SIZE ( mcp3202_channels ) ,
. resolution = 10
} ,
[ mcp3004 ] = {
. channels = mcp3204_channels ,
. num_channels = ARRAY_SIZE ( mcp3204_channels ) ,
. resolution = 10
} ,
[ mcp3008 ] = {
. channels = mcp3208_channels ,
. num_channels = ARRAY_SIZE ( mcp3208_channels ) ,
. resolution = 10
} ,
[ mcp3201 ] = {
. channels = mcp3201_channels ,
. num_channels = ARRAY_SIZE ( mcp3201_channels ) ,
. resolution = 12
} ,
[ mcp3202 ] = {
. channels = mcp3202_channels ,
. num_channels = ARRAY_SIZE ( mcp3202_channels ) ,
. resolution = 12
} ,
2013-05-03 13:58:00 +04:00
[ mcp3204 ] = {
. channels = mcp3204_channels ,
2014-10-08 22:42:00 +04:00
. num_channels = ARRAY_SIZE ( mcp3204_channels ) ,
. resolution = 12
2013-05-03 13:58:00 +04:00
} ,
[ mcp3208 ] = {
. channels = mcp3208_channels ,
2014-10-08 22:42:00 +04:00
. num_channels = ARRAY_SIZE ( mcp3208_channels ) ,
. resolution = 12
2013-05-03 13:58:00 +04:00
} ,
2015-07-14 16:36:21 +03:00
[ mcp3301 ] = {
. channels = mcp3201_channels ,
. num_channels = ARRAY_SIZE ( mcp3201_channels ) ,
. resolution = 13
} ,
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
[ mcp3550_50 ] = {
. channels = mcp3201_channels ,
. num_channels = ARRAY_SIZE ( mcp3201_channels ) ,
. resolution = 21 ,
/* 2% max deviation + 144 clock periods to exit shutdown */
. conv_time = 80000 * 1.02 + 144000 / 102.4 ,
} ,
[ mcp3550_60 ] = {
. channels = mcp3201_channels ,
. num_channels = ARRAY_SIZE ( mcp3201_channels ) ,
. resolution = 21 ,
. conv_time = 66670 * 1.02 + 144000 / 122.88 ,
} ,
[ mcp3551 ] = {
. channels = mcp3201_channels ,
. num_channels = ARRAY_SIZE ( mcp3201_channels ) ,
. resolution = 21 ,
. conv_time = 73100 * 1.02 + 144000 / 112.64 ,
} ,
[ mcp3553 ] = {
. channels = mcp3201_channels ,
. num_channels = ARRAY_SIZE ( mcp3201_channels ) ,
. resolution = 21 ,
. conv_time = 16670 * 1.02 + 144000 / 122.88 ,
} ,
2013-05-03 13:58:00 +04:00
} ;
static int mcp320x_probe ( struct spi_device * spi )
{
struct iio_dev * indio_dev ;
struct mcp320x * adc ;
2014-10-08 22:42:00 +04:00
const struct mcp320x_chip_info * chip_info ;
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
int ret , device_index ;
2013-05-03 13:58:00 +04:00
2013-07-23 12:58:00 +04:00
indio_dev = devm_iio_device_alloc ( & spi - > dev , sizeof ( * adc ) ) ;
2013-05-03 13:58:00 +04:00
if ( ! indio_dev )
return - ENOMEM ;
adc = iio_priv ( indio_dev ) ;
adc - > spi = spi ;
indio_dev - > dev . parent = & spi - > dev ;
2016-07-03 03:26:33 +03:00
indio_dev - > dev . of_node = spi - > dev . of_node ;
2013-05-03 13:58:00 +04:00
indio_dev - > name = spi_get_device_id ( spi ) - > name ;
indio_dev - > modes = INDIO_DIRECT_MODE ;
indio_dev - > info = & mcp320x_info ;
2017-08-22 16:33:00 +03:00
spi_set_drvdata ( spi , indio_dev ) ;
2013-05-03 13:58:00 +04:00
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
device_index = spi_get_device_id ( spi ) - > driver_data ;
chip_info = & mcp320x_chip_infos [ device_index ] ;
2013-05-03 13:58:00 +04:00
indio_dev - > channels = chip_info - > channels ;
indio_dev - > num_channels = chip_info - > num_channels ;
2015-07-10 23:55:30 +03:00
adc - > chip_info = chip_info ;
2013-05-03 13:58:00 +04:00
adc - > transfer [ 0 ] . tx_buf = & adc - > tx_buf ;
adc - > transfer [ 0 ] . len = sizeof ( adc - > tx_buf ) ;
adc - > transfer [ 1 ] . rx_buf = adc - > rx_buf ;
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
adc - > transfer [ 1 ] . len = DIV_ROUND_UP ( chip_info - > resolution , 8 ) ;
2017-09-09 21:32:41 +03:00
if ( chip_info - > num_channels = = 1 )
/* single-channel converters are rx only (no MOSI pin) */
spi_message_init_with_transfers ( & adc - > msg ,
& adc - > transfer [ 1 ] , 1 ) ;
else
spi_message_init_with_transfers ( & adc - > msg , adc - > transfer ,
ARRAY_SIZE ( adc - > transfer ) ) ;
2013-05-03 13:58:00 +04:00
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
switch ( device_index ) {
case mcp3550_50 :
case mcp3550_60 :
case mcp3551 :
case mcp3553 :
/* rx len increases from 24 to 25 bit in SPI mode 0,0 */
if ( ! ( spi - > mode & SPI_CPOL ) )
adc - > transfer [ 1 ] . len + + ;
/* conversions are started by asserting CS pin for 8 usec */
2020-02-27 15:29:40 +03:00
adc - > start_conv_transfer . delay . value = 8 ;
adc - > start_conv_transfer . delay . unit = SPI_DELAY_UNIT_USECS ;
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
spi_message_init_with_transfers ( & adc - > start_conv_msg ,
& adc - > start_conv_transfer , 1 ) ;
/*
* If CS was previously kept low ( continuous conversion mode )
* and then changed to high , the chip is in shutdown .
* Sometimes it fails to wake from shutdown and clocks out
* only 0xffffff . The magic sequence of performing two
* conversions without delay between them resets the chip
* and ensures all subsequent conversions succeed .
*/
mcp320x_adc_conversion ( adc , 0 , 1 , device_index , & ret ) ;
mcp320x_adc_conversion ( adc , 0 , 1 , device_index , & ret ) ;
}
2013-07-23 12:58:00 +04:00
adc - > reg = devm_regulator_get ( & spi - > dev , " vref " ) ;
if ( IS_ERR ( adc - > reg ) )
return PTR_ERR ( adc - > reg ) ;
2013-05-03 13:58:00 +04:00
ret = regulator_enable ( adc - > reg ) ;
if ( ret < 0 )
2013-07-23 12:58:00 +04:00
return ret ;
2013-05-03 13:58:00 +04:00
mutex_init ( & adc - > lock ) ;
ret = iio_device_register ( indio_dev ) ;
if ( ret < 0 )
goto reg_disable ;
return 0 ;
reg_disable :
regulator_disable ( adc - > reg ) ;
return ret ;
}
static int mcp320x_remove ( struct spi_device * spi )
{
struct iio_dev * indio_dev = spi_get_drvdata ( spi ) ;
struct mcp320x * adc = iio_priv ( indio_dev ) ;
iio_device_unregister ( indio_dev ) ;
regulator_disable ( adc - > reg ) ;
return 0 ;
}
2014-10-08 22:42:00 +04:00
# if defined(CONFIG_OF)
static const struct of_device_id mcp320x_dt_ids [ ] = {
2015-10-14 15:54:39 +03:00
/* NOTE: The use of compatibles with no vendor prefix is deprecated. */
2017-09-09 21:32:41 +03:00
{ . compatible = " mcp3001 " } ,
{ . compatible = " mcp3002 " } ,
{ . compatible = " mcp3004 " } ,
{ . compatible = " mcp3008 " } ,
{ . compatible = " mcp3201 " } ,
{ . compatible = " mcp3202 " } ,
{ . compatible = " mcp3204 " } ,
{ . compatible = " mcp3208 " } ,
{ . compatible = " mcp3301 " } ,
{ . compatible = " microchip,mcp3001 " } ,
{ . compatible = " microchip,mcp3002 " } ,
{ . compatible = " microchip,mcp3004 " } ,
{ . compatible = " microchip,mcp3008 " } ,
{ . compatible = " microchip,mcp3201 " } ,
{ . compatible = " microchip,mcp3202 " } ,
{ . compatible = " microchip,mcp3204 " } ,
{ . compatible = " microchip,mcp3208 " } ,
{ . compatible = " microchip,mcp3301 " } ,
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
{ . compatible = " microchip,mcp3550-50 " } ,
{ . compatible = " microchip,mcp3550-60 " } ,
{ . compatible = " microchip,mcp3551 " } ,
{ . compatible = " microchip,mcp3553 " } ,
2017-09-09 21:32:41 +03:00
{ }
2014-10-08 22:42:00 +04:00
} ;
MODULE_DEVICE_TABLE ( of , mcp320x_dt_ids ) ;
# endif
2013-05-03 13:58:00 +04:00
static const struct spi_device_id mcp320x_id [ ] = {
2014-10-08 22:42:00 +04:00
{ " mcp3001 " , mcp3001 } ,
{ " mcp3002 " , mcp3002 } ,
{ " mcp3004 " , mcp3004 } ,
{ " mcp3008 " , mcp3008 } ,
{ " mcp3201 " , mcp3201 } ,
{ " mcp3202 " , mcp3202 } ,
2013-05-03 13:58:00 +04:00
{ " mcp3204 " , mcp3204 } ,
{ " mcp3208 " , mcp3208 } ,
2015-07-14 16:36:21 +03:00
{ " mcp3301 " , mcp3301 } ,
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
{ " mcp3550-50 " , mcp3550_50 } ,
{ " mcp3550-60 " , mcp3550_60 } ,
{ " mcp3551 " , mcp3551 } ,
{ " mcp3553 " , mcp3553 } ,
2013-05-03 13:58:00 +04:00
{ }
} ;
MODULE_DEVICE_TABLE ( spi , mcp320x_id ) ;
static struct spi_driver mcp320x_driver = {
. driver = {
. name = " mcp320x " ,
2015-08-20 10:07:26 +03:00
. of_match_table = of_match_ptr ( mcp320x_dt_ids ) ,
2013-05-03 13:58:00 +04:00
} ,
. probe = mcp320x_probe ,
. remove = mcp320x_remove ,
. id_table = mcp320x_id ,
} ;
module_spi_driver ( mcp320x_driver ) ;
MODULE_AUTHOR ( " Oskar Andero <oskar.andero@gmail.com> " ) ;
iio: adc: mcp320x: Add support for mcp3550/1/3
These ADCs are marketed as single-channel 22 bit delta-sigma ADCs, but
in reality their resolution is 21 bit with an overrange or underrange
of 12% beyond Vref. In other words, "full scale" means +/- 2^20.
This driver does not explicitly signal back to the user when an
overrange or underrange occurs, but the user can detect it by comparing
the raw value to +/- 2^20 (or the scaled value to Vref).
The chips feature an extended temperature range and high accuracy,
low noise characteristics, but their conversion times are slow with
up to 80 ms +/- 2% (on the MCP3550-50).
Hence, unlike the other ADCs supported by the driver, conversion does
not take place in realtime upon lowering CS. Instead, CS is asserted
for 8 usec to start the conversion. After waiting for the duration of
the conversion, the result can be fetched. While waiting, control of
the bus is ceased so it may be used by a different device.
After the result has been fetched and 10 us have passed, the chip goes
into shutdown and an additional power-up delay of 144 clock periods is
then required to wake the analog circuitry upon the next conversion
(footnote below table 4-1, page 16 in the spec).
Optionally, the chips can be used in so-called "continuous conversion
mode": Conversions then take place continuously and the last result may
be fetched at any time without observing a delay. The mode is enabled
by permanently driving CS low, e.g. by wiring it to ground. The driver
only supports "single conversion mode" for now but should be adaptable
to "continuous conversion mode" with moderate effort.
The chips clock out a 3 byte word, unlike the other ADCs supported by
the driver which all have a lower resolution than 16 bit and thus make
do with 2 bytes. Calculate the word length on probe by rounding up the
resolution to full bytes. Crucially, if the clock idles low, the
transfer is preceded by a useless Data Ready bit which increases its
length from 24 bit to 25 bit = 4 bytes (section 5.5 in the spec).
Autosense this based on the SPI slave's configuration.
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2017-09-09 21:32:41 +03:00
MODULE_DESCRIPTION ( " Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3 " ) ;
2013-05-03 13:58:00 +04:00
MODULE_LICENSE ( " GPL v2 " ) ;
