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/ * NG2 m e m c p y . S : N i a g a r a - 2 o p t i m i z e d m e m c p y .
*
* Copyright ( C ) 2 0 0 7 D a v i d S . M i l l e r ( d a v e m @davemloft.net)
* /
# ifdef _ _ K E R N E L _ _
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# include < l i n u x / l i n k a g e . h >
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# include < a s m / v i s a s m . h >
# include < a s m / a s i . h >
# define G L O B A L _ S P A R E % g 7
# else
# define A S I _ P N F 0 x82
# define A S I _ B L K _ P 0 x f0
# define A S I _ B L K _ I N I T _ Q U A D _ L D D _ P 0 x e 2
# define F P R S _ F E F 0 x04
# ifdef M E M C P Y _ D E B U G
# define V I S E n t r y H a l f r d % f p r s , % o 5 ; wr %g0, FPRS_FEF, %fprs; \
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clr % g 1 ; clr %g2; clr %g3; clr %g5; subcc %g0, %g0, %g0;
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# define V I S E x i t H a l f a n d % o 5 , F P R S _ F E F , % o 5 ; wr %o5, 0x0, %fprs
# else
# define V I S E n t r y H a l f r d % f p r s , % o 5 ; wr %g0, FPRS_FEF, %fprs
# define V I S E x i t H a l f a n d % o 5 , F P R S _ F E F , % o 5 ; wr %o5, 0x0, %fprs
# endif
# define G L O B A L _ S P A R E % g 5
# endif
# ifndef S T O R E _ A S I
# ifndef S I M U L A T E _ N I A G A R A _ O N _ N O N _ N I A G A R A
# define S T O R E _ A S I A S I _ B L K _ I N I T _ Q U A D _ L D D _ P
# else
# define S T O R E _ A S I 0 x80 / * A S I _ P * /
# endif
# endif
# ifndef E X _ L D
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# define E X _ L D ( x ,y ) x
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# endif
sparc64: fix FP corruption in user copy functions
Short story: Exception handlers used by some copy_to_user() and
copy_from_user() functions do not diligently clean up floating point
register usage, and this can result in a user process seeing invalid
values in floating point registers. This sometimes makes the process
fail.
Long story: Several cpu-specific (NG4, NG2, U1, U3) memcpy functions
use floating point registers and VIS alignaddr/faligndata to
accelerate data copying when source and dest addresses don't align
well. Linux uses a lazy scheme for saving floating point registers; It
is not done upon entering the kernel since it's a very expensive
operation. Rather, it is done only when needed. If the kernel ends up
not using FP regs during the course of some trap or system call, then
it can return to user space without saving or restoring them.
The various memcpy functions begin their FP code with VISEntry (or a
variation thereof), which saves the FP regs. They conclude their FP
code with VISExit (or a variation) which essentially marks the FP regs
"clean", ie, they contain no unsaved values. fprs.FPRS_FEF is turned
off so that a lazy restore will be triggered when/if the user process
accesses floating point regs again.
The bug is that the user copy variants of memcpy, copy_from_user() and
copy_to_user(), employ an exception handling mechanism to detect faults
when accessing user space addresses, and when this handler is invoked,
an immediate return from the function is forced, and VISExit is not
executed, thus leaving the fprs register in an indeterminate state,
but often with fprs.FPRS_FEF set and one or more dirty bits. This
results in a return to user space with invalid values in the FP regs,
and since fprs.FPRS_FEF is on, no lazy restore occurs.
This bug affects copy_to_user() and copy_from_user() for NG4, NG2,
U3, and U1. All are fixed by using a new exception handler for those
loads and stores that are done during the time between VISEnter and
VISExit.
n.b. In NG4memcpy, the problematic code can be triggered by a copy
size greater than 128 bytes and an unaligned source address. This bug
is known to be the cause of random user process memory corruptions
while perf is running with the callgraph option (ie, perf record -g).
This occurs because perf uses copy_from_user() to read user stacks,
and may fault when it follows a stack frame pointer off to an
invalid page. Validation checks on the stack address just obscure
the underlying problem.
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-12-22 23:24:49 -07:00
# ifndef E X _ L D _ F P
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# define E X _ L D _ F P ( x ,y ) x
sparc64: fix FP corruption in user copy functions
Short story: Exception handlers used by some copy_to_user() and
copy_from_user() functions do not diligently clean up floating point
register usage, and this can result in a user process seeing invalid
values in floating point registers. This sometimes makes the process
fail.
Long story: Several cpu-specific (NG4, NG2, U1, U3) memcpy functions
use floating point registers and VIS alignaddr/faligndata to
accelerate data copying when source and dest addresses don't align
well. Linux uses a lazy scheme for saving floating point registers; It
is not done upon entering the kernel since it's a very expensive
operation. Rather, it is done only when needed. If the kernel ends up
not using FP regs during the course of some trap or system call, then
it can return to user space without saving or restoring them.
The various memcpy functions begin their FP code with VISEntry (or a
variation thereof), which saves the FP regs. They conclude their FP
code with VISExit (or a variation) which essentially marks the FP regs
"clean", ie, they contain no unsaved values. fprs.FPRS_FEF is turned
off so that a lazy restore will be triggered when/if the user process
accesses floating point regs again.
The bug is that the user copy variants of memcpy, copy_from_user() and
copy_to_user(), employ an exception handling mechanism to detect faults
when accessing user space addresses, and when this handler is invoked,
an immediate return from the function is forced, and VISExit is not
executed, thus leaving the fprs register in an indeterminate state,
but often with fprs.FPRS_FEF set and one or more dirty bits. This
results in a return to user space with invalid values in the FP regs,
and since fprs.FPRS_FEF is on, no lazy restore occurs.
This bug affects copy_to_user() and copy_from_user() for NG4, NG2,
U3, and U1. All are fixed by using a new exception handler for those
loads and stores that are done during the time between VISEnter and
VISExit.
n.b. In NG4memcpy, the problematic code can be triggered by a copy
size greater than 128 bytes and an unaligned source address. This bug
is known to be the cause of random user process memory corruptions
while perf is running with the callgraph option (ie, perf record -g).
This occurs because perf uses copy_from_user() to read user stacks,
and may fault when it follows a stack frame pointer off to an
invalid page. Validation checks on the stack address just obscure
the underlying problem.
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-12-22 23:24:49 -07:00
# endif
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# ifndef E X _ S T
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# define E X _ S T ( x ,y ) x
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# endif
sparc64: fix FP corruption in user copy functions
Short story: Exception handlers used by some copy_to_user() and
copy_from_user() functions do not diligently clean up floating point
register usage, and this can result in a user process seeing invalid
values in floating point registers. This sometimes makes the process
fail.
Long story: Several cpu-specific (NG4, NG2, U1, U3) memcpy functions
use floating point registers and VIS alignaddr/faligndata to
accelerate data copying when source and dest addresses don't align
well. Linux uses a lazy scheme for saving floating point registers; It
is not done upon entering the kernel since it's a very expensive
operation. Rather, it is done only when needed. If the kernel ends up
not using FP regs during the course of some trap or system call, then
it can return to user space without saving or restoring them.
The various memcpy functions begin their FP code with VISEntry (or a
variation thereof), which saves the FP regs. They conclude their FP
code with VISExit (or a variation) which essentially marks the FP regs
"clean", ie, they contain no unsaved values. fprs.FPRS_FEF is turned
off so that a lazy restore will be triggered when/if the user process
accesses floating point regs again.
The bug is that the user copy variants of memcpy, copy_from_user() and
copy_to_user(), employ an exception handling mechanism to detect faults
when accessing user space addresses, and when this handler is invoked,
an immediate return from the function is forced, and VISExit is not
executed, thus leaving the fprs register in an indeterminate state,
but often with fprs.FPRS_FEF set and one or more dirty bits. This
results in a return to user space with invalid values in the FP regs,
and since fprs.FPRS_FEF is on, no lazy restore occurs.
This bug affects copy_to_user() and copy_from_user() for NG4, NG2,
U3, and U1. All are fixed by using a new exception handler for those
loads and stores that are done during the time between VISEnter and
VISExit.
n.b. In NG4memcpy, the problematic code can be triggered by a copy
size greater than 128 bytes and an unaligned source address. This bug
is known to be the cause of random user process memory corruptions
while perf is running with the callgraph option (ie, perf record -g).
This occurs because perf uses copy_from_user() to read user stacks,
and may fault when it follows a stack frame pointer off to an
invalid page. Validation checks on the stack address just obscure
the underlying problem.
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-12-22 23:24:49 -07:00
# ifndef E X _ S T _ F P
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# define E X _ S T _ F P ( x ,y ) x
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# endif
# ifndef L O A D
# define L O A D ( t y p e ,a d d r ,d e s t ) t y p e [ a d d r ] , d e s t
# endif
# ifndef L O A D _ B L K
# define L O A D _ B L K ( a d d r ,d e s t ) l d d a [ a d d r ] A S I _ B L K _ P , d e s t
# endif
# ifndef S T O R E
# ifndef M E M C P Y _ D E B U G
# define S T O R E ( t y p e ,s r c ,a d d r ) t y p e s r c , [ a d d r ]
# else
# define S T O R E ( t y p e ,s r c ,a d d r ) t y p e ## a s r c , [ a d d r ] 0x80
# endif
# endif
# ifndef S T O R E _ B L K
# define S T O R E _ B L K ( s r c ,a d d r ) s t d a s r c , [ a d d r ] A S I _ B L K _ P
# endif
# ifndef S T O R E _ I N I T
# define S T O R E _ I N I T ( s r c ,a d d r ) s t x a s r c , [ a d d r ] S T O R E _ A S I
# endif
# ifndef F U N C _ N A M E
# define F U N C _ N A M E N G 2 m e m c p y
# endif
# ifndef P R E A M B L E
# define P R E A M B L E
# endif
# ifndef X C C
# define X C C x c c
# endif
# define F R E G _ F R O B ( x0 , x1 , x2 , x3 , x4 , x5 , x6 , x7 , x8 ) \
faligndata % x0 , % x1 , % f0 ; \
faligndata % x1 , % x2 , % f2 ; \
faligndata % x2 , % x3 , % f4 ; \
faligndata % x3 , % x4 , % f6 ; \
faligndata % x4 , % x5 , % f8 ; \
faligndata % x5 , % x6 , % f10 ; \
faligndata % x6 , % x7 , % f12 ; \
faligndata % x7 , % x8 , % f14 ;
# define F R E G _ M O V E _ 1 ( x0 ) \
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fsrc2 % x0 , % f0 ;
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# define F R E G _ M O V E _ 2 ( x0 , x1 ) \
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fsrc2 % x0 , % f0 ; \
fsrc2 % x1 , % f2 ;
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# define F R E G _ M O V E _ 3 ( x0 , x1 , x2 ) \
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fsrc2 % x0 , % f0 ; \
fsrc2 % x1 , % f2 ; \
fsrc2 % x2 , % f4 ;
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# define F R E G _ M O V E _ 4 ( x0 , x1 , x2 , x3 ) \
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fsrc2 % x0 , % f0 ; \
fsrc2 % x1 , % f2 ; \
fsrc2 % x2 , % f4 ; \
fsrc2 % x3 , % f6 ;
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# define F R E G _ M O V E _ 5 ( x0 , x1 , x2 , x3 , x4 ) \
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fsrc2 % x0 , % f0 ; \
fsrc2 % x1 , % f2 ; \
fsrc2 % x2 , % f4 ; \
fsrc2 % x3 , % f6 ; \
fsrc2 % x4 , % f8 ;
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# define F R E G _ M O V E _ 6 ( x0 , x1 , x2 , x3 , x4 , x5 ) \
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fsrc2 % x0 , % f0 ; \
fsrc2 % x1 , % f2 ; \
fsrc2 % x2 , % f4 ; \
fsrc2 % x3 , % f6 ; \
fsrc2 % x4 , % f8 ; \
fsrc2 % x5 , % f10 ;
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# define F R E G _ M O V E _ 7 ( x0 , x1 , x2 , x3 , x4 , x5 , x6 ) \
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fsrc2 % x0 , % f0 ; \
fsrc2 % x1 , % f2 ; \
fsrc2 % x2 , % f4 ; \
fsrc2 % x3 , % f6 ; \
fsrc2 % x4 , % f8 ; \
fsrc2 % x5 , % f10 ; \
fsrc2 % x6 , % f12 ;
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# define F R E G _ M O V E _ 8 ( x0 , x1 , x2 , x3 , x4 , x5 , x6 , x7 ) \
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fsrc2 % x0 , % f0 ; \
fsrc2 % x1 , % f2 ; \
fsrc2 % x2 , % f4 ; \
fsrc2 % x3 , % f6 ; \
fsrc2 % x4 , % f8 ; \
fsrc2 % x5 , % f10 ; \
fsrc2 % x6 , % f12 ; \
fsrc2 % x7 , % f14 ;
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# define F R E G _ L O A D _ 1 ( b a s e , x0 ) \
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EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x00 , % x0 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
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# define F R E G _ L O A D _ 2 ( b a s e , x0 , x1 ) \
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EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x00 , % x0 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x08 , % x1 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ;
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# define F R E G _ L O A D _ 3 ( b a s e , x0 , x1 , x2 ) \
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EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x00 , % x0 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x08 , % x1 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x10 , % x2 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ;
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# define F R E G _ L O A D _ 4 ( b a s e , x0 , x1 , x2 , x3 ) \
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EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x00 , % x0 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x08 , % x1 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x10 , % x2 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x18 , % x3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ;
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# define F R E G _ L O A D _ 5 ( b a s e , x0 , x1 , x2 , x3 , x4 ) \
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EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x00 , % x0 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x08 , % x1 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x10 , % x2 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x18 , % x3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x20 , % x4 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ;
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# define F R E G _ L O A D _ 6 ( b a s e , x0 , x1 , x2 , x3 , x4 , x5 ) \
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EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x00 , % x0 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x08 , % x1 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x10 , % x2 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x18 , % x3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x20 , % x4 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x28 , % x5 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ;
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# define F R E G _ L O A D _ 7 ( b a s e , x0 , x1 , x2 , x3 , x4 , x5 , x6 ) \
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EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x00 , % x0 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x08 , % x1 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x10 , % x2 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x18 , % x3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x20 , % x4 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x28 , % x5 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ; \
EX_ L D _ F P ( L O A D ( l d d , b a s e + 0 x30 , % x6 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 ) ;
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.register % g2 ,#s c r a t c h
.register % g3 ,#s c r a t c h
.text
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# ifndef E X _ R E T V A L
# define E X _ R E T V A L ( x ) x
__restore_fp :
VISExitHalf
__restore_asi :
retl
wr % g 0 , A S I _ A I U S , % a s i
ENTRY( N G 2 _ r e t l _ o 2 )
ba,p t % x c c , _ _ r e s t o r e _ a s i
mov % o 2 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 )
ENTRY( N G 2 _ r e t l _ o 2 _ p l u s _ 1 )
ba,p t % x c c , _ _ r e s t o r e _ a s i
add % o 2 , 1 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ p l u s _ 1 )
ENTRY( N G 2 _ r e t l _ o 2 _ p l u s _ 4 )
ba,p t % x c c , _ _ r e s t o r e _ a s i
add % o 2 , 4 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ p l u s _ 4 )
ENTRY( N G 2 _ r e t l _ o 2 _ p l u s _ 8 )
ba,p t % x c c , _ _ r e s t o r e _ a s i
add % o 2 , 8 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ p l u s _ 8 )
ENTRY( N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 1 )
add % o 4 , 1 , % o 4
ba,p t % x c c , _ _ r e s t o r e _ a s i
add % o 2 , % o 4 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 1 )
ENTRY( N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 8 )
add % o 4 , 8 , % o 4
ba,p t % x c c , _ _ r e s t o r e _ a s i
add % o 2 , % o 4 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 8 )
ENTRY( N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 1 6 )
add % o 4 , 1 6 , % o 4
ba,p t % x c c , _ _ r e s t o r e _ a s i
add % o 2 , % o 4 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 1 6 )
ENTRY( N G 2 _ r e t l _ o 2 _ p l u s _ g 1 _ f p )
ba,p t % x c c , _ _ r e s t o r e _ f p
add % o 2 , % g 1 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ p l u s _ g 1 _ f p )
ENTRY( N G 2 _ r e t l _ o 2 _ p l u s _ g 1 _ p l u s _ 6 4 _ f p )
add % g 1 , 6 4 , % g 1
ba,p t % x c c , _ _ r e s t o r e _ f p
add % o 2 , % g 1 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ p l u s _ g 1 _ p l u s _ 6 4 _ f p )
ENTRY( N G 2 _ r e t l _ o 2 _ p l u s _ g 1 _ p l u s _ 1 )
add % g 1 , 1 , % g 1
ba,p t % x c c , _ _ r e s t o r e _ a s i
add % o 2 , % g 1 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ p l u s _ g 1 _ p l u s _ 1 )
ENTRY( N G 2 _ r e t l _ o 2 _ a n d _ 7 _ p l u s _ o 4 )
and % o 2 , 7 , % o 2
ba,p t % x c c , _ _ r e s t o r e _ a s i
add % o 2 , % o 4 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ a n d _ 7 _ p l u s _ o 4 )
ENTRY( N G 2 _ r e t l _ o 2 _ a n d _ 7 _ p l u s _ o 4 _ p l u s _ 8 )
and % o 2 , 7 , % o 2
add % o 4 , 8 , % o 4
ba,p t % x c c , _ _ r e s t o r e _ a s i
add % o 2 , % o 4 , % o 0
ENDPROC( N G 2 _ r e t l _ o 2 _ a n d _ 7 _ p l u s _ o 4 _ p l u s _ 8 )
# endif
2007-08-16 01:47:25 -07:00
.align 64
.globl FUNC_NAME
.type _ N A M E ,#f u n c t i o n
FUNC_NAME : /* %o0=dst, %o1=src, %o2=len */
srlx % o 2 , 3 1 , % g 2
cmp % g 2 , 0
tne % x c c , 5
PREAMBLE
2012-09-27 01:06:43 -07:00
mov % o 0 , % o 3
2007-08-16 01:47:25 -07:00
cmp % o 2 , 0
be,p n % X C C , 8 5 f
2012-09-27 01:06:43 -07:00
or % o 0 , % o 1 , G L O B A L _ S P A R E
2007-08-16 01:47:25 -07:00
cmp % o 2 , 1 6
blu,a ,p n % X C C , 8 0 f
2012-09-27 01:06:43 -07:00
or G L O B A L _ S P A R E , % o 2 , G L O B A L _ S P A R E
2007-08-16 01:47:25 -07:00
/ * 2 blocks ( 1 2 8 b y t e s ) i s t h e m i n i m u m w e c a n d o t h e b l o c k
* copy w i t h . W e n e e d t o e n s u r e t h a t w e ' l l i t e r a t e a t l e a s t
* once i n t h e b l o c k c o p y l o o p . A t w o r s t w e ' l l n e e d t o a l i g n
* the d e s t i n a t i o n t o a 6 4 - b y t e b o u n d a r y w h i c h c a n c h e w u p
* to ( 6 4 - 1 ) b y t e s f r o m t h e l e n g t h b e f o r e w e p e r f o r m t h e
* block c o p y l o o p .
*
* However, t h e c u t - o f f p o i n t , p e r f o r m a n c e w i s e , i s a r o u n d
* 4 6 4 - byte b l o c k s .
* /
cmp % o 2 , ( 4 * 6 4 )
blu,p t % X C C , 7 5 f
2012-09-27 01:06:43 -07:00
andcc G L O B A L _ S P A R E , 0 x7 , % g 0
2007-08-16 01:47:25 -07:00
/ * % o0 : dst
* % o1 : src
* % o2 : len ( k n o w n t o b e > = 1 2 8 )
*
* The b l o c k c o p y l o o p s c a n u s e % o 4 , % g 2 , % g 3 a s
* temporaries w h i l e c o p y i n g t h e d a t a . % o 5 m u s t
* be p r e s e r v e d b e t w e e n V I S E n t r y H a l f a n d V I S E x i t H a l f
* /
LOAD( p r e f e t c h , % o 1 + 0 x00 0 , #o n e _ r e a d )
LOAD( p r e f e t c h , % o 1 + 0 x04 0 , #o n e _ r e a d )
LOAD( p r e f e t c h , % o 1 + 0 x08 0 , #o n e _ r e a d )
/* Align destination on 64-byte boundary. */
andcc % o 0 , ( 6 4 - 1 ) , % o 4
be,p t % X C C , 2 f
sub % o 4 , 6 4 , % o 4
sub % g 0 , % o 4 , % o 4 ! b y t e s t o a l i g n d s t
sub % o 2 , % o 4 , % o 2
1 : subcc % o 4 , 1 , % o 4
2016-10-24 20:46:44 -07:00
EX_ L D ( L O A D ( l d u b , % o 1 , % g 1 ) , N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 1 )
EX_ S T ( S T O R E ( s t b , % g 1 , % o 0 ) , N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 1 )
2007-08-16 01:47:25 -07:00
add % o 1 , 1 , % o 1
bne,p t % X C C , 1 b
add % o 0 , 1 , % o 0
2 :
/ * Clobbers o 5 / g 1 / g 2 / g 3 / g 7 / i c c / x c c . W e m u s t p r e s e r v e
* o5 f r o m h e r e u n t i l w e h i t V I S E x i t H a l f .
* /
VISEntryHalf
2014-05-17 11:28:05 -07:00
membar #S y n c
2007-08-16 01:47:25 -07:00
alignaddr % o 1 , % g 0 , % g 0
add % o 1 , ( 6 4 - 1 ) , % o 4
andn % o 4 , ( 6 4 - 1 ) , % o 4
andn % o 2 , ( 6 4 - 1 ) , % g 1
sub % o 2 , % g 1 , % o 2
and % o 1 , ( 6 4 - 1 ) , % g 2
add % o 1 , % g 1 , % o 1
sub % o 0 , % o 4 , % g 3
brz,p t % g 2 , 1 9 0 f
cmp % g 2 , 3 2
blu,a 5 f
cmp % g 2 , 1 6
cmp % g 2 , 4 8
blu,a 4 f
cmp % g 2 , 4 0
cmp % g 2 , 5 6
blu 1 7 0 f
nop
ba,a ,p t % x c c , 1 8 0 f
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
nop
2007-08-16 01:47:25 -07:00
4 : /* 32 <= low bits < 48 */
blu 1 5 0 f
nop
ba,a ,p t % x c c , 1 6 0 f
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
nop
2007-08-16 01:47:25 -07:00
5 : /* 0 < low bits < 32 */
blu,a 6 f
cmp % g 2 , 8
cmp % g 2 , 2 4
blu 1 3 0 f
nop
ba,a ,p t % x c c , 1 4 0 f
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
nop
2007-08-16 01:47:25 -07:00
6 : /* 0 < low bits < 16 */
bgeu 1 2 0 f
nop
/* fall through for 0 < low bits < 8 */
110 : sub % o 4 , 6 4 , % g 2
2016-10-24 20:46:44 -07:00
EX_ L D _ F P ( L O A D _ B L K ( % g 2 , % f0 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
1 : EX_ S T _ F P ( S T O R E _ I N I T ( % g 0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
EX_ L D _ F P ( L O A D _ B L K ( % o 4 , % f16 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ F R O B ( f0 , f2 , f4 , f6 , f8 , f10 , f12 , f14 , f16 )
2016-10-24 20:46:44 -07:00
EX_ S T _ F P ( S T O R E _ B L K ( % f0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ M O V E _ 8 ( f16 , f18 , f20 , f22 , f24 , f26 , f28 , f30 )
subcc % g 1 , 6 4 , % g 1
add % o 4 , 6 4 , % o 4
bne,p t % x c c , 1 b
LOAD( p r e f e t c h , % o 4 + 6 4 , #o n e _ r e a d )
ba,p t % x c c , 1 9 5 f
nop
120 : sub % o 4 , 5 6 , % g 2
FREG_ L O A D _ 7 ( % g 2 , f0 , f2 , f4 , f6 , f8 , f10 , f12 )
2016-10-24 20:46:44 -07:00
1 : EX_ S T _ F P ( S T O R E _ I N I T ( % g 0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
EX_ L D _ F P ( L O A D _ B L K ( % o 4 , % f16 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ F R O B ( f0 , f2 , f4 , f6 , f8 , f10 , f12 , f16 , f18 )
2016-10-24 20:46:44 -07:00
EX_ S T _ F P ( S T O R E _ B L K ( % f0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ M O V E _ 7 ( f18 , f20 , f22 , f24 , f26 , f28 , f30 )
subcc % g 1 , 6 4 , % g 1
add % o 4 , 6 4 , % o 4
bne,p t % x c c , 1 b
LOAD( p r e f e t c h , % o 4 + 6 4 , #o n e _ r e a d )
ba,p t % x c c , 1 9 5 f
nop
130 : sub % o 4 , 4 8 , % g 2
FREG_ L O A D _ 6 ( % g 2 , f0 , f2 , f4 , f6 , f8 , f10 )
2016-10-24 20:46:44 -07:00
1 : EX_ S T _ F P ( S T O R E _ I N I T ( % g 0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
EX_ L D _ F P ( L O A D _ B L K ( % o 4 , % f16 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ F R O B ( f0 , f2 , f4 , f6 , f8 , f10 , f16 , f18 , f20 )
2016-10-24 20:46:44 -07:00
EX_ S T _ F P ( S T O R E _ B L K ( % f0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ M O V E _ 6 ( f20 , f22 , f24 , f26 , f28 , f30 )
subcc % g 1 , 6 4 , % g 1
add % o 4 , 6 4 , % o 4
bne,p t % x c c , 1 b
LOAD( p r e f e t c h , % o 4 + 6 4 , #o n e _ r e a d )
ba,p t % x c c , 1 9 5 f
nop
140 : sub % o 4 , 4 0 , % g 2
FREG_ L O A D _ 5 ( % g 2 , f0 , f2 , f4 , f6 , f8 )
2016-10-24 20:46:44 -07:00
1 : EX_ S T _ F P ( S T O R E _ I N I T ( % g 0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
EX_ L D _ F P ( L O A D _ B L K ( % o 4 , % f16 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ F R O B ( f0 , f2 , f4 , f6 , f8 , f16 , f18 , f20 , f22 )
2016-10-24 20:46:44 -07:00
EX_ S T _ F P ( S T O R E _ B L K ( % f0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ M O V E _ 5 ( f22 , f24 , f26 , f28 , f30 )
subcc % g 1 , 6 4 , % g 1
add % o 4 , 6 4 , % o 4
bne,p t % x c c , 1 b
LOAD( p r e f e t c h , % o 4 + 6 4 , #o n e _ r e a d )
ba,p t % x c c , 1 9 5 f
nop
150 : sub % o 4 , 3 2 , % g 2
FREG_ L O A D _ 4 ( % g 2 , f0 , f2 , f4 , f6 )
2016-10-24 20:46:44 -07:00
1 : EX_ S T _ F P ( S T O R E _ I N I T ( % g 0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
EX_ L D _ F P ( L O A D _ B L K ( % o 4 , % f16 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ F R O B ( f0 , f2 , f4 , f6 , f16 , f18 , f20 , f22 , f24 )
2016-10-24 20:46:44 -07:00
EX_ S T _ F P ( S T O R E _ B L K ( % f0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ M O V E _ 4 ( f24 , f26 , f28 , f30 )
subcc % g 1 , 6 4 , % g 1
add % o 4 , 6 4 , % o 4
bne,p t % x c c , 1 b
LOAD( p r e f e t c h , % o 4 + 6 4 , #o n e _ r e a d )
ba,p t % x c c , 1 9 5 f
nop
160 : sub % o 4 , 2 4 , % g 2
FREG_ L O A D _ 3 ( % g 2 , f0 , f2 , f4 )
2016-10-24 20:46:44 -07:00
1 : EX_ S T _ F P ( S T O R E _ I N I T ( % g 0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
EX_ L D _ F P ( L O A D _ B L K ( % o 4 , % f16 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ F R O B ( f0 , f2 , f4 , f16 , f18 , f20 , f22 , f24 , f26 )
2016-10-24 20:46:44 -07:00
EX_ S T _ F P ( S T O R E _ B L K ( % f0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ M O V E _ 3 ( f26 , f28 , f30 )
subcc % g 1 , 6 4 , % g 1
add % o 4 , 6 4 , % o 4
bne,p t % x c c , 1 b
LOAD( p r e f e t c h , % o 4 + 6 4 , #o n e _ r e a d )
ba,p t % x c c , 1 9 5 f
nop
170 : sub % o 4 , 1 6 , % g 2
FREG_ L O A D _ 2 ( % g 2 , f0 , f2 )
2016-10-24 20:46:44 -07:00
1 : EX_ S T _ F P ( S T O R E _ I N I T ( % g 0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
EX_ L D _ F P ( L O A D _ B L K ( % o 4 , % f16 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ F R O B ( f0 , f2 , f16 , f18 , f20 , f22 , f24 , f26 , f28 )
2016-10-24 20:46:44 -07:00
EX_ S T _ F P ( S T O R E _ B L K ( % f0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ M O V E _ 2 ( f28 , f30 )
subcc % g 1 , 6 4 , % g 1
add % o 4 , 6 4 , % o 4
bne,p t % x c c , 1 b
LOAD( p r e f e t c h , % o 4 + 6 4 , #o n e _ r e a d )
ba,p t % x c c , 1 9 5 f
nop
180 : sub % o 4 , 8 , % g 2
FREG_ L O A D _ 1 ( % g 2 , f0 )
2016-10-24 20:46:44 -07:00
1 : EX_ S T _ F P ( S T O R E _ I N I T ( % g 0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
EX_ L D _ F P ( L O A D _ B L K ( % o 4 , % f16 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ F R O B ( f0 , f16 , f18 , f20 , f22 , f24 , f26 , f28 , f30 )
2016-10-24 20:46:44 -07:00
EX_ S T _ F P ( S T O R E _ B L K ( % f0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
FREG_ M O V E _ 1 ( f30 )
subcc % g 1 , 6 4 , % g 1
add % o 4 , 6 4 , % o 4
bne,p t % x c c , 1 b
LOAD( p r e f e t c h , % o 4 + 6 4 , #o n e _ r e a d )
ba,p t % x c c , 1 9 5 f
nop
190 :
2016-10-24 20:46:44 -07:00
1 : EX_ S T _ F P ( S T O R E _ I N I T ( % g 0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 )
2007-08-16 01:47:25 -07:00
subcc % g 1 , 6 4 , % g 1
2016-10-24 20:46:44 -07:00
EX_ L D _ F P ( L O A D _ B L K ( % o 4 , % f0 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 _ p l u s _ 6 4 )
EX_ S T _ F P ( S T O R E _ B L K ( % f0 , % o 4 + % g 3 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 _ p l u s _ 6 4 )
2007-08-16 01:47:25 -07:00
add % o 4 , 6 4 , % o 4
bne,p t % x c c , 1 b
LOAD( p r e f e t c h , % o 4 + 6 4 , #o n e _ r e a d )
195 :
add % o 4 , % g 3 , % o 0
membar #S y n c
VISExitHalf
/ * % o2 c o n t a i n s a n y f i n a l b y t e s s t i l l n e e d e d t o b e c o p i e d
* over. I f a n y t h i n g i s l e f t , w e c o p y i t o n e b y t e a t a t i m e .
* /
brz,p t % o 2 , 8 5 f
2012-09-27 01:06:43 -07:00
sub % o 0 , % o 1 , G L O B A L _ S P A R E
2007-08-16 01:47:25 -07:00
ba,a ,p t % X C C , 9 0 f
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
nop
2007-08-16 01:47:25 -07:00
.align 64
75 : /* 16 < len <= 64 */
bne,p n % X C C , 7 5 f
2012-09-27 01:06:43 -07:00
sub % o 0 , % o 1 , G L O B A L _ S P A R E
2007-08-16 01:47:25 -07:00
72 :
andn % o 2 , 0 x f , % o 4
and % o 2 , 0 x f , % o 2
1 : subcc % o 4 , 0 x10 , % o 4
2016-10-24 20:46:44 -07:00
EX_ L D ( L O A D ( l d x , % o 1 , % o 5 ) , N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 1 6 )
2007-08-16 01:47:25 -07:00
add % o 1 , 0 x08 , % o 1
2016-10-24 20:46:44 -07:00
EX_ L D ( L O A D ( l d x , % o 1 , % g 1 ) , N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 1 6 )
2007-08-16 01:47:25 -07:00
sub % o 1 , 0 x08 , % o 1
2016-10-24 20:46:44 -07:00
EX_ S T ( S T O R E ( s t x , % o 5 , % o 1 + G L O B A L _ S P A R E ) , N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 1 6 )
2007-08-16 01:47:25 -07:00
add % o 1 , 0 x8 , % o 1
2016-10-24 20:46:44 -07:00
EX_ S T ( S T O R E ( s t x , % g 1 , % o 1 + G L O B A L _ S P A R E ) , N G 2 _ r e t l _ o 2 _ p l u s _ o 4 _ p l u s _ 8 )
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bgu,p t % X C C , 1 b
add % o 1 , 0 x8 , % o 1
73 : andcc % o 2 , 0 x8 , % g 0
be,p t % X C C , 1 f
nop
sub % o 2 , 0 x8 , % o 2
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EX_ L D ( L O A D ( l d x , % o 1 , % o 5 ) , N G 2 _ r e t l _ o 2 _ p l u s _ 8 )
EX_ S T ( S T O R E ( s t x , % o 5 , % o 1 + G L O B A L _ S P A R E ) , N G 2 _ r e t l _ o 2 _ p l u s _ 8 )
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add % o 1 , 0 x8 , % o 1
1 : andcc % o 2 , 0 x4 , % g 0
be,p t % X C C , 1 f
nop
sub % o 2 , 0 x4 , % o 2
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EX_ L D ( L O A D ( l d u w , % o 1 , % o 5 ) , N G 2 _ r e t l _ o 2 _ p l u s _ 4 )
EX_ S T ( S T O R E ( s t w , % o 5 , % o 1 + G L O B A L _ S P A R E ) , N G 2 _ r e t l _ o 2 _ p l u s _ 4 )
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add % o 1 , 0 x4 , % o 1
1 : cmp % o 2 , 0
be,p t % X C C , 8 5 f
nop
ba,p t % x c c , 9 0 f
nop
75 :
andcc % o 0 , 0 x7 , % g 1
sub % g 1 , 0 x8 , % g 1
be,p n % i c c , 2 f
sub % g 0 , % g 1 , % g 1
sub % o 2 , % g 1 , % o 2
1 : subcc % g 1 , 1 , % g 1
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EX_ L D ( L O A D ( l d u b , % o 1 , % o 5 ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 _ p l u s _ 1 )
EX_ S T ( S T O R E ( s t b , % o 5 , % o 1 + G L O B A L _ S P A R E ) , N G 2 _ r e t l _ o 2 _ p l u s _ g 1 _ p l u s _ 1 )
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bgu,p t % i c c , 1 b
add % o 1 , 1 , % o 1
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2 : add % o 1 , G L O B A L _ S P A R E , % o 0
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andcc % o 1 , 0 x7 , % g 1
bne,p t % i c c , 8 f
sll % g 1 , 3 , % g 1
cmp % o 2 , 1 6
bgeu,p t % i c c , 7 2 b
nop
ba,a ,p t % x c c , 7 3 b
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8 : mov 6 4 , G L O B A L _ S P A R E
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andn % o 1 , 0 x7 , % o 1
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EX_ L D ( L O A D ( l d x , % o 1 , % g 2 ) , N G 2 _ r e t l _ o 2 )
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sub G L O B A L _ S P A R E , % g 1 , G L O B A L _ S P A R E
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andn % o 2 , 0 x7 , % o 4
sllx % g 2 , % g 1 , % g 2
1 : add % o 1 , 0 x8 , % o 1
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EX_ L D ( L O A D ( l d x , % o 1 , % g 3 ) , N G 2 _ r e t l _ o 2 _ a n d _ 7 _ p l u s _ o 4 )
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subcc % o 4 , 0 x8 , % o 4
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srlx % g 3 , G L O B A L _ S P A R E , % o 5
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or % o 5 , % g 2 , % o 5
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EX_ S T ( S T O R E ( s t x , % o 5 , % o 0 ) , N G 2 _ r e t l _ o 2 _ a n d _ 7 _ p l u s _ o 4 _ p l u s _ 8 )
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add % o 0 , 0 x8 , % o 0
bgu,p t % i c c , 1 b
sllx % g 3 , % g 1 , % g 2
srl % g 1 , 3 , % g 1
andcc % o 2 , 0 x7 , % o 2
be,p n % i c c , 8 5 f
add % o 1 , % g 1 , % o 1
ba,p t % x c c , 9 0 f
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sub % o 0 , % o 1 , G L O B A L _ S P A R E
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.align 64
80 : /* 0 < len <= 16 */
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andcc G L O B A L _ S P A R E , 0 x3 , % g 0
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bne,p n % X C C , 9 0 f
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sub % o 0 , % o 1 , G L O B A L _ S P A R E
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1 :
subcc % o 2 , 4 , % o 2
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EX_ L D ( L O A D ( l d u w , % o 1 , % g 1 ) , N G 2 _ r e t l _ o 2 _ p l u s _ 4 )
EX_ S T ( S T O R E ( s t w , % g 1 , % o 1 + G L O B A L _ S P A R E ) , N G 2 _ r e t l _ o 2 _ p l u s _ 4 )
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bgu,p t % X C C , 1 b
add % o 1 , 4 , % o 1
85 : retl
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mov E X _ R E T V A L ( % o 3 ) , % o 0
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.align 32
90 :
subcc % o 2 , 1 , % o 2
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EX_ L D ( L O A D ( l d u b , % o 1 , % g 1 ) , N G 2 _ r e t l _ o 2 _ p l u s _ 1 )
EX_ S T ( S T O R E ( s t b , % g 1 , % o 1 + G L O B A L _ S P A R E ) , N G 2 _ r e t l _ o 2 _ p l u s _ 1 )
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bgu,p t % X C C , 9 0 b
add % o 1 , 1 , % o 1
retl
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mov E X _ R E T V A L ( % o 3 ) , % o 0
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.size _ N A M E , . - F U N C _ N A M E
