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/ * atomic. S : T h e s e t h i n g s a r e t o o b i g t o d o i n l i n e .
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*
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* Copyright ( C ) 1 9 9 9 , 2 0 0 7 D a v i d S . M i l l e r ( d a v e m @davemloft.net)
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* /
# include < a s m / a s i . h >
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# include < a s m / b a c k o f f . h >
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.text
/ * Two v e r s i o n s o f t h e a t o m i c r o u t i n e s , o n e t h a t
* does n o t r e t u r n a v a l u e a n d d o e s n o t p e r f o r m
* memory b a r r i e r s , a n d a s e c o n d w h i c h r e t u r n s
* a v a l u e a n d d o e s t h e b a r r i e r s .
* /
.globl atomic_add
.type atomic_ a d d ,#f u n c t i o n
atomic_add : /* %o0 = increment, %o1 = atomic_ptr */
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BACKOFF_ S E T U P ( % o 2 )
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1 : lduw [ % o 1 ] , % g 1
add % g 1 , % o 0 , % g 7
cas [ % o 1 ] , % g 1 , % g 7
cmp % g 1 , % g 7
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bne,p n % i c c , 2 f
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nop
retl
nop
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2 : BACKOFF_ S P I N ( % o 2 , % o 3 , 1 b )
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.size atomic_ a d d , . - a t o m i c _ a d d
.globl atomic_sub
.type atomic_ s u b ,#f u n c t i o n
atomic_sub : /* %o0 = decrement, %o1 = atomic_ptr */
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BACKOFF_ S E T U P ( % o 2 )
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1 : lduw [ % o 1 ] , % g 1
sub % g 1 , % o 0 , % g 7
cas [ % o 1 ] , % g 1 , % g 7
cmp % g 1 , % g 7
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bne,p n % i c c , 2 f
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nop
retl
nop
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2 : BACKOFF_ S P I N ( % o 2 , % o 3 , 1 b )
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.size atomic_ s u b , . - a t o m i c _ s u b
.globl atomic_add_ret
.type atomic_ a d d _ r e t ,#f u n c t i o n
atomic_add_ret : /* %o0 = increment, %o1 = atomic_ptr */
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BACKOFF_ S E T U P ( % o 2 )
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1 : lduw [ % o 1 ] , % g 1
add % g 1 , % o 0 , % g 7
cas [ % o 1 ] , % g 1 , % g 7
cmp % g 1 , % g 7
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bne,p n % i c c , 2 f
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add % g 7 , % o 0 , % g 7
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
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sra % g 7 , 0 , % o 0
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retl
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
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nop
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2 : BACKOFF_ S P I N ( % o 2 , % o 3 , 1 b )
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.size atomic_ a d d _ r e t , . - a t o m i c _ a d d _ r e t
.globl atomic_sub_ret
.type atomic_ s u b _ r e t ,#f u n c t i o n
atomic_sub_ret : /* %o0 = decrement, %o1 = atomic_ptr */
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BACKOFF_ S E T U P ( % o 2 )
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1 : lduw [ % o 1 ] , % g 1
sub % g 1 , % o 0 , % g 7
cas [ % o 1 ] , % g 1 , % g 7
cmp % g 1 , % g 7
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bne,p n % i c c , 2 f
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sub % g 7 , % o 0 , % g 7
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
sra % g 7 , 0 , % o 0
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retl
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
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nop
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2 : BACKOFF_ S P I N ( % o 2 , % o 3 , 1 b )
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.size atomic_ s u b _ r e t , . - a t o m i c _ s u b _ r e t
.globl atomic64_add
.type atomic6 4 _ a d d ,#f u n c t i o n
atomic64_add : /* %o0 = increment, %o1 = atomic_ptr */
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BACKOFF_ S E T U P ( % o 2 )
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1 : ldx [ % o 1 ] , % g 1
add % g 1 , % o 0 , % g 7
casx [ % o 1 ] , % g 1 , % g 7
cmp % g 1 , % g 7
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bne,p n % x c c , 2 f
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nop
retl
nop
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2 : BACKOFF_ S P I N ( % o 2 , % o 3 , 1 b )
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.size atomic6 4 _ a d d , . - a t o m i c64 _ a d d
.globl atomic64_sub
.type atomic6 4 _ s u b ,#f u n c t i o n
atomic64_sub : /* %o0 = decrement, %o1 = atomic_ptr */
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BACKOFF_ S E T U P ( % o 2 )
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1 : ldx [ % o 1 ] , % g 1
sub % g 1 , % o 0 , % g 7
casx [ % o 1 ] , % g 1 , % g 7
cmp % g 1 , % g 7
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bne,p n % x c c , 2 f
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nop
retl
nop
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2 : BACKOFF_ S P I N ( % o 2 , % o 3 , 1 b )
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.size atomic6 4 _ s u b , . - a t o m i c64 _ s u b
.globl atomic64_add_ret
.type atomic6 4 _ a d d _ r e t ,#f u n c t i o n
atomic64_add_ret : /* %o0 = increment, %o1 = atomic_ptr */
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BACKOFF_ S E T U P ( % o 2 )
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1 : ldx [ % o 1 ] , % g 1
add % g 1 , % o 0 , % g 7
casx [ % o 1 ] , % g 1 , % g 7
cmp % g 1 , % g 7
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bne,p n % x c c , 2 f
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add % g 7 , % o 0 , % g 7
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
mov % g 7 , % o 0
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retl
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
nop
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2 : BACKOFF_ S P I N ( % o 2 , % o 3 , 1 b )
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.size atomic6 4 _ a d d _ r e t , . - a t o m i c64 _ a d d _ r e t
.globl atomic64_sub_ret
.type atomic6 4 _ s u b _ r e t ,#f u n c t i o n
atomic64_sub_ret : /* %o0 = decrement, %o1 = atomic_ptr */
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BACKOFF_ S E T U P ( % o 2 )
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1 : ldx [ % o 1 ] , % g 1
sub % g 1 , % o 0 , % g 7
casx [ % o 1 ] , % g 1 , % g 7
cmp % g 1 , % g 7
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bne,p n % x c c , 2 f
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sub % g 7 , % o 0 , % g 7
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
mov % g 7 , % o 0
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retl
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
nop
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2 : BACKOFF_ S P I N ( % o 2 , % o 3 , 1 b )
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.size atomic6 4 _ s u b _ r e t , . - a t o m i c64 _ s u b _ r e t