[PATCH] avr32 architecture
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.
AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density. The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.
The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit. It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.
Full data sheet is available from
http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
Information about the AT32STK1000 development board can be found at
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918
including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.
Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.
This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.
[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-25 23:32:13 -07:00
/*
* Copyright ( C ) 2004 - 2006 Atmel Corporation
*
* ASID handling taken from SH implementation .
* Copyright ( C ) 1999 Niibe Yutaka
* Copyright ( C ) 2003 Paul Mundt
*
* This program is free software ; you can redistribute it and / or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation .
*/
# ifndef __ASM_AVR32_MMU_CONTEXT_H
# define __ASM_AVR32_MMU_CONTEXT_H
# include <asm/tlbflush.h>
# include <asm/sysreg.h>
2007-05-02 19:27:14 +02:00
# include <asm-generic/mm_hooks.h>
[PATCH] avr32 architecture
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.
AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density. The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.
The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit. It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.
Full data sheet is available from
http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from
http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
Information about the AT32STK1000 development board can be found at
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918
including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.
Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.
This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.
[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-25 23:32:13 -07:00
/*
* The MMU " context " consists of two things :
* ( a ) TLB cache version
* ( b ) ASID ( Address Space IDentifier )
*/
# define MMU_CONTEXT_ASID_MASK 0x000000ff
# define MMU_CONTEXT_VERSION_MASK 0xffffff00
# define MMU_CONTEXT_FIRST_VERSION 0x00000100
# define NO_CONTEXT 0
# define MMU_NO_ASID 0x100
/* Virtual Page Number mask */
# define MMU_VPN_MASK 0xfffff000
/* Cache of MMU context last used */
extern unsigned long mmu_context_cache ;
/*
* Get MMU context if needed
*/
static inline void
get_mmu_context ( struct mm_struct * mm )
{
unsigned long mc = mmu_context_cache ;
if ( ( ( mm - > context ^ mc ) & MMU_CONTEXT_VERSION_MASK ) = = 0 )
/* It's up to date, do nothing */
return ;
/* It's old, we need to get new context with new version */
mc = + + mmu_context_cache ;
if ( ! ( mc & MMU_CONTEXT_ASID_MASK ) ) {
/*
* We have exhausted all ASIDs of this version .
* Flush the TLB and start new cycle .
*/
flush_tlb_all ( ) ;
/*
* Fix version . Note that we avoid version # 0
* to distinguish NO_CONTEXT .
*/
if ( ! mc )
mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION ;
}
mm - > context = mc ;
}
/*
* Initialize the context related info for a new mm_struct
* instance .
*/
static inline int init_new_context ( struct task_struct * tsk ,
struct mm_struct * mm )
{
mm - > context = NO_CONTEXT ;
return 0 ;
}
/*
* Destroy context related info for an mm_struct that is about
* to be put to rest .
*/
static inline void destroy_context ( struct mm_struct * mm )
{
/* Do nothing */
}
static inline void set_asid ( unsigned long asid )
{
/* XXX: We're destroying TLBEHI[8:31] */
sysreg_write ( TLBEHI , asid & MMU_CONTEXT_ASID_MASK ) ;
cpu_sync_pipeline ( ) ;
}
static inline unsigned long get_asid ( void )
{
unsigned long asid ;
asid = sysreg_read ( TLBEHI ) ;
return asid & MMU_CONTEXT_ASID_MASK ;
}
static inline void activate_context ( struct mm_struct * mm )
{
get_mmu_context ( mm ) ;
set_asid ( mm - > context & MMU_CONTEXT_ASID_MASK ) ;
}
static inline void switch_mm ( struct mm_struct * prev ,
struct mm_struct * next ,
struct task_struct * tsk )
{
if ( likely ( prev ! = next ) ) {
unsigned long __pgdir = ( unsigned long ) next - > pgd ;
sysreg_write ( PTBR , __pgdir ) ;
activate_context ( next ) ;
}
}
# define deactivate_mm(tsk,mm) do { } while(0)
# define activate_mm(prev, next) switch_mm((prev), (next), NULL)
static inline void
enter_lazy_tlb ( struct mm_struct * mm , struct task_struct * tsk )
{
}
static inline void enable_mmu ( void )
{
sysreg_write ( MMUCR , ( SYSREG_BIT ( MMUCR_S )
| SYSREG_BIT ( E )
| SYSREG_BIT ( MMUCR_I ) ) ) ;
nop ( ) ; nop ( ) ; nop ( ) ; nop ( ) ; nop ( ) ; nop ( ) ; nop ( ) ; nop ( ) ;
if ( mmu_context_cache = = NO_CONTEXT )
mmu_context_cache = MMU_CONTEXT_FIRST_VERSION ;
set_asid ( mmu_context_cache & MMU_CONTEXT_ASID_MASK ) ;
}
static inline void disable_mmu ( void )
{
sysreg_write ( MMUCR , SYSREG_BIT ( MMUCR_S ) ) ;
}
# endif /* __ASM_AVR32_MMU_CONTEXT_H */