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/* SPDX-License-Identifier: GPL-2.0+ */
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/ *
* Copyright ( c ) 2 0 1 3 S a m s u n g E l e c t r o n i c s C o . , L t d .
* http : / / www. s a m s u n g . c o m
*
* Exynos l o w - l e v e l r e s u m e c o d e
* /
# include < l i n u x / l i n k a g e . h >
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# include < a s m / a s m - o f f s e t s . h >
# include < a s m / h a r d w a r e / c a c h e - l 2 x0 . h >
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# include " s m c . h "
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# define C P U _ M A S K 0 x f f0 f f f f0
# define C P U _ C O R T E X _ A 9 0 x41 0 f c09 0
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.text
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.align
/ *
* sleep m a g i c , t o a l l o w t h e b o o t l o a d e r t o c h e c k f o r a n v a l i d
* image t o r e s u m e t o . M u s t b e t h e f i r s t w o r d b e f o r e t h e
* exynos_ c p u _ r e s u m e e n t r y .
* /
.word 0x2bedf00d
/ *
* exynos_ c p u _ r e s u m e
*
* resume c o d e e n t r y f o r b o o t l o a d e r t o c a l l
* /
ENTRY( e x y n o s _ c p u _ r e s u m e )
# ifdef C O N F I G _ C A C H E _ L 2 X 0
mrc p15 , 0 , r0 , c0 , c0 , 0
ldr r1 , =CPU_MASK
and r0 , r0 , r1
ldr r1 , =CPU_CORTEX_A9
cmp r0 , r1
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bleq l 2 c31 0 _ e a r l y _ r e s u m e
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# endif
b c p u _ r e s u m e
ENDPROC( e x y n o s _ c p u _ r e s u m e )
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.align
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.arch armv7 - a
.arch_extension sec
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ENTRY( e x y n o s _ c p u _ r e s u m e _ n s )
mrc p15 , 0 , r0 , c0 , c0 , 0
ldr r1 , =CPU_MASK
and r0 , r0 , r1
ldr r1 , =CPU_CORTEX_A9
cmp r0 , r1
bne s k i p _ c p15
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adr r0 , _ c p15 _ s a v e _ p o w e r
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ldr r1 , [ r0 ]
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ldr r1 , [ r0 , r1 ]
adr r0 , _ c p15 _ s a v e _ d i a g
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ldr r2 , [ r0 ]
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ldr r2 , [ r0 , r2 ]
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mov r0 , #S M C _ C M D _ C 15 R E S U M E
dsb
smc #0
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# ifdef C O N F I G _ C A C H E _ L 2 X 0
adr r0 , 1 f
ldr r2 , [ r0 ]
add r0 , r2 , r0
/* Check that the address has been initialised. */
ldr r1 , [ r0 , #L 2 X 0 _ R _ P H Y _ B A S E ]
teq r1 , #0
beq s k i p _ l 2 x0
/* Check if controller has been enabled. */
ldr r2 , [ r1 , #L 2 X 0 _ C T R L ]
tst r2 , #0x1
bne s k i p _ l 2 x0
ldr r1 , [ r0 , #L 2 X 0 _ R _ T A G _ L A T E N C Y ]
ldr r2 , [ r0 , #L 2 X 0 _ R _ D A T A _ L A T E N C Y ]
ldr r3 , [ r0 , #L 2 X 0 _ R _ P R E F E T C H _ C T R L ]
mov r0 , #S M C _ C M D _ L 2 X 0 S E T U P 1
smc #0
/* Reload saved regs pointer because smc corrupts registers. */
adr r0 , 1 f
ldr r2 , [ r0 ]
add r0 , r2 , r0
ldr r1 , [ r0 , #L 2 X 0 _ R _ P W R _ C T R L ]
ldr r2 , [ r0 , #L 2 X 0 _ R _ A U X _ C T R L ]
mov r0 , #S M C _ C M D _ L 2 X 0 S E T U P 2
smc #0
mov r0 , #S M C _ C M D _ L 2 X 0 I N V A L L
smc #0
mov r1 , #1
mov r0 , #S M C _ C M D _ L 2 X 0 C T R L
smc #0
skip_l2x0 :
# endif / * C O N F I G _ C A C H E _ L 2 X 0 * /
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skip_cp15 :
b c p u _ r e s u m e
ENDPROC( e x y n o s _ c p u _ r e s u m e _ n s )
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.align
_cp15_save_power :
.long cp15_save_power - .
_cp15_save_diag :
.long cp15_save_diag - .
# ifdef C O N F I G _ C A C H E _ L 2 X 0
1 : .long l 2 x0 _ s a v e d _ r e g s - .
# endif / * C O N F I G _ C A C H E _ L 2 X 0 * /
.data
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.align 2
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.globl cp15_save_diag
cp15_save_diag :
.long 0 @ cp15 diagnostic
.globl cp15_save_power
cp15_save_power :
.long 0 @ cp15 power control