2015-07-17 19:33:44 +03:00
i synthesize instructions events
2020-05-30 20:24:41 +08:00
b synthesize branches events (branch misses for Arm SPE)
2015-07-17 19:33:44 +03:00
c synthesize branches events (calls only)
r synthesize branches events (returns only)
x synthesize transactions events
2017-05-26 11:17:24 +03:00
w synthesize ptwrite events
2017-05-26 11:17:25 +03:00
p synthesize power events
2019-08-06 11:46:03 +03:00
o synthesize other events recorded due to the use
of aux-output (refer to perf record)
2015-07-17 19:33:44 +03:00
e synthesize error events
d create a debug log
2020-05-30 20:24:41 +08:00
f synthesize first level cache events
m synthesize last level cache events
t synthesize TLB events
a synthesize remote access events
2015-07-17 19:33:44 +03:00
g synthesize a call chain (use with i or x)
2020-04-01 13:16:05 +03:00
G synthesize a call chain on existing event records
2015-09-25 16:15:39 +03:00
l synthesize last branch entries (use with i or x)
2020-04-29 18:07:46 +03:00
L synthesize last branch entries on existing event records
2016-03-28 10:45:38 -07:00
s skip initial number of events
2020-07-10 18:11:02 +03:00
q quicker (less detailed) decoding
2015-07-17 19:33:44 +03:00
2018-09-20 11:05:37 -07:00
The default is all events i.e. the same as --itrace=ibxwpe,
except for perf script where it is --itrace=ce
2015-07-17 19:33:44 +03:00
2018-09-20 11:05:37 -07:00
In addition, the period (default 100000, except for perf script where it is 1)
for instructions events can be specified in units of:
2015-07-17 19:33:44 +03:00
i instructions
t ticks
ms milliseconds
us microseconds
ns nanoseconds (default)
Also the call chain size (default 16, max. 1024) for instructions or
transactions events can be specified.
2015-09-25 16:15:39 +03:00
Also the number of last branch entries (default 64, max. 1024) for
instructions or transactions events can be specified.
2016-03-28 10:45:38 -07:00
2020-04-29 18:07:50 +03:00
Similar to options g and l, size may also be specified for options G and L.
On x86, note that G and L work poorly when data has been recorded with
large PEBS. Refer linkperf:perf-intel-pt[1] man page for details.
2017-05-26 11:17:24 +03:00
It is also possible to skip events generated (instructions, branches, transactions,
2017-05-26 11:17:25 +03:00
ptwrite, power) at the beginning. This is useful to ignore initialization code.
2016-03-28 10:45:38 -07:00
--itrace=i0nss1000000
skips the first million instructions.
2020-07-10 18:10:57 +03:00
The 'e' option may be followed by flags which affect what errors will or
will not be reported. Each flag must be preceded by either '+' or '-'.
The flags are:
o overflow
l trace data lost
2020-07-10 18:10:59 +03:00
If supported, the 'd' option may be followed by flags which affect what
debug messages will or will not be logged. Each flag must be preceded
by either '+' or '-'. The flags are:
a all perf events
2020-07-10 18:11:02 +03:00
If supported, the 'q' option may be repeated to increase the effect.