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linux/arch/arm/mach-imx/mx31.h

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imx: properly protect mach/mx{1,[25][157x]}.h from multiple inclusion Some headers have used (now) wrong names or havn't had protection at all. This is needed before adding static inline functions to the headers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Magnus Lilja <lilja.magnus@gmail.com> Cc: Holger Schurig <hs4233@mail.mn-solutions.de> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Daniel Mack <daniel@caiaq.de>
2010-01-08 18:02:30 +03:00
#ifndef __MACH_MX31_H__
#define __MACH_MX31_H__
[ARM] 4461/1: MXC platform and i.MX31ADS core support This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-10 01:06:53 +04:00
/*
* IRAM
*/
imx: add namespace prefixes for symbols in mx31.h The old names are still defined using the new names. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-12 23:43:39 +03:00
#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
[ARM] MX35: Add register definitions for the i.MX35 This patch moves the stuff common to i.MX31 and i.MX35 to mx3x.h and the specifics to mx31.h/mx35.h. We can build a kernel which runs on i.MX31 and i.MX35, so always include mx31.h and mx35.h Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-02 16:11:54 +03:00
#define MX31_IRAM_SIZE SZ_16K
[ARM] 4461/1: MXC platform and i.MX31ADS core support This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-10 01:06:53 +04:00
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_L2CC_BASE_ADDR 0x30000000
#define MX31_L2CC_SIZE SZ_1M
[ARM] 4461/1: MXC platform and i.MX31ADS core support This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-10 01:06:53 +04:00
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_AIPS1_BASE_ADDR 0x43f00000
#define MX31_AIPS1_SIZE SZ_1M
#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
ARM: imx: dynamically register imx-i2c devices (imx31) Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2010-06-16 20:03:05 +04:00
#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
ARM: mx3: dynamically allocate fsl-usb2-udc devices While adapting the #defines for this I noticed that the offset used for USB HS on i.MX35 differs from the documented offset. I kept the working offset and commented that the documentation differs. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2010-11-12 18:40:06 +03:00
#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
[ARM] 4461/1: MXC platform and i.MX31ADS core support This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-10 01:06:53 +04:00
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_SPBA0_BASE_ADDR 0x50000000
#define MX31_SPBA0_SIZE SZ_1M
ARM: mx3: dynamically register mxc-mmc devices Compared to the static devices the dynamic have a DMA resource. This should be save as it seems unused in the driver. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2010-11-12 13:10:55 +03:00
#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
[ARM] 4461/1: MXC platform and i.MX31ADS core support This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-10 01:06:53 +04:00
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_AIPS2_BASE_ADDR 0x53f00000
#define MX31_AIPS2_SIZE SZ_1M
#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
[ARM] 4461/1: MXC platform and i.MX31ADS core support This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-10 01:06:53 +04:00
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_ROMP_BASE_ADDR 0x60000000
ARM: imx: use __iomem pointers for MMIO ARM is moving to stricter checks on readl/write functions, so we need to use the correct types everywhere. This found a bug in mach-armadillo5x0.c, where we attempt mmio on the MXC_CCM_RCSR address that is currently defined to 0xc and consequently causes an illegal address access. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Shawn Guo <shawn.guo@linaro.org>
2012-09-15 00:14:01 +04:00
#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000)
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_ROMP_SIZE SZ_1M
#define MX31_AVIC_BASE_ADDR 0x68000000
#define MX31_AVIC_SIZE SZ_1M
#define MX31_IPU_MEM_BASE_ADDR 0x70000000
#define MX31_CSD0_BASE_ADDR 0x80000000
#define MX31_CSD1_BASE_ADDR 0x90000000
#define MX31_CS0_BASE_ADDR 0xa0000000
#define MX31_CS1_BASE_ADDR 0xa8000000
#define MX31_CS2_BASE_ADDR 0xb0000000
#define MX31_CS3_BASE_ADDR 0xb2000000
#define MX31_CS4_BASE_ADDR 0xb4000000
ARM: imx: use __iomem pointers for MMIO ARM is moving to stricter checks on readl/write functions, so we need to use the correct types everywhere. This found a bug in mach-armadillo5x0.c, where we attempt mmio on the MXC_CCM_RCSR address that is currently defined to 0xc and consequently causes an illegal address access. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Shawn Guo <shawn.guo@linaro.org>
2012-09-15 00:14:01 +04:00
#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000)
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_CS4_SIZE SZ_32M
#define MX31_CS5_BASE_ADDR 0xb6000000
ARM: imx: use __iomem pointers for MMIO ARM is moving to stricter checks on readl/write functions, so we need to use the correct types everywhere. This found a bug in mach-armadillo5x0.c, where we attempt mmio on the MXC_CCM_RCSR address that is currently defined to 0xc and consequently causes an illegal address access. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Shawn Guo <shawn.guo@linaro.org>
2012-09-15 00:14:01 +04:00
#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000)
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_CS5_SIZE SZ_32M
#define MX31_X_MEMC_BASE_ADDR 0xb8000000
#define MX31_X_MEMC_SIZE SZ_64K
#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
imx: define functions to configure chip selects in the WEIM This has the addional effect that the macros CSCR_U, CSCR_L and CSCR_A are not used anymore in mach-pcm038.c and mach-qong.c. These still use the deprecated IO_ADDRESS macro and shouldn't be used in new code. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Holger Schurig <hs4233@mail.mn-solutions.de> Cc: Dmitriy Taychenachev <dimichxp@gmail.com>
2010-01-07 13:27:17 +03:00
#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
ARM: imx: change static io mapping to use a function Now only the virtual addresses [0xf4000000, 0xf5ffffff] are used for static per-SoC mappings. The few mappings of whole chip selects are moved accordingly. The now wrong defines for virtual base addresses are removed. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2010-10-25 17:44:25 +04:00
#define MX31_IO_P2V(x) IMX_IO_P2V(x)
ARM: imx: refactor the io mapping macro This makes it more assembler friendly and allows it to be used in situation that need an unsigned long and not a pointer. Also the naming is clearer. IOMEM is introduced without IMX_ prefix as it is used this way in more than one ARM subarch and it might become globally available soon. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2010-10-25 13:40:30 +04:00
#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
imx31: define and use MX31_IO_ADDRESS Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Daniel Mack <daniel@caiaq.de> Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Magnus Lilja <lilja.magnus@gmail.com>
2009-12-16 21:06:12 +03:00
ARM: imx: enable SPARSE_IRQ for imx platform As all irqchips on imx have been changed to allocate their irq_descs, and all unneeded mach/irqs.h inclusions on imx have been cleaned up, now it's time to select SPARSE_IRQ for imx/mxc. The SPARSE_IRQ support forces irqs allocation starting from 16. All those static irq number definition for SoCs need to shift 16 to keep non-DT boot works. With all those static IRQ number and start definitions removed from mach/irqs.h, the header becomes just a container of a couple of mach-imx specific irq/fiq calls. Since mach/irqs.h is not included by asm/irq.h now, the users of mxc_set_irq_fiq needs to explicitly include mach/irqs.h themselves. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-06-14 07:16:14 +04:00
/*
* Interrupt numbers
*/
#include <asm/irq.h>
#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
ARM: mx3: dynamically register mxc-mmc devices Compared to the static devices the dynamic have a DMA resource. This should be save as it seems unused in the driver. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2010-11-12 13:10:55 +03:00
#define MX31_DMA_REQ_SDHC1 20
#define MX31_DMA_REQ_SDHC2 21
ARM: imx: dynamically allocate imx-ssi devices Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2010-08-25 19:37:45 +04:00
#define MX31_DMA_REQ_SSI2_RX1 22
#define MX31_DMA_REQ_SSI2_TX1 23
#define MX31_DMA_REQ_SSI2_RX0 24
#define MX31_DMA_REQ_SSI2_TX0 25
#define MX31_DMA_REQ_SSI1_RX1 26
#define MX31_DMA_REQ_SSI1_TX1 27
#define MX31_DMA_REQ_SSI1_RX0 28
#define MX31_DMA_REQ_SSI1_TX0 29
imx: copy constants from mx3x.h to mx31.h using the appropriate namespace Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2009-11-13 23:24:48 +03:00
#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
imx: properly protect mach/mx{1,[25][157x]}.h from multiple inclusion Some headers have used (now) wrong names or havn't had protection at all. This is needed before adding static inline functions to the headers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Magnus Lilja <lilja.magnus@gmail.com> Cc: Holger Schurig <hs4233@mail.mn-solutions.de> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Daniel Mack <daniel@caiaq.de>
2010-01-08 18:02:30 +03:00
#endif /* ifndef __MACH_MX31_H__ */
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