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/* SPDX-License-Identifier: GPL-2.0 */
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/*
* This file is part of AD5686 DAC driver
*
* Copyright 2018 Analog Devices Inc .
*/
# ifndef __DRIVERS_IIO_DAC_AD5686_H__
# define __DRIVERS_IIO_DAC_AD5686_H__
# include <linux/types.h>
# include <linux/cache.h>
# include <linux/mutex.h>
# include <linux/kernel.h>
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# define AD5310_CMD(x) ((x) << 12)
iio:dac:ad5686: Add AD5681R/AD5682R/AD5683/AD5683R support
The AD5681R/AD5682R/AD5683/AD5683R are a family of one channel DACs with
12-bit, 14-bit and 16-bit precision respectively. The devices have either
no built-in reference, or built-in 2.5V reference.
These devices are similar to AD5691R/AD5692R/AD5693/AD5693R except
with a few notable differences:
* they use the SPI interface instead of I2C
* in the write control register, DB18 and DB17 are used for setting the
power mode, while DB16 is the REF bit. This is why a new regmap type
was defined and checked accordingly.
* the shift register is 24 bits wide, the first four bits are the command
bits followed by the data bits. As the data comprises of 20-bit, 18-bit
or 16-bit input code, this means that 4 LSB bits are don't care. This is
why the data needs to be shifted on the left with four bits. Therefore,
AD5683_REGMAP is checked inside a switch case in the ad5686_spi_write()
function. On the other hand, similar devices such as AD5693R family,
have the 4 MSB command bits followed by 4 don't care bits.
Datasheet:
http://www.analog.com/media/en/technical-documentation/data-sheets/AD5683R_5682R_5681R_5683.pdf
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-05-18 18:23:34 +03:00
# define AD5683_DATA(x) ((x) << 4)
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# define AD5686_ADDR(x) ((x) << 16)
# define AD5686_CMD(x) ((x) << 20)
# define AD5686_ADDR_DAC(chan) (0x1 << (chan))
# define AD5686_ADDR_ALL_DAC 0xF
# define AD5686_CMD_NOOP 0x0
# define AD5686_CMD_WRITE_INPUT_N 0x1
# define AD5686_CMD_UPDATE_DAC_N 0x2
# define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3
# define AD5686_CMD_POWERDOWN_DAC 0x4
# define AD5686_CMD_LDAC_MASK 0x5
# define AD5686_CMD_RESET 0x6
# define AD5686_CMD_INTERNAL_REFER_SETUP 0x7
# define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8
# define AD5686_CMD_READBACK_ENABLE 0x9
# define AD5686_LDAC_PWRDN_NONE 0x0
# define AD5686_LDAC_PWRDN_1K 0x1
# define AD5686_LDAC_PWRDN_100K 0x2
# define AD5686_LDAC_PWRDN_3STATE 0x3
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# define AD5686_CMD_CONTROL_REG 0x4
iio:dac:ad5686: Add AD5681R/AD5682R/AD5683/AD5683R support
The AD5681R/AD5682R/AD5683/AD5683R are a family of one channel DACs with
12-bit, 14-bit and 16-bit precision respectively. The devices have either
no built-in reference, or built-in 2.5V reference.
These devices are similar to AD5691R/AD5692R/AD5693/AD5693R except
with a few notable differences:
* they use the SPI interface instead of I2C
* in the write control register, DB18 and DB17 are used for setting the
power mode, while DB16 is the REF bit. This is why a new regmap type
was defined and checked accordingly.
* the shift register is 24 bits wide, the first four bits are the command
bits followed by the data bits. As the data comprises of 20-bit, 18-bit
or 16-bit input code, this means that 4 LSB bits are don't care. This is
why the data needs to be shifted on the left with four bits. Therefore,
AD5683_REGMAP is checked inside a switch case in the ad5686_spi_write()
function. On the other hand, similar devices such as AD5693R family,
have the 4 MSB command bits followed by 4 don't care bits.
Datasheet:
http://www.analog.com/media/en/technical-documentation/data-sheets/AD5683R_5682R_5681R_5683.pdf
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-05-18 18:23:34 +03:00
# define AD5686_CMD_READBACK_ENABLE_V2 0x5
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# define AD5310_REF_BIT_MSK BIT(8)
iio:dac:ad5686: Add AD5681R/AD5682R/AD5683/AD5683R support
The AD5681R/AD5682R/AD5683/AD5683R are a family of one channel DACs with
12-bit, 14-bit and 16-bit precision respectively. The devices have either
no built-in reference, or built-in 2.5V reference.
These devices are similar to AD5691R/AD5692R/AD5693/AD5693R except
with a few notable differences:
* they use the SPI interface instead of I2C
* in the write control register, DB18 and DB17 are used for setting the
power mode, while DB16 is the REF bit. This is why a new regmap type
was defined and checked accordingly.
* the shift register is 24 bits wide, the first four bits are the command
bits followed by the data bits. As the data comprises of 20-bit, 18-bit
or 16-bit input code, this means that 4 LSB bits are don't care. This is
why the data needs to be shifted on the left with four bits. Therefore,
AD5683_REGMAP is checked inside a switch case in the ad5686_spi_write()
function. On the other hand, similar devices such as AD5693R family,
have the 4 MSB command bits followed by 4 don't care bits.
Datasheet:
http://www.analog.com/media/en/technical-documentation/data-sheets/AD5683R_5682R_5681R_5683.pdf
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-05-18 18:23:34 +03:00
# define AD5683_REF_BIT_MSK BIT(12)
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# define AD5693_REF_BIT_MSK BIT(12)
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/**
* ad5686_supported_device_ids :
*/
enum ad5686_supported_device_ids {
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ID_AD5310R ,
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ID_AD5311R ,
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ID_AD5671R ,
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ID_AD5672R ,
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ID_AD5674R ,
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ID_AD5675R ,
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ID_AD5676 ,
ID_AD5676R ,
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ID_AD5679R ,
iio:dac:ad5686: Add AD5681R/AD5682R/AD5683/AD5683R support
The AD5681R/AD5682R/AD5683/AD5683R are a family of one channel DACs with
12-bit, 14-bit and 16-bit precision respectively. The devices have either
no built-in reference, or built-in 2.5V reference.
These devices are similar to AD5691R/AD5692R/AD5693/AD5693R except
with a few notable differences:
* they use the SPI interface instead of I2C
* in the write control register, DB18 and DB17 are used for setting the
power mode, while DB16 is the REF bit. This is why a new regmap type
was defined and checked accordingly.
* the shift register is 24 bits wide, the first four bits are the command
bits followed by the data bits. As the data comprises of 20-bit, 18-bit
or 16-bit input code, this means that 4 LSB bits are don't care. This is
why the data needs to be shifted on the left with four bits. Therefore,
AD5683_REGMAP is checked inside a switch case in the ad5686_spi_write()
function. On the other hand, similar devices such as AD5693R family,
have the 4 MSB command bits followed by 4 don't care bits.
Datasheet:
http://www.analog.com/media/en/technical-documentation/data-sheets/AD5683R_5682R_5681R_5683.pdf
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-05-18 18:23:34 +03:00
ID_AD5681R ,
ID_AD5682R ,
ID_AD5683 ,
ID_AD5683R ,
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ID_AD5684 ,
ID_AD5684R ,
ID_AD5685R ,
ID_AD5686 ,
ID_AD5686R ,
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ID_AD5691R ,
ID_AD5692R ,
ID_AD5693 ,
ID_AD5693R ,
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ID_AD5694 ,
ID_AD5694R ,
ID_AD5695R ,
ID_AD5696 ,
ID_AD5696R ,
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} ;
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enum ad5686_regmap_type {
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AD5310_REGMAP ,
iio:dac:ad5686: Add AD5681R/AD5682R/AD5683/AD5683R support
The AD5681R/AD5682R/AD5683/AD5683R are a family of one channel DACs with
12-bit, 14-bit and 16-bit precision respectively. The devices have either
no built-in reference, or built-in 2.5V reference.
These devices are similar to AD5691R/AD5692R/AD5693/AD5693R except
with a few notable differences:
* they use the SPI interface instead of I2C
* in the write control register, DB18 and DB17 are used for setting the
power mode, while DB16 is the REF bit. This is why a new regmap type
was defined and checked accordingly.
* the shift register is 24 bits wide, the first four bits are the command
bits followed by the data bits. As the data comprises of 20-bit, 18-bit
or 16-bit input code, this means that 4 LSB bits are don't care. This is
why the data needs to be shifted on the left with four bits. Therefore,
AD5683_REGMAP is checked inside a switch case in the ad5686_spi_write()
function. On the other hand, similar devices such as AD5693R family,
have the 4 MSB command bits followed by 4 don't care bits.
Datasheet:
http://www.analog.com/media/en/technical-documentation/data-sheets/AD5683R_5682R_5681R_5683.pdf
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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AD5683_REGMAP ,
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AD5686_REGMAP ,
AD5693_REGMAP
} ;
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struct ad5686_state ;
typedef int ( * ad5686_write_func ) ( struct ad5686_state * st ,
u8 cmd , u8 addr , u16 val ) ;
typedef int ( * ad5686_read_func ) ( struct ad5686_state * st , u8 addr ) ;
/**
* struct ad5686_chip_info - chip specific information
* @ int_vref_mv : AD5620 / 40 / 60 : the internal reference voltage
* @ num_channels : number of channels
* @ channel : channel specification
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* @ regmap_type : register map layout variant
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*/
struct ad5686_chip_info {
u16 int_vref_mv ;
unsigned int num_channels ;
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const struct iio_chan_spec * channels ;
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enum ad5686_regmap_type regmap_type ;
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} ;
/**
* struct ad5446_state - driver instance specific data
* @ spi : spi_device
* @ chip_info : chip model specific constants , available modes etc
* @ reg : supply regulator
* @ vref_mv : actual reference voltage used
* @ pwr_down_mask : power down mask
* @ pwr_down_mode : current power down mode
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* @ use_internal_vref : set to true if the internal reference voltage is used
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* @ lock lock to protect the data buffer during regmap ops
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* @ data : spi transfer buffers
*/
struct ad5686_state {
struct device * dev ;
const struct ad5686_chip_info * chip_info ;
struct regulator * reg ;
unsigned short vref_mv ;
unsigned int pwr_down_mask ;
unsigned int pwr_down_mode ;
ad5686_write_func write ;
ad5686_read_func read ;
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bool use_internal_vref ;
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struct mutex lock ;
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/*
* DMA ( thus cache coherency maintenance ) requires the
* transfer buffers to live in their own cache lines .
*/
union {
__be32 d32 ;
__be16 d16 ;
u8 d8 [ 4 ] ;
} data [ 3 ] ____cacheline_aligned ;
} ;
int ad5686_probe ( struct device * dev ,
enum ad5686_supported_device_ids chip_type ,
const char * name , ad5686_write_func write ,
ad5686_read_func read ) ;
int ad5686_remove ( struct device * dev ) ;
# endif /* __DRIVERS_IIO_DAC_AD5686_H__ */