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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Shared support code for AMD K8 northbridges and derivatives .
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* Copyright 2006 Andi Kleen , SUSE Labs .
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*/
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# define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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# include <linux/types.h>
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
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# include <linux/slab.h>
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# include <linux/init.h>
# include <linux/errno.h>
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# include <linux/export.h>
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# include <linux/spinlock.h>
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# include <linux/pci_ids.h>
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# include <asm/amd_nb.h>
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# define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
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# define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
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# define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
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# define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
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# define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
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# define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
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# define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
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# define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
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# define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
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# define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
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# define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
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# define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
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# define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
# define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
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# define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
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/* Protect the PCI config register pairs used for SMN. */
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static DEFINE_MUTEX ( smn_mutex ) ;
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static u32 * flush_words ;
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static const struct pci_device_id amd_root_ids [ ] = {
{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_ROOT ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M10H_ROOT ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M30H_ROOT ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M60H_ROOT ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M10H_ROOT ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M40H_ROOT ) } ,
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{ }
} ;
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# define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
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static const struct pci_device_id amd_nb_misc_ids [ ] = {
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_K8_NB_MISC ) } ,
{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_10H_NB_MISC ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_15H_NB_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_15H_M10H_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_15H_M30H_NB_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_15H_M60H_NB_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_16H_NB_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_DF_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_CNB17H_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_DF_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 ) } ,
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{ }
} ;
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static const struct pci_device_id amd_nb_link_ids [ ] = {
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_15H_NB_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_15H_M30H_NB_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_15H_M60H_NB_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_16H_NB_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_DF_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_DF_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 ) } ,
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{ PCI_DEVICE ( PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_CNB17H_F4 ) } ,
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{ }
} ;
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static const struct pci_device_id hygon_root_ids [ ] = {
{ PCI_DEVICE ( PCI_VENDOR_ID_HYGON , PCI_DEVICE_ID_AMD_17H_ROOT ) } ,
{ }
} ;
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static const struct pci_device_id hygon_nb_misc_ids [ ] = {
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{ PCI_DEVICE ( PCI_VENDOR_ID_HYGON , PCI_DEVICE_ID_AMD_17H_DF_F3 ) } ,
{ }
} ;
static const struct pci_device_id hygon_nb_link_ids [ ] = {
{ PCI_DEVICE ( PCI_VENDOR_ID_HYGON , PCI_DEVICE_ID_AMD_17H_DF_F4 ) } ,
{ }
} ;
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const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges [ ] __initconst = {
{ 0x00 , 0x18 , 0x20 } ,
{ 0xff , 0x00 , 0x20 } ,
{ 0xfe , 0x00 , 0x20 } ,
{ }
} ;
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static struct amd_northbridge_info amd_northbridges ;
u16 amd_nb_num ( void )
{
return amd_northbridges . num ;
}
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EXPORT_SYMBOL_GPL ( amd_nb_num ) ;
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bool amd_nb_has_feature ( unsigned int feature )
{
return ( ( amd_northbridges . flags & feature ) = = feature ) ;
}
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EXPORT_SYMBOL_GPL ( amd_nb_has_feature ) ;
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struct amd_northbridge * node_to_amd_nb ( int node )
{
return ( node < amd_northbridges . num ) ? & amd_northbridges . nb [ node ] : NULL ;
}
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EXPORT_SYMBOL_GPL ( node_to_amd_nb ) ;
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static struct pci_dev * next_northbridge ( struct pci_dev * dev ,
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const struct pci_device_id * ids )
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{
do {
dev = pci_get_device ( PCI_ANY_ID , PCI_ANY_ID , dev ) ;
if ( ! dev )
break ;
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} while ( ! pci_match_id ( ids , dev ) ) ;
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return dev ;
}
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static int __amd_smn_rw ( u16 node , u32 address , u32 * value , bool write )
{
struct pci_dev * root ;
int err = - ENODEV ;
if ( node > = amd_northbridges . num )
goto out ;
root = node_to_amd_nb ( node ) - > root ;
if ( ! root )
goto out ;
mutex_lock ( & smn_mutex ) ;
err = pci_write_config_dword ( root , 0x60 , address ) ;
if ( err ) {
pr_warn ( " Error programming SMN address 0x%x. \n " , address ) ;
goto out_unlock ;
}
err = ( write ? pci_write_config_dword ( root , 0x64 , * value )
: pci_read_config_dword ( root , 0x64 , value ) ) ;
if ( err )
pr_warn ( " Error %s SMN address 0x%x. \n " ,
( write ? " writing to " : " reading from " ) , address ) ;
out_unlock :
mutex_unlock ( & smn_mutex ) ;
out :
return err ;
}
int amd_smn_read ( u16 node , u32 address , u32 * value )
{
return __amd_smn_rw ( node , address , value , false ) ;
}
EXPORT_SYMBOL_GPL ( amd_smn_read ) ;
int amd_smn_write ( u16 node , u32 address , u32 value )
{
return __amd_smn_rw ( node , address , & value , true ) ;
}
EXPORT_SYMBOL_GPL ( amd_smn_write ) ;
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int amd_cache_northbridges ( void )
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{
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const struct pci_device_id * misc_ids = amd_nb_misc_ids ;
const struct pci_device_id * link_ids = amd_nb_link_ids ;
const struct pci_device_id * root_ids = amd_root_ids ;
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struct pci_dev * root , * misc , * link ;
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struct amd_northbridge * nb ;
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u16 roots_per_misc = 0 ;
u16 misc_count = 0 ;
u16 root_count = 0 ;
u16 i , j ;
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if ( amd_northbridges . num )
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return 0 ;
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if ( boot_cpu_data . x86_vendor = = X86_VENDOR_HYGON ) {
root_ids = hygon_root_ids ;
misc_ids = hygon_nb_misc_ids ;
link_ids = hygon_nb_link_ids ;
}
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misc = NULL ;
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while ( ( misc = next_northbridge ( misc , misc_ids ) ) ! = NULL )
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misc_count + + ;
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if ( ! misc_count )
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return - ENODEV ;
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root = NULL ;
while ( ( root = next_northbridge ( root , root_ids ) ) ! = NULL )
root_count + + ;
if ( root_count ) {
roots_per_misc = root_count / misc_count ;
/*
* There should be _exactly_ N roots for each DF / SMN
* interface .
*/
if ( ! roots_per_misc | | ( root_count % roots_per_misc ) ) {
pr_info ( " Unsupported AMD DF/PCI configuration found \n " ) ;
return - ENODEV ;
}
}
nb = kcalloc ( misc_count , sizeof ( struct amd_northbridge ) , GFP_KERNEL ) ;
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if ( ! nb )
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return - ENOMEM ;
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amd_northbridges . nb = nb ;
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amd_northbridges . num = misc_count ;
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link = misc = root = NULL ;
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for ( i = 0 ; i < amd_northbridges . num ; i + + ) {
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node_to_amd_nb ( i ) - > root = root =
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next_northbridge ( root , root_ids ) ;
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node_to_amd_nb ( i ) - > misc = misc =
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next_northbridge ( misc , misc_ids ) ;
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node_to_amd_nb ( i ) - > link = link =
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next_northbridge ( link , link_ids ) ;
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/*
* If there are more PCI root devices than data fabric /
* system management network interfaces , then the ( N )
* PCI roots per DF / SMN interface are functionally the
* same ( for DF / SMN access ) and N - 1 are redundant . N - 1
* PCI roots should be skipped per DF / SMN interface so
* the following DF / SMN interfaces get mapped to
* correct PCI roots .
*/
for ( j = 1 ; j < roots_per_misc ; j + + )
root = next_northbridge ( root , root_ids ) ;
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}
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if ( amd_gart_present ( ) )
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amd_northbridges . flags | = AMD_NB_GART ;
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/*
* Check for L3 cache presence .
*/
if ( ! cpuid_edx ( 0x80000006 ) )
return 0 ;
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/*
* Some CPU families support L3 Cache Index Disable . There are some
* limitations because of E382 and E388 on family 0x10 .
*/
if ( boot_cpu_data . x86 = = 0x10 & &
boot_cpu_data . x86_model > = 0x8 & &
( boot_cpu_data . x86_model > 0x9 | |
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boot_cpu_data . x86_stepping > = 0x1 ) )
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amd_northbridges . flags | = AMD_NB_L3_INDEX_DISABLE ;
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if ( boot_cpu_data . x86 = = 0x15 )
amd_northbridges . flags | = AMD_NB_L3_INDEX_DISABLE ;
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/* L3 cache partitioning is supported on family 0x15 */
if ( boot_cpu_data . x86 = = 0x15 )
amd_northbridges . flags | = AMD_NB_L3_PARTITIONING ;
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return 0 ;
}
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EXPORT_SYMBOL_GPL ( amd_cache_northbridges ) ;
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/*
* Ignores subdevice / subvendor but as far as I can figure out
* they ' re useless anyways
*/
bool __init early_is_amd_nb ( u32 device )
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{
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const struct pci_device_id * misc_ids = amd_nb_misc_ids ;
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const struct pci_device_id * id ;
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u32 vendor = device & 0xffff ;
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if ( boot_cpu_data . x86_vendor ! = X86_VENDOR_AMD & &
boot_cpu_data . x86_vendor ! = X86_VENDOR_HYGON )
return false ;
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if ( boot_cpu_data . x86_vendor = = X86_VENDOR_HYGON )
misc_ids = hygon_nb_misc_ids ;
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device > > = 16 ;
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for ( id = misc_ids ; id - > vendor ; id + + )
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if ( vendor = = id - > vendor & & device = = id - > device )
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return true ;
return false ;
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}
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struct resource * amd_get_mmconfig_range ( struct resource * res )
{
u32 address ;
u64 base , msr ;
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unsigned int segn_busn_bits ;
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if ( boot_cpu_data . x86_vendor ! = X86_VENDOR_AMD & &
boot_cpu_data . x86_vendor ! = X86_VENDOR_HYGON )
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return NULL ;
/* assume all cpus from fam10h have mmconfig */
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if ( boot_cpu_data . x86 < 0x10 )
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return NULL ;
address = MSR_FAM10H_MMIO_CONF_BASE ;
rdmsrl ( address , msr ) ;
/* mmconfig is not enabled */
if ( ! ( msr & FAM10H_MMIO_CONF_ENABLE ) )
return NULL ;
base = msr & ( FAM10H_MMIO_CONF_BASE_MASK < < FAM10H_MMIO_CONF_BASE_SHIFT ) ;
segn_busn_bits = ( msr > > FAM10H_MMIO_CONF_BUSRANGE_SHIFT ) &
FAM10H_MMIO_CONF_BUSRANGE_MASK ;
res - > flags = IORESOURCE_MEM ;
res - > start = base ;
res - > end = base + ( 1ULL < < ( segn_busn_bits + 20 ) ) - 1 ;
return res ;
}
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int amd_get_subcaches ( int cpu )
{
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struct pci_dev * link = node_to_amd_nb ( topology_die_id ( cpu ) ) - > link ;
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unsigned int mask ;
if ( ! amd_nb_has_feature ( AMD_NB_L3_PARTITIONING ) )
return 0 ;
pci_read_config_dword ( link , 0x1d4 , & mask ) ;
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return ( mask > > ( 4 * cpu_data ( cpu ) . cpu_core_id ) ) & 0xf ;
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}
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int amd_set_subcaches ( int cpu , unsigned long mask )
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{
static unsigned int reset , ban ;
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struct amd_northbridge * nb = node_to_amd_nb ( topology_die_id ( cpu ) ) ;
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unsigned int reg ;
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int cuid ;
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if ( ! amd_nb_has_feature ( AMD_NB_L3_PARTITIONING ) | | mask > 0xf )
return - EINVAL ;
/* if necessary, collect reset state of L3 partitioning and BAN mode */
if ( reset = = 0 ) {
pci_read_config_dword ( nb - > link , 0x1d4 , & reset ) ;
pci_read_config_dword ( nb - > misc , 0x1b8 , & ban ) ;
ban & = 0x180000 ;
}
/* deactivate BAN mode if any subcaches are to be disabled */
if ( mask ! = 0xf ) {
pci_read_config_dword ( nb - > misc , 0x1b8 , & reg ) ;
pci_write_config_dword ( nb - > misc , 0x1b8 , reg & ~ 0x180000 ) ;
}
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cuid = cpu_data ( cpu ) . cpu_core_id ;
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mask < < = 4 * cuid ;
mask | = ( 0xf ^ ( 1 < < cuid ) ) < < 26 ;
pci_write_config_dword ( nb - > link , 0x1d4 , mask ) ;
/* reset BAN mode if L3 partitioning returned to reset state */
pci_read_config_dword ( nb - > link , 0x1d4 , & reg ) ;
if ( reg = = reset ) {
pci_read_config_dword ( nb - > misc , 0x1b8 , & reg ) ;
reg & = ~ 0x180000 ;
pci_write_config_dword ( nb - > misc , 0x1b8 , reg | ban ) ;
}
return 0 ;
}
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static void amd_cache_gart ( void )
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{
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u16 i ;
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if ( ! amd_nb_has_feature ( AMD_NB_GART ) )
return ;
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flush_words = kmalloc_array ( amd_northbridges . num , sizeof ( u32 ) , GFP_KERNEL ) ;
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if ( ! flush_words ) {
amd_northbridges . flags & = ~ AMD_NB_GART ;
pr_notice ( " Cannot initialize GART flush words, GART support disabled \n " ) ;
return ;
}
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for ( i = 0 ; i ! = amd_northbridges . num ; i + + )
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pci_read_config_dword ( node_to_amd_nb ( i ) - > misc , 0x9c , & flush_words [ i ] ) ;
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}
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void amd_flush_garts ( void )
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{
int flushed , i ;
unsigned long flags ;
static DEFINE_SPINLOCK ( gart_lock ) ;
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if ( ! amd_nb_has_feature ( AMD_NB_GART ) )
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return ;
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/*
* Avoid races between AGP and IOMMU . In theory it ' s not needed
* but I ' m not sure if the hardware won ' t lose flush requests
* when another is pending . This whole thing is so expensive anyways
* that it doesn ' t matter to serialize more . - AK
*/
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spin_lock_irqsave ( & gart_lock , flags ) ;
flushed = 0 ;
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for ( i = 0 ; i < amd_northbridges . num ; i + + ) {
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pci_write_config_dword ( node_to_amd_nb ( i ) - > misc , 0x9c ,
flush_words [ i ] | 1 ) ;
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flushed + + ;
}
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for ( i = 0 ; i < amd_northbridges . num ; i + + ) {
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u32 w ;
/* Make sure the hardware actually executed the flush*/
for ( ; ; ) {
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pci_read_config_dword ( node_to_amd_nb ( i ) - > misc ,
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0x9c , & w ) ;
if ( ! ( w & 1 ) )
break ;
cpu_relax ( ) ;
}
}
spin_unlock_irqrestore ( & gart_lock , flags ) ;
if ( ! flushed )
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pr_notice ( " nothing to flush? \n " ) ;
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}
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EXPORT_SYMBOL_GPL ( amd_flush_garts ) ;
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static void __fix_erratum_688 ( void * info )
{
# define MSR_AMD64_IC_CFG 0xC0011021
msr_set_bit ( MSR_AMD64_IC_CFG , 3 ) ;
msr_set_bit ( MSR_AMD64_IC_CFG , 14 ) ;
}
/* Apply erratum 688 fix so machines without a BIOS fix work. */
static __init void fix_erratum_688 ( void )
{
struct pci_dev * F4 ;
u32 val ;
if ( boot_cpu_data . x86 ! = 0x14 )
return ;
if ( ! amd_northbridges . num )
return ;
F4 = node_to_amd_nb ( 0 ) - > link ;
if ( ! F4 )
return ;
if ( pci_read_config_dword ( F4 , 0x164 , & val ) )
return ;
if ( val & BIT ( 2 ) )
return ;
on_each_cpu ( __fix_erratum_688 , NULL , 0 ) ;
pr_info ( " x86/cpu/AMD: CPU erratum 688 worked around \n " ) ;
}
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static __init int init_amd_nbs ( void )
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{
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amd_cache_northbridges ( ) ;
amd_cache_gart ( ) ;
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fix_erratum_688 ( ) ;
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return 0 ;
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}
/* This has to go after the PCI subsystem */
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fs_initcall ( init_amd_nbs ) ;