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/ *
* PowerPC v e r s i o n
* Copyright ( C ) 1 9 9 5 - 1 9 9 6 G a r y T h o m a s ( g d t @linuxppc.org)
* Rewritten b y C o r t D o u g a n ( c o r t @cs.nmt.edu) for PReP
* Copyright ( C ) 1 9 9 6 C o r t D o u g a n < c o r t @cs.nmt.edu>
* Low- l e v e l e x c e p t i o n h a n d l e r s a n d M M U s u p p o r t
* rewritten b y P a u l M a c k e r r a s .
* Copyright ( C ) 1 9 9 6 P a u l M a c k e r r a s .
* MPC8 x x m o d i f i c a t i o n s b y D a n M a l e k
* Copyright ( C ) 1 9 9 7 D a n M a l e k ( d m a l e k @jlc.net).
*
* This f i l e c o n t a i n s l o w - l e v e l s u p p o r t a n d s e t u p f o r P o w e r P C 8 x x
* embedded p r o c e s s o r s , i n c l u d i n g t r a p a n d i n t e r r u p t d i s p a t c h .
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or
* modify i t u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* as p u b l i s h e d b y t h e F r e e S o f t w a r e F o u n d a t i o n ; either version
* 2 of t h e L i c e n s e , o r ( a t y o u r o p t i o n ) a n y l a t e r v e r s i o n .
*
* /
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# include < l i n u x / i n i t . h >
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# include < a s m / p r o c e s s o r . h >
# include < a s m / p a g e . h >
# include < a s m / m m u . h >
# include < a s m / c a c h e . h >
# include < a s m / p g t a b l e . h >
# include < a s m / c p u t a b l e . h >
# include < a s m / t h r e a d _ i n f o . h >
# include < a s m / p p c _ a s m . h >
# include < a s m / a s m - o f f s e t s . h >
2010-11-18 15:06:17 +00:00
# include < a s m / p t r a c e . h >
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 09:02:43 +02:00
# include < a s m / f i x m a p . h >
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/* Macro to make the code more readable. */
# ifdef C O N F I G _ 8 x x _ C P U 6
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# define S P R N _ M I _ T W C _ A D D R 0 x2 b80
# define S P R N _ M I _ R P N _ A D D R 0 x2 d80
# define S P R N _ M D _ T W C _ A D D R 0 x3 b80
# define S P R N _ M D _ R P N _ A D D R 0 x3 d80
# define M T S P R _ C P U 6 ( s p r , r e g , t r e g ) \
li t r e g , s p r ## _ A D D R ; \
stw t r e g , 1 2 ( r0 ) ; \
lwz t r e g , 1 2 ( r0 ) ; \
mtspr s p r , r e g
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# else
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# define M T S P R _ C P U 6 ( s p r , r e g , t r e g ) \
mtspr s p r , r e g
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# endif
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/* Macro to test if an address is a kernel address */
# if C O N F I G _ T A S K _ S I Z E < = 0 x80 0 0 0 0 0 0 & & C O N F I G _ P A G E _ O F F S E T > = 0 x80 0 0 0 0 0 0
# define I S _ K E R N E L ( t m p , a d d r ) \
andis. t m p , a d d r , 0 x80 0 0 / * A d d r e s s > = 0 x80 0 0 0 0 0 0 * /
# define B R A N C H _ U N L E S S _ K E R N E L ( l a b e l ) b e q l a b e l
# else
# define I S _ K E R N E L ( t m p , a d d r ) \
rlwinm t m p , a d d r , 1 6 , 1 6 , 3 1 ; \
cmpli c r0 , t m p , P A G E _ O F F S E T > > 1 6
# define B R A N C H _ U N L E S S _ K E R N E L ( l a b e l ) b l t l a b e l
# endif
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/ *
* Value f o r t h e b i t s t h a t h a v e f i x e d v a l u e i n R P N e n t r i e s .
* Also u s e d f o r t a g g i n g D A R f o r D T L B e r r o r .
* /
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# ifdef C O N F I G _ P P C _ 1 6 K _ P A G E S
# define R P N _ P A T T E R N ( 0 x00 f0 | M D _ S P S 1 6 K )
# else
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# define R P N _ P A T T E R N 0 x00 f0
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# endif
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_ _ HEAD
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_ ENTRY( _ s t e x t ) ;
_ ENTRY( _ s t a r t ) ;
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/ * MPC8 x x
* This p o r t w a s d o n e o n a n M B X b o a r d w i t h a n 8 6 0 . R i g h t n o w I o n l y
* support a n E L F c o m p r e s s e d ( z I m a g e ) b o o t f r o m E P P C - B u g b e c a u s e t h e
* code t h e r e l o a d s u p s o m e r e g i s t e r s b e f o r e c a l l i n g u s :
* r3 : ptr t o b o a r d i n f o d a t a
* r4 : initrd_ s t a r t o r i f n o i n i t r d t h e n 0
* r5 : initrd_ e n d - u n u s e d i f r4 i s 0
* r6 : Start o f c o m m a n d l i n e s t r i n g
* r7 : End o f c o m m a n d l i n e s t r i n g
*
* I d e c i d e d t o u s e c o n d i t i o n a l c o m p i l a t i o n i n s t e a d o f c h e c k i n g P V R a n d
* adding m o r e p r o c e s s o r s p e c i f i c b r a n c h e s a r o u n d c o d e I d o n ' t n e e d .
* Since t h i s i s a n e m b e d d e d p r o c e s s o r , I a l s o a p p r e c i a t e a n y m e m o r y
* savings I c a n g e t .
*
* The M P C 8 x x d o e s n o t h a v e a n y B A T s , b u t i t s u p p o r t s l a r g e p a g e s i z e s .
* We f i r s t i n i t i a l i z e t h e M M U t o s u p p o r t 8 M b y t e p a g e s , t h e n l o a d o n e
* entry i n t o e a c h o f t h e i n s t r u c t i o n a n d d a t a T L B s t o m a p t h e f i r s t
* 8 M 1 : 1 . I a l s o m a p p e d a n a d d i t i o n a l I / O s p a c e 1 : 1 s o w e c a n g e t t o
* the " i n t e r n a l " p r o c e s s o r r e g i s t e r s b e f o r e M M U _ i n i t i s c a l l e d .
*
* - - Dan
* /
.globl __start
__start :
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mr r31 ,r3 / * s a v e d e v i c e t r e e p t r * /
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/ * We h a v e t o t u r n o n t h e M M U r i g h t a w a y s o w e g e t c a c h e m o d e s
* set c o r r e c t l y .
* /
bl i n i t i a l _ m m u
/ * We n o w h a v e t h e l o w e r 8 M e g m a p p e d i n t o T L B e n t r i e s , a n d t h e c a c h e s
* ready t o w o r k .
* /
turn_on_mmu :
mfmsr r0
ori r0 ,r0 ,M S R _ D R | M S R _ I R
mtspr S P R N _ S R R 1 ,r0
lis r0 ,s t a r t _ h e r e @h
ori r0 ,r0 ,s t a r t _ h e r e @l
mtspr S P R N _ S R R 0 ,r0
SYNC
rfi / * e n a b l e s M M U * /
/ *
* Exception e n t r y c o d e . T h i s c o d e r u n s w i t h a d d r e s s t r a n s l a t i o n
* turned o f f , i . e . u s i n g p h y s i c a l a d d r e s s e s .
* We a s s u m e s p r g 3 h a s t h e p h y s i c a l a d d r e s s o f t h e c u r r e n t
* task' s t h r e a d _ s t r u c t .
* /
# define E X C E P T I O N _ P R O L O G \
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EXCEPTION_ P R O L O G _ 0 ; \
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mfcr r10 ; \
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EXCEPTION_ P R O L O G _ 1 ; \
EXCEPTION_ P R O L O G _ 2
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# define E X C E P T I O N _ P R O L O G _ 0 \
mtspr S P R N _ S P R G _ S C R A T C H 0 ,r10 ; \
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mtspr S P R N _ S P R G _ S C R A T C H 1 ,r11
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# define E X C E P T I O N _ P R O L O G _ 1 \
mfspr r11 ,S P R N _ S R R 1 ; /* check whether user or kernel */ \
andi. r11 ,r11 ,M S R _ P R ; \
tophys( r11 ,r1 ) ; /* use tophys(r1) if kernel */ \
beq 1 f ; \
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mfspr r11 ,S P R N _ S P R G _ T H R E A D ; \
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lwz r11 ,T H R E A D _ I N F O - T H R E A D ( r11 ) ; \
addi r11 ,r11 ,T H R E A D _ S I Z E ; \
tophys( r11 ,r11 ) ; \
1 : subi r11 ,r11 ,I N T _ F R A M E _ S I Z E / * a l l o c e x c . f r a m e * /
# define E X C E P T I O N _ P R O L O G _ 2 \
CLR_ T O P 3 2 ( r11 ) ; \
stw r10 ,_ C C R ( r11 ) ; /* save registers */ \
stw r12 ,G P R 1 2 ( r11 ) ; \
stw r9 ,G P R 9 ( r11 ) ; \
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mfspr r10 ,S P R N _ S P R G _ S C R A T C H 0 ; \
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stw r10 ,G P R 1 0 ( r11 ) ; \
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mfspr r12 ,S P R N _ S P R G _ S C R A T C H 1 ; \
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stw r12 ,G P R 1 1 ( r11 ) ; \
mflr r10 ; \
stw r10 ,_ L I N K ( r11 ) ; \
mfspr r12 ,S P R N _ S R R 0 ; \
mfspr r9 ,S P R N _ S R R 1 ; \
stw r1 ,G P R 1 ( r11 ) ; \
stw r1 ,0 ( r11 ) ; \
tovirt( r1 ,r11 ) ; /* set new kernel sp */ \
li r10 ,M S R _ K E R N E L & ~ ( M S R _ I R | M S R _ D R ) ; /* can take exceptions */ \
MTMSRD( r10 ) ; /* (except for mach check in rtas) */ \
stw r0 ,G P R 0 ( r11 ) ; \
SAVE_ 4 G P R S ( 3 , r11 ) ; \
SAVE_ 2 G P R S ( 7 , r11 )
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/ *
* Exception e x i t c o d e .
* /
# define E X C E P T I O N _ E P I L O G _ 0 \
mfspr r10 ,S P R N _ S P R G _ S C R A T C H 0 ; \
mfspr r11 ,S P R N _ S P R G _ S C R A T C H 1
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/ *
* Note : code w h i c h f o l l o w s t h i s u s e s c r0 . e q ( s e t i f f r o m k e r n e l ) ,
* r1 1 , r12 ( S R R 0 ) , a n d r9 ( S R R 1 ) .
*
* Note2 : once w e h a v e s e t r1 w e a r e i n a p o s i t i o n t o t a k e e x c e p t i o n s
* again, a n d w e c o u l d t h u s s e t M S R : R I a t t h a t p o i n t .
* /
/ *
* Exception v e c t o r s .
* /
# define E X C E P T I O N ( n , l a b e l , h d l r , x f e r ) \
. = n; \
label : \
EXCEPTION_ P R O L O G ; \
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D ; \
xfer( n , h d l r )
# define E X C _ X F E R _ T E M P L A T E ( n , h d l r , t r a p , c o p y e e , t f e r , r e t ) \
li r10 ,t r a p ; \
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stw r10 ,_ T R A P ( r11 ) ; \
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li r10 ,M S R _ K E R N E L ; \
copyee( r10 , r9 ) ; \
bl t f e r ; \
i## n : \
.long ; \
.long ret
# define C O P Y _ E E ( d , s ) r l w i m i d ,s ,0 ,1 6 ,1 6
# define N O C O P Y ( d , s )
# define E X C _ X F E R _ S T D ( n , h d l r ) \
EXC_ X F E R _ T E M P L A T E ( n , h d l r , n , N O C O P Y , t r a n s f e r _ t o _ h a n d l e r _ f u l l , \
ret_ f r o m _ e x c e p t _ f u l l )
# define E X C _ X F E R _ L I T E ( n , h d l r ) \
EXC_ X F E R _ T E M P L A T E ( n , h d l r , n + 1 , N O C O P Y , t r a n s f e r _ t o _ h a n d l e r , \
ret_ f r o m _ e x c e p t )
# define E X C _ X F E R _ E E ( n , h d l r ) \
EXC_ X F E R _ T E M P L A T E ( n , h d l r , n , C O P Y _ E E , t r a n s f e r _ t o _ h a n d l e r _ f u l l , \
ret_ f r o m _ e x c e p t _ f u l l )
# define E X C _ X F E R _ E E _ L I T E ( n , h d l r ) \
EXC_ X F E R _ T E M P L A T E ( n , h d l r , n + 1 , C O P Y _ E E , t r a n s f e r _ t o _ h a n d l e r , \
ret_ f r o m _ e x c e p t )
/* System reset */
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EXCEPTION( 0 x10 0 , R e s e t , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ S T D )
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/* Machine check */
. = 0 x2 0 0
MachineCheck :
EXCEPTION_ P R O L O G
mfspr r4 ,S P R N _ D A R
stw r4 ,_ D A R ( r11 )
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li r5 ,R P N _ P A T T E R N
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mtspr S P R N _ D A R ,r5 / * T a g D A R , t o b e u s e d i n D T L B E r r o r * /
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mfspr r5 ,S P R N _ D S I S R
stw r5 ,_ D S I S R ( r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
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EXC_ X F E R _ S T D ( 0 x20 0 , m a c h i n e _ c h e c k _ e x c e p t i o n )
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/ * Data a c c e s s e x c e p t i o n .
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* This i s " n e v e r g e n e r a t e d " b y t h e M P C 8 x x .
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* /
. = 0 x3 0 0
DataAccess :
/ * Instruction a c c e s s e x c e p t i o n .
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* This i s " n e v e r g e n e r a t e d " b y t h e M P C 8 x x .
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* /
. = 0 x4 0 0
InstructionAccess :
/* External interrupt */
EXCEPTION( 0 x50 0 , H a r d w a r e I n t e r r u p t , d o _ I R Q , E X C _ X F E R _ L I T E )
/* Alignment exception */
. = 0 x6 0 0
Alignment :
EXCEPTION_ P R O L O G
mfspr r4 ,S P R N _ D A R
stw r4 ,_ D A R ( r11 )
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li r5 ,R P N _ P A T T E R N
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mtspr S P R N _ D A R ,r5 / * T a g D A R , t o b e u s e d i n D T L B E r r o r * /
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mfspr r5 ,S P R N _ D S I S R
stw r5 ,_ D S I S R ( r11 )
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
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EXC_ X F E R _ E E ( 0 x60 0 , a l i g n m e n t _ e x c e p t i o n )
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/* Program check exception */
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EXCEPTION( 0 x70 0 , P r o g r a m C h e c k , p r o g r a m _ c h e c k _ e x c e p t i o n , E X C _ X F E R _ S T D )
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/ * No F P U o n M P C 8 x x . T h i s e x c e p t i o n i s n o t s u p p o s e d t o h a p p e n .
* /
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EXCEPTION( 0 x80 0 , F P U n a v a i l a b l e , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ S T D )
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/* Decrementer */
EXCEPTION( 0 x90 0 , D e c r e m e n t e r , t i m e r _ i n t e r r u p t , E X C _ X F E R _ L I T E )
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EXCEPTION( 0 x a00 , T r a p _ 0 a , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x b00 , T r a p _ 0 b , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
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/* System call */
. = 0 xc0 0
SystemCall :
EXCEPTION_ P R O L O G
EXC_ X F E R _ E E _ L I T E ( 0 x c00 , D o S y s c a l l )
/* Single step - not used on 601 */
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EXCEPTION( 0 x d00 , S i n g l e S t e p , s i n g l e _ s t e p _ e x c e p t i o n , E X C _ X F E R _ S T D )
EXCEPTION( 0 x e 0 0 , T r a p _ 0 e , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x f00 , T r a p _ 0 f , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
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/ * On t h e M P C 8 x x , t h i s i s a s o f t w a r e e m u l a t i o n i n t e r r u p t . I t o c c u r s
* for a l l u n i m p l e m e n t e d a n d i l l e g a l i n s t r u c t i o n s .
* /
EXCEPTION( 0 x10 0 0 , S o f t E m u , S o f t w a r e E m u l a t i o n , E X C _ X F E R _ S T D )
. = 0 x1 1 0 0
/ *
* For t h e M P C 8 x x , t h i s i s a s o f t w a r e t a b l e w a l k t o l o a d t h e i n s t r u c t i o n
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* TLB. T h e t a s k s w i t c h l o a d s t h e M _ T W r e g i s t e r w i t h t h e p o i n t e r t o t h e f i r s t
* level t a b l e .
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* If w e d i s c o v e r t h e r e i s n o s e c o n d l e v e l t a b l e ( v a l u e i s z e r o ) o r i f t h e r e
* is a n i n v a l i d p t e , w e l o a d t h a t i n t o t h e T L B , w h i c h c a u s e s a n o t h e r f a u l t
* into t h e T L B E r r o r i n t e r r u p t w h e r e w e c a n h a n d l e s u c h p r o b l e m s .
* We h a v e t o u s e t h e M D _ x x x r e g i s t e r s f o r t h e t a b l e w a l k b e c a u s e t h e
* equivalent M I _ x x x r e g i s t e r s o n l y p e r f o r m t h e a t t r i b u t e f u n c t i o n s .
* /
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# ifdef C O N F I G _ 8 x x _ C P U 1 5
# define I N V A L I D A T E _ A D J A C E N T _ P A G E S _ C P U 1 5 ( t m p , a d d r ) \
addi t m p , a d d r , P A G E _ S I Z E ; \
tlbie t m p ; \
addi t m p , a d d r , - P A G E _ S I Z E ; \
tlbie t m p
# else
# define I N V A L I D A T E _ A D J A C E N T _ P A G E S _ C P U 1 5 ( t m p , a d d r )
# endif
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InstructionTLBMiss :
# ifdef C O N F I G _ 8 x x _ C P U 6
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mtspr S P R N _ S P R G _ S C R A T C H 2 , r3
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# endif
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EXCEPTION_ P R O L O G _ 0
2005-09-26 16:04:21 +10:00
/ * If w e a r e f a u l t i n g a k e r n e l a d d r e s s , w e h a v e t o u s e t h e
* kernel p a g e t a b l e s .
* /
2016-02-03 23:34:21 +01:00
# if d e f i n e d ( C O N F I G _ M O D U L E S ) | | d e f i n e d ( C O N F I G _ D E B U G _ P A G E A L L O C )
2010-03-02 05:37:10 +00:00
/ * Only m o d u l e s w i l l c a u s e I T L B M i s s e s a s w e a l w a y s
* pin t h e f i r s t 8 M B o f k e r n e l m e m o r y * /
2015-04-20 07:54:42 +02:00
mfspr r11 , S P R N _ S R R 0 / * G e t e f f e c t i v e a d d r e s s o f f a u l t * /
INVALIDATE_ A D J A C E N T _ P A G E S _ C P U 1 5 ( r10 , r11 )
mfcr r10
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IS_ K E R N E L ( r11 , r11 )
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mfspr r11 , S P R N _ M _ T W / * G e t l e v e l 1 t a b l e * /
2015-04-20 07:54:46 +02:00
BRANCH_ U N L E S S _ K E R N E L ( 3 f )
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lis r11 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @ha
2005-09-26 16:04:21 +10:00
3 :
2015-04-20 07:54:42 +02:00
mtcr r10
mfspr r10 , S P R N _ S R R 0 / * G e t e f f e c t i v e a d d r e s s o f f a u l t * /
# else
mfspr r10 , S P R N _ S R R 0 / * G e t e f f e c t i v e a d d r e s s o f f a u l t * /
INVALIDATE_ A D J A C E N T _ P A G E S _ C P U 1 5 ( r11 , r10 )
mfspr r11 , S P R N _ M _ T W / * G e t l e v e l 1 t a b l e b a s e a d d r e s s * /
2010-03-02 05:37:10 +00:00
# endif
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/* Insert level 1 index */
rlwimi r11 , r10 , 3 2 - ( ( P A G E _ S H I F T - 2 ) < < 1 ) , ( P A G E _ S H I F T - 2 ) < < 1 , 2 9
2015-01-20 10:57:34 +01:00
lwz r11 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @l(r11) /* Get the level 1 entry */
2005-09-26 16:04:21 +10:00
2014-09-19 10:36:09 +02:00
/* Extract level 2 index */
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rlwinm r10 , r10 , 3 2 - ( P A G E _ S H I F T - 2 ) , 3 2 - P A G E _ S H I F T , 2 9
2015-04-22 12:06:43 +02:00
rlwimi r10 , r11 , 0 , 0 , 3 2 - P A G E _ S H I F T - 1 / * A d d l e v e l 2 b a s e * /
lwz r10 , 0 ( r10 ) / * G e t t h e p t e * /
/* Insert the APG into the TWC from the Linux PTE. */
2015-04-22 12:06:45 +02:00
rlwimi r11 , r10 , 0 , 2 5 , 2 6
2015-04-22 12:06:43 +02:00
/* Load the MI_TWC with the attributes for this "segment." */
MTSPR_ C P U 6 ( S P R N _ M I _ T W C , r11 , r3 ) / * S e t s e g m e n t a t t r i b u t e s * /
2005-09-26 16:04:21 +10:00
2010-03-02 05:37:11 +00:00
# ifdef C O N F I G _ S W A P
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rlwinm r11 , r10 , 3 2 - 5 , _ P A G E _ P R E S E N T
and r11 , r11 , r10
rlwimi r10 , r11 , 0 , _ P A G E _ P R E S E N T
2010-03-02 05:37:11 +00:00
# endif
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li r11 , R P N _ P A T T E R N
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/ * The L i n u x P T E w o n ' t g o e x a c t l y i n t o t h e M M U T L B .
2015-04-22 12:06:43 +02:00
* Software i n d i c a t o r b i t s 2 0 - 2 3 a n d 2 8 m u s t b e c l e a r .
2005-09-26 16:04:21 +10:00
* Software i n d i c a t o r b i t s 2 4 , 2 5 , 2 6 , a n d 2 7 m u s t b e
* set. A l l o t h e r L i n u x P T E b i t s c o n t r o l t h e b e h a v i o r
* of t h e M M U .
* /
2015-04-22 12:06:43 +02:00
rlwimi r10 , r11 , 0 , 0 x0 f f8 / * S e t 2 4 - 2 7 , c l e a r 2 0 - 2 3 ,2 8 * /
2014-09-19 10:36:09 +02:00
MTSPR_ C P U 6 ( S P R N _ M I _ R P N , r10 , r3 ) / * U p d a t e T L B e n t r y * /
2005-09-26 16:04:21 +10:00
2010-03-02 05:37:12 +00:00
/* Restore registers */
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# ifdef C O N F I G _ 8 x x _ C P U 6
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mfspr r3 , S P R N _ S P R G _ S C R A T C H 2
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# endif
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EXCEPTION_ E P I L O G _ 0
2005-09-26 16:04:21 +10:00
rfi
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/ *
* Bottom p a r t o f D a t a S t o r e T L B M i s s h a n d l e r f o r I M M R a r e a
* not e n o u g h s p a c e i n t h e D a t a S t o r e T L B M i s s a r e a
* /
DTLBMissIMMR :
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mtcr r10
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/* Set 512k byte guarded page and mark it valid */
li r10 , M D _ P S 5 1 2 K | M D _ G U A R D E D | M D _ S V A L I D
2016-05-17 09:02:51 +02:00
MTSPR_ C P U 6 ( S P R N _ M D _ T W C , r10 , r11 )
2016-05-17 09:02:45 +02:00
mfspr r10 , S P R N _ I M M R / * G e t c u r r e n t I M M R * /
rlwinm r10 , r10 , 0 , 0 x f f f80 0 0 0 / * G e t 5 1 2 k b y t e s b o u n d a r y * /
ori r10 , r10 , 0 x f0 | M D _ S P S 1 6 K | _ P A G E _ S H A R E D | _ P A G E _ D I R T Y | \
_ PAGE_ P R E S E N T | _ P A G E _ N O _ C A C H E
2016-05-17 09:02:51 +02:00
MTSPR_ C P U 6 ( S P R N _ M D _ R P N , r10 , r11 ) / * U p d a t e T L B e n t r y * /
2016-05-17 09:02:45 +02:00
li r11 , R P N _ P A T T E R N
mtspr S P R N _ D A R , r11 / * T a g D A R * /
EXCEPTION_ E P I L O G _ 0
rfi
2005-09-26 16:04:21 +10:00
. = 0 x1 2 0 0
DataStoreTLBMiss :
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EXCEPTION_ P R O L O G _ 0
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mfcr r10
2005-09-26 16:04:21 +10:00
/ * If w e a r e f a u l t i n g a k e r n e l a d d r e s s , w e h a v e t o u s e t h e
* kernel p a g e t a b l e s .
* /
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mfspr r11 , S P R N _ M D _ E P N
rlwinm r11 , r11 , 1 6 , 0 x f f f8
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# ifndef C O N F I G _ P I N _ T L B
cmpli c r0 , r11 , V I R T _ I M M R _ B A S E @h
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# endif
cmpli c r7 , r11 , P A G E _ O F F S E T @h
# ifndef C O N F I G _ P I N _ T L B
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_ ENTRY( D T L B M i s s _ j m p )
beq- D T L B M i s s I M M R
# endif
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bge- c r7 , 4 f
2016-05-17 09:02:45 +02:00
2016-05-17 09:02:51 +02:00
mfspr r11 , S P R N _ M _ T W / * G e t l e v e l 1 t a b l e * /
2005-09-26 16:04:21 +10:00
3 :
2016-05-17 09:02:51 +02:00
mtcr r10
# ifdef C O N F I G _ 8 x x _ C P U 6
mtspr S P R N _ S P R G _ S C R A T C H 2 , r3
# endif
mfspr r10 , S P R N _ M D _ E P N
2015-04-20 07:54:42 +02:00
2015-01-20 10:57:34 +01:00
/* Insert level 1 index */
rlwimi r11 , r10 , 3 2 - ( ( P A G E _ S H I F T - 2 ) < < 1 ) , ( P A G E _ S H I F T - 2 ) < < 1 , 2 9
2015-01-20 10:57:34 +01:00
lwz r11 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @l(r11) /* Get the level 1 entry */
2005-09-26 16:04:21 +10:00
/ * We h a v e a p t e t a b l e , s o l o a d f e t c h t h e p t e f r o m t h e t a b l e .
* /
2014-09-19 10:36:08 +02:00
/* Extract level 2 index */
2014-09-19 10:36:09 +02:00
rlwinm r10 , r10 , 3 2 - ( P A G E _ S H I F T - 2 ) , 3 2 - P A G E _ S H I F T , 2 9
rlwimi r10 , r11 , 0 , 0 , 3 2 - P A G E _ S H I F T - 1 / * A d d l e v e l 2 b a s e * /
2005-09-26 16:04:21 +10:00
lwz r10 , 0 ( r10 ) / * G e t t h e p t e * /
2015-04-22 12:06:43 +02:00
/ * Insert t h e G u a r d e d f l a g a n d A P G i n t o t h e T W C f r o m t h e L i n u x P T E .
* It i s b i t 2 6 - 2 7 o f b o t h t h e L i n u x P T E a n d t h e T W C ( a t l e a s t
2005-09-26 16:04:21 +10:00
* I g o t t h a t r i g h t : - ) . I t w i l l b e b e t t e r w h e n w e c a n p u t
* this i n t o t h e L i n u x p g d / p m d a n d l o a d i t i n t h e o p e r a t i o n
* above.
* /
2015-04-22 12:06:43 +02:00
rlwimi r11 , r10 , 0 , 2 6 , 2 7
2009-11-20 00:21:08 +00:00
/ * Insert t h e W r i t e T h r u f l a g i n t o t h e T W C f r o m t h e L i n u x P T E .
* It i s b i t 2 5 i n t h e L i n u x P T E a n d b i t 3 0 i n t h e T W C
* /
rlwimi r11 , r10 , 3 2 - 5 , 3 0 , 3 0
2014-09-19 10:36:09 +02:00
MTSPR_ C P U 6 ( S P R N _ M D _ T W C , r11 , r3 )
2005-09-26 16:04:21 +10:00
2009-11-20 00:21:03 +00:00
/ * Both _ P A G E _ A C C E S S E D a n d _ P A G E _ P R E S E N T h a s t o b e s e t .
* We a l s o n e e d t o k n o w i f t h e i n s n i s a l o a d / s t o r e , s o :
* Clear _ P A G E _ P R E S E N T a n d l o a d t h a t w h i c h w i l l
* trap i n t o D T L B E r r o r w i t h s t o r e b i t s e t a c c o r d i n l y .
* /
/ * PRESENT=0x1 , A C C E S S E D =0x20
* r1 1 = ( ( r10 & P R E S E N T ) & ( ( r10 & A C C E S S E D ) > > 5 ) ) ;
* r1 0 = ( r10 & ~ P R E S E N T ) | r11 ;
* /
2010-03-02 05:37:11 +00:00
# ifdef C O N F I G _ S W A P
2009-11-20 00:21:11 +00:00
rlwinm r11 , r10 , 3 2 - 5 , _ P A G E _ P R E S E N T
2009-11-20 00:21:03 +00:00
and r11 , r11 , r10
2009-11-20 00:21:11 +00:00
rlwimi r10 , r11 , 0 , _ P A G E _ P R E S E N T
2010-03-02 05:37:11 +00:00
# endif
2005-09-26 16:04:21 +10:00
/ * The L i n u x P T E w o n ' t g o e x a c t l y i n t o t h e M M U T L B .
2009-11-20 00:21:03 +00:00
* Software i n d i c a t o r b i t s 2 2 a n d 2 8 m u s t b e c l e a r .
2005-09-26 16:04:21 +10:00
* Software i n d i c a t o r b i t s 2 4 , 2 5 , 2 6 , a n d 2 7 m u s t b e
* set. A l l o t h e r L i n u x P T E b i t s c o n t r o l t h e b e h a v i o r
* of t h e M M U .
* /
2015-01-20 10:57:33 +01:00
li r11 , R P N _ P A T T E R N
2005-09-26 16:04:21 +10:00
rlwimi r10 , r11 , 0 , 2 4 , 2 8 / * S e t 2 4 - 2 7 , c l e a r 2 8 * /
2015-04-22 12:06:45 +02:00
rlwimi r10 , r11 , 0 , 2 0 , 2 0 / * c l e a r 2 0 * /
2014-09-19 10:36:09 +02:00
MTSPR_ C P U 6 ( S P R N _ M D _ R P N , r10 , r3 ) / * U p d a t e T L B e n t r y * /
2005-09-26 16:04:21 +10:00
2010-03-02 05:37:12 +00:00
/* Restore registers */
2016-05-17 09:02:51 +02:00
# ifdef C O N F I G _ 8 x x _ C P U 6
2015-04-20 07:54:44 +02:00
mfspr r3 , S P R N _ S P R G _ S C R A T C H 2
2016-05-17 09:02:51 +02:00
# endif
2014-08-29 11:14:37 +02:00
mtspr S P R N _ D A R , r11 / * T a g D A R * /
EXCEPTION_ E P I L O G _ 0
2005-09-26 16:04:21 +10:00
rfi
2016-05-17 09:02:51 +02:00
4 :
_ ENTRY( D T L B M i s s _ c m p )
2016-05-17 09:02:54 +02:00
cmpli c r0 , r11 , ( P A G E _ O F F S E T + 0 x18 0 0 0 0 0 ) @h
2016-05-17 09:02:51 +02:00
lis r11 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @ha
bge- 3 b
mtcr r10
/* Set 8M byte page and mark it valid */
li r10 , M D _ P S 8 M E G | M D _ S V A L I D
MTSPR_ C P U 6 ( S P R N _ M D _ T W C , r10 , r11 )
mfspr r10 , S P R N _ M D _ E P N
rlwinm r10 , r10 , 0 , 0 x0 f80 0 0 0 0 / * 8 x x s u p p o r t s m a x 2 5 6 M b R A M * /
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-09 17:07:50 +01:00
ori r10 , r10 , 0 x f0 | M D _ S P S 1 6 K | _ P A G E _ S H A R E D | _ P A G E _ D I R T Y | \
_ PAGE_ P R E S E N T
2016-05-17 09:02:51 +02:00
MTSPR_ C P U 6 ( S P R N _ M D _ R P N , r10 , r11 ) / * U p d a t e T L B e n t r y * /
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-09 17:07:50 +01:00
li r11 , R P N _ P A T T E R N
mtspr S P R N _ D A R , r11 / * T a g D A R * /
EXCEPTION_ E P I L O G _ 0
rfi
2005-09-26 16:04:21 +10:00
/ * This i s a n i n s t r u c t i o n T L B e r r o r o n t h e M P C 8 x x . T h i s c o u l d b e d u e
* to m a n y r e a s o n s , s u c h a s e x e c u t i n g g u a r d e d m e m o r y o r i l l e g a l i n s t r u c t i o n
* addresses. T h e r e i s n o t h i n g t o d o b u t h a n d l e a b i g t i m e e r r o r f a u l t .
* /
. = 0 x1 3 0 0
InstructionTLBError :
2015-01-20 10:57:33 +01:00
EXCEPTION_ P R O L O G
2014-09-19 10:36:06 +02:00
mr r4 ,r12
mr r5 ,r9
2014-09-19 10:36:10 +02:00
andis. r10 ,r5 ,0 x40 0 0
beq+ 1 f
tlbie r4
2014-09-19 10:36:06 +02:00
/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
2014-09-19 10:36:10 +02:00
1 : EXC_ X F E R _ L I T E ( 0 x40 0 , h a n d l e _ p a g e _ f a u l t )
2005-09-26 16:04:21 +10:00
/ * This i s t h e d a t a T L B e r r o r o n t h e M P C 8 x x . T h i s c o u l d b e d u e t o
2014-08-29 11:14:38 +02:00
* many r e a s o n s , i n c l u d i n g a d i r t y u p d a t e t o a p t e . W e b a i l o u t t o
* a h i g h e r l e v e l f u n c t i o n t h a t c a n h a n d l e i t .
2005-09-26 16:04:21 +10:00
* /
. = 0 x1 4 0 0
DataTLBError :
2014-08-29 11:14:37 +02:00
EXCEPTION_ P R O L O G _ 0
2015-04-20 07:54:40 +02:00
mfcr r10
2005-09-26 16:04:21 +10:00
2014-08-29 11:14:38 +02:00
mfspr r11 , S P R N _ D A R
2014-09-19 10:36:09 +02:00
cmpwi c r0 , r11 , R P N _ P A T T E R N
2009-11-20 00:21:06 +00:00
beq- F i x u p D A R / * m u s t b e a b u g g y d c b X , i c b i i n s n . * /
2014-08-29 11:14:37 +02:00
DARFixed : /* Return from dcbx instruction bug workaround */
2014-09-19 10:36:08 +02:00
EXCEPTION_ P R O L O G _ 1
EXCEPTION_ P R O L O G _ 2
2014-09-19 10:36:10 +02:00
mfspr r5 ,S P R N _ D S I S R
stw r5 ,_ D S I S R ( r11 )
2014-09-19 10:36:07 +02:00
mfspr r4 ,S P R N _ D A R
2014-09-19 10:36:10 +02:00
andis. r10 ,r5 ,0 x40 0 0
beq+ 1 f
tlbie r4
1 : li r10 ,R P N _ P A T T E R N
2014-09-19 10:36:07 +02:00
mtspr S P R N _ D A R ,r10 / * T a g D A R , t o b e u s e d i n D T L B E r r o r * /
/* 0x300 is DataAccess exception, needed by bad_page_fault() */
EXC_ X F E R _ L I T E ( 0 x30 0 , h a n d l e _ p a g e _ f a u l t )
2005-09-26 16:04:21 +10:00
2005-10-01 18:43:42 +10:00
EXCEPTION( 0 x15 0 0 , T r a p _ 1 5 , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x16 0 0 , T r a p _ 1 6 , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x17 0 0 , T r a p _ 1 7 , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x18 0 0 , T r a p _ 1 8 , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x19 0 0 , T r a p _ 1 9 , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x1 a00 , T r a p _ 1 a , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x1 b00 , T r a p _ 1 b , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
2005-09-26 16:04:21 +10:00
/ * On t h e M P C 8 x x , t h e s e n e x t f o u r t r a p s a r e u s e d f o r d e v e l o p m e n t
* support o f b r e a k p o i n t s a n d s u c h . S o m e d a y I w i l l g e t a r o u n d t o
* using t h e m .
* /
2005-10-01 18:43:42 +10:00
EXCEPTION( 0 x1 c00 , T r a p _ 1 c , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x1 d00 , T r a p _ 1 d , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x1 e 0 0 , T r a p _ 1 e , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
EXCEPTION( 0 x1 f00 , T r a p _ 1 f , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ E E )
2005-09-26 16:04:21 +10:00
. = 0 x2 0 0 0
2009-11-20 00:21:06 +00:00
/ * This i s t h e p r o c e d u r e t o c a l c u l a t e t h e d a t a E A f o r b u g g y d c b x ,d c b i i n s t r u c t i o n s
* by d e c o d i n g t h e r e g i s t e r s u s e d b y t h e d c b x i n s t r u c t i o n a n d a d d i n g t h e m .
2014-08-29 11:14:37 +02:00
* DAR i s s e t t o t h e c a l c u l a t e d a d d r e s s .
2009-11-20 00:21:06 +00:00
* /
/* define if you don't want to use self modifying code */
# define N O _ S E L F _ M O D I F Y I N G _ C O D E
FixupDAR : /* Entry point for dcbx workaround. */
2014-08-29 11:14:38 +02:00
mtspr S P R N _ S P R G _ S C R A T C H 2 , r10
2009-11-20 00:21:06 +00:00
/* fetch instruction from memory. */
mfspr r10 , S P R N _ S R R 0
2015-04-20 07:54:46 +02:00
IS_ K E R N E L ( r11 , r10 )
2015-01-20 10:57:34 +01:00
mfspr r11 , S P R N _ M _ T W / * G e t l e v e l 1 t a b l e * /
2015-04-20 07:54:46 +02:00
BRANCH_ U N L E S S _ K E R N E L ( 3 f )
2016-05-17 09:02:51 +02:00
rlwinm r11 , r10 , 1 6 , 0 x f f f8
_ ENTRY( F i x u p D A R _ c m p )
2016-05-17 09:02:54 +02:00
cmpli c r7 , r11 , ( P A G E _ O F F S E T + 0 x18 0 0 0 0 0 ) @h
2016-05-17 09:02:51 +02:00
blt- c r7 , 2 0 0 f
2015-01-20 10:57:34 +01:00
lis r11 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @ha
2015-01-20 10:57:34 +01:00
/* Insert level 1 index */
3 : rlwimi r11 , r10 , 3 2 - ( ( P A G E _ S H I F T - 2 ) < < 1 ) , ( P A G E _ S H I F T - 2 ) < < 1 , 2 9
2015-01-20 10:57:34 +01:00
lwz r11 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @l(r11) /* Get the level 1 entry */
2015-01-20 10:57:34 +01:00
rlwinm r11 , r11 ,0 ,0 ,1 9 / * E x t r a c t p a g e d e s c r i p t o r p a g e a d d r e s s * /
/* Insert level 2 index */
rlwimi r11 , r10 , 3 2 - ( P A G E _ S H I F T - 2 ) , 3 2 - P A G E _ S H I F T , 2 9
lwz r11 , 0 ( r11 ) / * G e t t h e p t e * /
2009-11-20 00:21:06 +00:00
/* concat physical page address(r11) and page offset(r10) */
2014-09-19 10:36:09 +02:00
rlwimi r11 , r10 , 0 , 3 2 - P A G E _ S H I F T , 3 1
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-09 17:07:50 +01:00
201 : lwz r11 ,0 ( r11 )
2009-11-20 00:21:06 +00:00
/* Check if it really is a dcbx instruction. */
/ * dcbt a n d d c b t s t d o e s n o t g e n e r a t e D T L B M i s s e s / E r r o r s ,
* no n e e d t o i n c l u d e t h e m h e r e * /
2014-08-29 11:14:38 +02:00
xoris r10 , r11 , 0 x7 c00 / * c h e c k i f m a j o r O P c o d e i s 3 1 * /
rlwinm r10 , r10 , 0 , 2 1 , 5
2009-11-20 00:21:06 +00:00
cmpwi c r0 , r10 , 2 0 2 8 / * I s d c b z ? * /
beq+ 1 4 2 f
cmpwi c r0 , r10 , 9 4 0 / * I s d c b i ? * /
beq+ 1 4 2 f
cmpwi c r0 , r10 , 1 0 8 / * I s d c b s t ? * /
beq+ 1 4 4 f / * F i x u p s t o r e b i t ! * /
cmpwi c r0 , r10 , 1 7 2 / * I s d c b f ? * /
beq+ 1 4 2 f
cmpwi c r0 , r10 , 1 9 6 4 / * I s i c b i ? * /
beq+ 1 4 2 f
2014-08-29 11:14:38 +02:00
141 : mfspr r10 ,S P R N _ S P R G _ S C R A T C H 2
b D A R F i x e d / * N o p e , g o b a c k t o n o r m a l T L B p r o c e s s i n g * /
2009-11-20 00:21:06 +00:00
2016-05-17 09:02:51 +02:00
/* create physical page address from effective address */
200 : tophys( r11 , r10 )
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-09 17:07:50 +01:00
b 2 0 1 b
2009-11-20 00:21:06 +00:00
144 : mfspr r10 , S P R N _ D S I S R
rlwinm r10 , r10 ,0 ,7 ,5 / * C l e a r s t o r e b i t f o r b u g g y d c b s t i n s n * /
mtspr S P R N _ D S I S R , r10
142 : /* continue, it was a dcbx, dcbi instruction. */
# ifndef N O _ S E L F _ M O D I F Y I N G _ C O D E
andis. r10 ,r11 ,0 x1 f / * t e s t i f r e g R A i s r0 * /
li r10 ,m o d i f i e d _ i n s t r @l
dcbtst r0 ,r10 / * t o u c h f o r s t o r e * /
rlwinm r11 ,r11 ,0 ,0 ,2 0 / * Z e r o l o w e r 1 0 b i t s * /
oris r11 ,r11 ,6 4 0 / * T r a n s f o r m i n s t r . t o a " a d d r10 ,R A ,R B " * /
ori r11 ,r11 ,5 3 2
stw r11 ,0 ( r10 ) / * s t o r e a d d / a n d i n s t r u c t i o n * /
dcbf 0 ,r10 / * f l u s h n e w i n s t r . t o m e m o r y . * /
icbi 0 ,r10 / * i n v a l i d a t e i n s t r . c a c h e l i n e * /
2014-08-29 11:14:37 +02:00
mfspr r11 , S P R N _ S P R G _ S C R A T C H 1 / * r e s t o r e r11 * /
mfspr r10 , S P R N _ S P R G _ S C R A T C H 0 / * r e s t o r e r10 * /
2009-11-20 00:21:06 +00:00
isync / * W a i t u n t i l n e w i n s t r i s l o a d e d f r o m m e m o r y * /
modified_instr :
.space 4 /* this is where the add instr. is stored */
bne+ 1 4 3 f
subf r10 ,r0 ,r10 / * r10 =r10 - r0 , o n l y i f r e g R A i s r0 * /
143 : mtdar r10 / * s t o r e f a u l t i n g E A i n D A R * /
2014-08-29 11:14:38 +02:00
mfspr r10 ,S P R N _ S P R G _ S C R A T C H 2
2009-11-20 00:21:06 +00:00
b D A R F i x e d / * G o b a c k t o n o r m a l T L B h a n d l i n g * /
# else
mfctr r10
mtdar r10 / * s a v e c t r r e g i n D A R * /
rlwinm r10 , r11 , 2 4 , 2 4 , 2 8 / * o f f s e t i n t o j u m p t a b l e f o r r e g R B * /
addi r10 , r10 , 1 5 0 f @l /* add start of table */
mtctr r10 / * l o a d c t r w i t h j u m p a d d r e s s * /
xor r10 , r10 , r10 / * s u m s t a r t s a t z e r o * /
bctr / * j u m p i n t o t a b l e * /
150 :
add r10 , r10 , r0 ;b 151f
add r10 , r10 , r1 ;b 151f
add r10 , r10 , r2 ;b 151f
add r10 , r10 , r3 ;b 151f
add r10 , r10 , r4 ;b 151f
add r10 , r10 , r5 ;b 151f
add r10 , r10 , r6 ;b 151f
add r10 , r10 , r7 ;b 151f
add r10 , r10 , r8 ;b 151f
add r10 , r10 , r9 ;b 151f
mtctr r11 ;b 154f /* r10 needs special handling */
mtctr r11 ;b 153f /* r11 needs special handling */
add r10 , r10 , r12 ;b 151f
add r10 , r10 , r13 ;b 151f
add r10 , r10 , r14 ;b 151f
add r10 , r10 , r15 ;b 151f
add r10 , r10 , r16 ;b 151f
add r10 , r10 , r17 ;b 151f
add r10 , r10 , r18 ;b 151f
add r10 , r10 , r19 ;b 151f
add r10 , r10 , r20 ;b 151f
add r10 , r10 , r21 ;b 151f
add r10 , r10 , r22 ;b 151f
add r10 , r10 , r23 ;b 151f
add r10 , r10 , r24 ;b 151f
add r10 , r10 , r25 ;b 151f
add r10 , r10 , r26 ;b 151f
add r10 , r10 , r27 ;b 151f
add r10 , r10 , r28 ;b 151f
add r10 , r10 , r29 ;b 151f
add r10 , r10 , r30 ;b 151f
add r10 , r10 , r31
151 :
rlwinm. r11 ,r11 ,1 9 ,2 4 ,2 8 / * o f f s e t i n t o j u m p t a b l e f o r r e g R A * /
beq 1 5 2 f / * i f r e g R A i s z e r o , d o n ' t a d d i t * /
addi r11 , r11 , 1 5 0 b @l /* add start of table */
mtctr r11 / * l o a d c t r w i t h j u m p a d d r e s s * /
rlwinm r11 ,r11 ,0 ,1 6 ,1 0 / * m a k e s u r e w e d o n ' t e x e c u t e t h i s m o r e t h a n o n c e * /
bctr / * j u m p i n t o t a b l e * /
152 :
mfdar r11
mtctr r11 / * r e s t o r e c t r r e g f r o m D A R * /
mtdar r10 / * s a v e f a u l t E A t o D A R * /
2014-08-29 11:14:38 +02:00
mfspr r10 ,S P R N _ S P R G _ S C R A T C H 2
2009-11-20 00:21:06 +00:00
b D A R F i x e d / * G o b a c k t o n o r m a l T L B h a n d l i n g * /
/* special handling for r10,r11 since these are modified already */
2014-08-29 11:14:37 +02:00
153 : mfspr r11 , S P R N _ S P R G _ S C R A T C H 1 / * l o a d r11 f r o m S P R N _ S P R G _ S C R A T C H 1 * /
2014-08-29 11:14:39 +02:00
add r10 , r10 , r11 / * a d d i t * /
mfctr r11 / * r e s t o r e r11 * /
b 1 5 1 b
2014-08-29 11:14:37 +02:00
154 : mfspr r11 , S P R N _ S P R G _ S C R A T C H 0 / * l o a d r10 f r o m S P R N _ S P R G _ S C R A T C H 0 * /
2014-08-29 11:14:39 +02:00
add r10 , r10 , r11 / * a d d i t * /
2009-11-20 00:21:06 +00:00
mfctr r11 / * r e s t o r e r11 * /
b 1 5 1 b
# endif
2005-09-26 16:04:21 +10:00
/ *
* This i s w h e r e t h e m a i n k e r n e l c o d e s t a r t s .
* /
start_here :
/* ptr to current */
lis r2 ,i n i t _ t a s k @h
ori r2 ,r2 ,i n i t _ t a s k @l
/* ptr to phys current thread */
tophys( r4 ,r2 )
addi r4 ,r4 ,T H R E A D / * i n i t t a s k ' s T H R E A D * /
2009-07-14 20:52:54 +00:00
mtspr S P R N _ S P R G _ T H R E A D ,r4
2005-09-26 16:04:21 +10:00
/* stack */
lis r1 ,i n i t _ t h r e a d _ u n i o n @ha
addi r1 ,r1 ,i n i t _ t h r e a d _ u n i o n @l
li r0 ,0
stwu r0 ,T H R E A D _ S I Z E - S T A C K _ F R A M E _ O V E R H E A D ( r1 )
bl e a r l y _ i n i t / * W e h a v e t o d o t h i s w i t h M M U o n * /
/ *
* Decide w h a t s o r t o f m a c h i n e t h i s i s a n d i n i t i a l i z e t h e M M U .
* /
2011-07-25 11:29:33 +00:00
li r3 ,0
mr r4 ,r31
2005-09-26 16:04:21 +10:00
bl m a c h i n e _ i n i t
bl M M U _ i n i t
/ *
* Go b a c k t o r u n n i n g u n m a p p e d s o w e c a n l o a d u p n e w v a l u e s
* and c h a n g e t o u s i n g o u r e x c e p t i o n v e c t o r s .
* On t h e 8 x x , a l l w e h a v e t o d o i s i n v a l i d a t e t h e T L B t o c l e a r
* the o l d 8 M b y t e T L B m a p p i n g s a n d l o a d t h e p a g e t a b l e b a s e r e g i s t e r .
* /
/ * The r i g h t w a y t o d o t h i s w o u l d b e t o t r a c k i t d o w n t h r o u g h
* init' s T H R E A D l i k e t h e c o n t e x t s w i t c h c o d e d o e s , b u t t h i s i s
* easier. . . . . . u n t i l s o m e o n e c h a n g e s i n i t ' s s t a t i c s t r u c t u r e s .
* /
2015-01-20 10:57:34 +01:00
lis r6 , s w a p p e r _ p g _ d i r @ha
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tophys( r6 ,r6 )
# ifdef C O N F I G _ 8 x x _ C P U 6
lis r4 , c p u 6 _ e r r a t a _ w o r d @h
ori r4 , r4 , c p u 6 _ e r r a t a _ w o r d @l
2014-09-19 10:36:08 +02:00
li r3 , 0 x3 f80
2005-09-26 16:04:21 +10:00
stw r3 , 1 2 ( r4 )
lwz r3 , 1 2 ( r4 )
# endif
2014-09-19 10:36:08 +02:00
mtspr S P R N _ M _ T W , r6
2005-09-26 16:04:21 +10:00
lis r4 ,2 f @h
ori r4 ,r4 ,2 f @l
tophys( r4 ,r4 )
li r3 ,M S R _ K E R N E L & ~ ( M S R _ I R | M S R _ D R )
mtspr S P R N _ S R R 0 ,r4
mtspr S P R N _ S R R 1 ,r3
rfi
/* Load up the kernel context */
2 :
SYNC / * F o r c e a l l P T E u p d a t e s t o f i n i s h * /
tlbia / * C l e a r a l l T L B e n t r i e s * /
sync / * w a i t f o r t l b i a / t l b i e t o f i n i s h * /
TLBSYNC / * . . . o n a l l C P U s * /
/ * set u p t h e P T E p o i n t e r s f o r t h e A b a t r o n b d i G D B .
* /
tovirt( r6 ,r6 )
lis r5 , a b a t r o n _ p t e p t r s @h
ori r5 , r5 , a b a t r o n _ p t e p t r s @l
stw r5 , 0 x f0 ( r0 ) / * M u s t m a t c h y o u r A b a t r o n c o n f i g f i l e * /
tophys( r5 ,r5 )
stw r6 , 0 ( r5 )
/* Now turn on the MMU for real! */
li r4 ,M S R _ K E R N E L
lis r3 ,s t a r t _ k e r n e l @h
ori r3 ,r3 ,s t a r t _ k e r n e l @l
mtspr S P R N _ S R R 0 ,r3
mtspr S P R N _ S R R 1 ,r4
rfi / * e n a b l e M M U a n d j u m p t o s t a r t _ k e r n e l * /
/ * Set u p t h e i n i t i a l M M U s t a t e s o w e c a n d o t h e f i r s t l e v e l o f
* kernel i n i t i a l i z a t i o n . T h i s m a p s t h e f i r s t 8 M B y t e s o f m e m o r y 1 : 1
* virtual t o p h y s i c a l . A l s o , s e t t h e c a c h e m o d e s i n c e t h a t i s d e f i n e d
* by T L B e n t r i e s a n d p e r f o r m a n y a d d i t i o n a l m a p p i n g ( l i k e o f t h e I M M R ) .
* If c o n f i g u r e d t o p i n s o m e T L B s , w e p i n t h e f i r s t 8 M b y t e s o f k e r n e l ,
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 09:02:43 +02:00
* 2 4 Mbytes o f d a t a , a n d t h e 5 1 2 k I M M R s p a c e . A n y t h i n g n o t c o v e r e d b y
2005-09-26 16:04:21 +10:00
* these m a p p i n g s i s m a p p e d b y p a g e t a b l e s .
* /
initial_mmu :
2016-05-17 09:02:49 +02:00
li r8 , 0
mtspr S P R N _ M I _ C T R , r8 / * r e m o v e P I N N E D I T L B e n t r i e s * /
lis r10 , M D _ R E S E T V A L @h
# ifndef C O N F I G _ 8 x x _ C O P Y B A C K
oris r10 , r10 , M D _ W T D E F @h
# endif
mtspr S P R N _ M D _ C T R , r10 / * r e m o v e P I N N E D D T L B e n t r i e s * /
2005-09-26 16:04:21 +10:00
tlbia / * I n v a l i d a t e a l l T L B e n t r i e s * /
2009-12-29 05:10:58 +00:00
/ * Always p i n t h e f i r s t 8 M B I T L B t o p r e v e n t I T L B
misses w h i l e m u c k i n g a r o u n d w i t h S R R 0 / S R R 1 i n a s m
* /
2005-09-26 16:04:21 +10:00
lis r8 , M I _ R S V 4 I @h
ori r8 , r8 , 0 x1 c00
2009-12-29 05:10:58 +00:00
2005-09-26 16:04:21 +10:00
mtspr S P R N _ M I _ C T R , r8 / * S e t i n s t r u c t i o n M M U c o n t r o l * /
# ifdef C O N F I G _ P I N _ T L B
2016-05-17 09:02:49 +02:00
oris r10 , r10 , M D _ R S V 4 I @h
2005-09-26 16:04:21 +10:00
ori r10 , r10 , 0 x1 c00
mtspr S P R N _ M D _ C T R , r10 / * S e t d a t a T L B c o n t r o l * /
2016-05-17 09:02:49 +02:00
# endif
2005-09-26 16:04:21 +10:00
2016-05-17 09:02:54 +02:00
/* Now map the lower 8 Meg into the ITLB. */
2005-09-26 16:04:21 +10:00
lis r8 , K E R N E L B A S E @h /* Create vaddr for TLB */
ori r8 , r8 , M I _ E V A L I D / * M a r k i t v a l i d * /
mtspr S P R N _ M I _ E P N , r8
2015-04-22 12:06:45 +02:00
li r8 , M I _ P S 8 M E G | ( 2 < < 5 ) / * S e t 8 M b y t e p a g e , A P G 2 * /
2005-09-26 16:04:21 +10:00
ori r8 , r8 , M I _ S V A L I D / * M a k e i t v a l i d * /
mtspr S P R N _ M I _ T W C , r8
li r8 , M I _ B O O T I N I T / * C r e a t e R P N f o r a d d r e s s 0 * /
mtspr S P R N _ M I _ R P N , r8 / * S t o r e T L B e n t r y * /
2016-05-17 09:02:54 +02:00
2015-04-22 12:06:45 +02:00
lis r8 , M I _ A P G _ I N I T @h /* Set protection modes */
ori r8 , r8 , M I _ A P G _ I N I T @l
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mtspr S P R N _ M I _ A P , r8
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lis r8 , M D _ A P G _ I N I T @h
ori r8 , r8 , M D _ A P G _ I N I T @l
2005-09-26 16:04:21 +10:00
mtspr S P R N _ M D _ A P , r8
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 09:02:43 +02:00
/ * Map a 5 1 2 k p a g e f o r t h e I M M R t o g e t t h e p r o c e s s o r
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* internal r e g i s t e r s ( a m o n g o t h e r t h i n g s ) .
* /
# ifdef C O N F I G _ P I N _ T L B
mfspr r9 , 6 3 8 / * G e t c u r r e n t I M M R * /
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 09:02:43 +02:00
andis. r9 , r9 , 0 x f f f8 / * G e t 5 1 2 k b y t e s b o u n d a r y * /
2005-09-26 16:04:21 +10:00
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 09:02:43 +02:00
lis r8 , V I R T _ I M M R _ B A S E @h /* Create vaddr for TLB */
2005-09-26 16:04:21 +10:00
ori r8 , r8 , M D _ E V A L I D / * M a r k i t v a l i d * /
mtspr S P R N _ M D _ E P N , r8
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 09:02:43 +02:00
li r8 , M D _ P S 5 1 2 K | M D _ G U A R D E D / * S e t 5 1 2 k b y t e p a g e * /
2005-09-26 16:04:21 +10:00
ori r8 , r8 , M D _ S V A L I D / * M a k e i t v a l i d * /
mtspr S P R N _ M D _ T W C , r8
mr r8 , r9 / * C r e a t e p a d d r f o r T L B * /
ori r8 , r8 , M I _ B O O T I N I T | 0 x2 / * I n h i b i t c a c h e - - C o r t * /
mtspr S P R N _ M D _ R P N , r8
# endif
/ * Since t h e c a c h e i s e n a b l e d a c c o r d i n g t o t h e i n f o r m a t i o n w e
* just l o a d e d i n t o t h e T L B , i n v a l i d a t e a n d e n a b l e t h e c a c h e s h e r e .
* We s h o u l d p r o b a b l y c h e c k / s e t o t h e r m o d e s . . . . l a t e r .
* /
lis r8 , I D C _ I N V A L L @h
mtspr S P R N _ I C _ C S T , r8
mtspr S P R N _ D C _ C S T , r8
lis r8 , I D C _ E N A B L E @h
mtspr S P R N _ I C _ C S T , r8
# ifdef C O N F I G _ 8 x x _ C O P Y B A C K
mtspr S P R N _ D C _ C S T , r8
# else
/ * For a d e b u g o p t i o n , I l e f t t h i s h e r e t o e a s i l y e n a b l e
* the w r i t e t h r o u g h c a c h e m o d e
* /
lis r8 , D C _ S F W T @h
mtspr S P R N _ D C _ C S T , r8
lis r8 , I D C _ E N A B L E @h
mtspr S P R N _ D C _ C S T , r8
# endif
blr
/ *
* We p u t a f e w t h i n g s h e r e t h a t h a v e t o b e p a g e - a l i g n e d .
* This s t u f f g o e s a t t h e b e g i n n i n g o f t h e d a t a s e g m e n t ,
* which i s p a g e - a l i g n e d .
* /
.data
.globl sdata
sdata :
.globl empty_zero_page
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.align PAGE_SHIFT
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empty_zero_page :
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.space PAGE_SIZE
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.globl swapper_pg_dir
swapper_pg_dir :
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.space PGD_TABLE_SIZE
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/ * Room f o r t w o P T E t a b l e p o i n e r s , u s u a l l y t h e k e r n e l a n d c u r r e n t u s e r
* pointer t o t h e i r r e s p e c t i v e r o o t p a g e t a b l e ( p g d i r ) .
* /
abatron_pteptrs :
.space 8
# ifdef C O N F I G _ 8 x x _ C P U 6
.globl cpu6_errata_word
cpu6_errata_word :
.space 16
# endif
