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linux/arch/arm/mach-rockchip/pm.h

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 263 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-29 17:18:02 +03:00
/* SPDX-License-Identifier: GPL-2.0-only */
ARM: rockchip: add suspend and resume for RK3288 It's a basic version of suspend and resume for rockchip, it only support RK3288 now. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-01 11:52:17 +03:00
/*
* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
* Author: Tony Xie <tony.xie@rock-chips.com>
*/
#ifndef __MACH_ROCKCHIP_PM_H
#define __MACH_ROCKCHIP_PM_H
extern unsigned long rkpm_bootdata_cpusp;
extern unsigned long rkpm_bootdata_cpu_code;
extern unsigned long rkpm_bootdata_l2ctlr_f;
extern unsigned long rkpm_bootdata_l2ctlr;
extern unsigned long rkpm_bootdata_ddr_code;
extern unsigned long rkpm_bootdata_ddr_data;
extern unsigned long rk3288_bootram_sz;
void rockchip_slp_cpu_resume(void);
ARM: rockchip: make rockchip_suspend_init conditional If CONFIG_PM_SLEEP is disabled, we get a build error for rockchips: arch/arm/mach-rockchip/built-in.o: In function `rockchip_dt_init': :(.init.text+0x1c): undefined reference to `rockchip_suspend_init' This adds an inline alternative for that case. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Cc: linux-rockchip@lists.infradead.org
2015-01-27 23:26:36 +03:00
#ifdef CONFIG_PM_SLEEP
ARM: rockchip: add suspend and resume for RK3288 It's a basic version of suspend and resume for rockchip, it only support RK3288 now. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-01 11:52:17 +03:00
void __init rockchip_suspend_init(void);
ARM: rockchip: make rockchip_suspend_init conditional If CONFIG_PM_SLEEP is disabled, we get a build error for rockchips: arch/arm/mach-rockchip/built-in.o: In function `rockchip_dt_init': :(.init.text+0x1c): undefined reference to `rockchip_suspend_init' This adds an inline alternative for that case. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Cc: linux-rockchip@lists.infradead.org
2015-01-27 23:26:36 +03:00
#else
static inline void rockchip_suspend_init(void)
{
}
#endif
ARM: rockchip: add suspend and resume for RK3288 It's a basic version of suspend and resume for rockchip, it only support RK3288 now. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-01 11:52:17 +03:00
/****** following is rk3288 defined **********/
#define RK3288_PMU_WAKEUP_CFG0 0x00
#define RK3288_PMU_WAKEUP_CFG1 0x04
#define RK3288_PMU_PWRMODE_CON 0x18
#define RK3288_PMU_OSC_CNT 0x20
#define RK3288_PMU_PLL_CNT 0x24
#define RK3288_PMU_STABL_CNT 0x28
#define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
#define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
#define RK3288_PMU_CORE_PWRDWN_CNT 0x34
#define RK3288_PMU_CORE_PWRUP_CNT 0x38
#define RK3288_PMU_GPU_PWRDWN_CNT 0x3c
#define RK3288_PMU_GPU_PWRUP_CNT 0x40
#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
#define RK3288_PMU_PWRMODE_CON1 0x90
#define RK3288_SGRF_SOC_CON0 (0x0000)
#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
ARM: rockchip: disable watchdog during suspend The watchdog clock should be disable in dw_wdt_suspend, but we set a dummy clock to watchdog for rk3288. So the watchdog will continue to work during suspend. And we switch the system clock to 32khz from 24Mhz, during suspend, so the watchdog timer over count will increase to 755 times, about 12.5 hours, the original value is 60 seconds. So watchdog will reset the system over a night, but voltage are all incorrect, then it hang on reset. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-02-09 16:12:23 +03:00
#define SGRF_PCLK_WDT_GATE BIT(6)
#define SGRF_PCLK_WDT_GATE_WRITE BIT(22)
ARM: rockchip: add suspend and resume for RK3288 It's a basic version of suspend and resume for rockchip, it only support RK3288 now. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-01 11:52:17 +03:00
#define SGRF_FAST_BOOT_EN BIT(8)
#define SGRF_FAST_BOOT_EN_WRITE BIT(24)
ARM: rockchip: disable dapswjdp during suspend Reset dapswjdp is controlled by JTAG_TRSTN, if the iomux of this pin is not "jtag_trstn". the AP would think this pin is always high, so it can not reset before resume. When system resume, but the dapswjdp is not in a default state, it may Access some illegal address, it cause system crash during resume. Let's disable this jtag function by clear the dapdeviceen bit, it prohibit the dapswjdp to access memory and registers. This bit would be enable in MASKROM, so we need clear it in suspend everytime. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-04-15 08:57:11 +03:00
#define RK3288_SGRF_CPU_CON0 (0x40)
#define SGRF_DAPDEVICEEN BIT(0)
#define SGRF_DAPDEVICEEN_WRITE BIT(16)
ARM: rockchip: add suspend and resume for RK3288 It's a basic version of suspend and resume for rockchip, it only support RK3288 now. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-01 11:52:17 +03:00
/* PMU_WAKEUP_CFG1 bits */
#define PMU_ARMINT_WAKEUP_EN BIT(0)
ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend PMU_GPIOINT_WAKEUP_EN seems needed when entering the shallow suspend (with logic staying on) but does not seem to be needed for the deep suspend for unknown reasons. Testing revealed that this setting really is necessary to reliably resume the veyron devices from suspend. Reported-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2015-07-22 18:18:03 +03:00
#define PMU_GPIOINT_WAKEUP_EN BIT(3)
ARM: rockchip: add suspend and resume for RK3288 It's a basic version of suspend and resume for rockchip, it only support RK3288 now. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-01 11:52:17 +03:00
enum rk3288_pwr_mode_con {
PMU_PWR_MODE_EN = 0,
PMU_CLK_CORE_SRC_GATE_EN,
PMU_GLOBAL_INT_DISABLE,
PMU_L2FLUSH_EN,
PMU_BUS_PD_EN,
PMU_A12_0_PD_EN,
PMU_SCU_EN,
PMU_PLL_PD_EN,
PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */
PMU_PWROFF_COMB,
PMU_ALIVE_USE_LF,
PMU_PMU_USE_LF,
PMU_OSC_24M_DIS,
PMU_INPUT_CLAMP_EN,
PMU_WAKEUP_RESET_EN,
PMU_SREF0_ENTER_EN,
PMU_SREF1_ENTER_EN,
PMU_DDR0IO_RET_EN,
PMU_DDR1IO_RET_EN,
PMU_DDR0_GATING_EN,
PMU_DDR1_GATING_EN,
PMU_DDR0IO_RET_DE_REQ,
PMU_DDR1IO_RET_DE_REQ
};
enum rk3288_pwr_mode_con1 {
PMU_CLR_BUS = 0,
PMU_CLR_CORE,
PMU_CLR_CPUP,
PMU_CLR_ALIVE,
PMU_CLR_DMA,
PMU_CLR_PERI,
PMU_CLR_GPU,
PMU_CLR_VIDEO,
PMU_CLR_HEVC,
PMU_CLR_VIO,
};
#endif /* __MACH_ROCKCHIP_PM_H */
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