[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
/ *
2008-08-05 19:14:15 +04:00
* arch/ a r m / m a c h - o r i o n 5 x / i n c l u d e / m a c h / e n t r y - m a c r o . S
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
*
* Low- l e v e l I R Q h e l p e r m a c r o s f o r O r i o n p l a t f o r m s
*
2008-02-07 23:55:17 +03:00
* This f i l e i s l i c e n s e d u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c
* License v e r s i o n 2 . T h i s p r o g r a m i s l i c e n s e d " a s i s " w i t h o u t a n y
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
* warranty o f a n y k i n d , w h e t h e r e x p r e s s o r i m p l i e d .
* /
2009-04-22 23:08:17 +04:00
# include < m a c h / b r i d g e - r e g s . h >
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
.macro disable_fiq
.endm
.macro _ r e t _ t o _ u s e r , t m p1 , t m p2
.endm
.macro _ i r q n r _ p r e a m b l e , b a s e , t m p
ldr \ b a s e , =MAIN_IRQ_CAUSE
.endm
.macro _ i r q n r _ a n d _ b a s e , i r q n r , i r q s t a t , b a s e , t m p
ldr \ i r q s t a t , [ \ b a s e , #0 ] @ main cause
ldr \ t m p , [ \ b a s e , #( M A I N _ I R Q _ M A S K - M A I N _ I R Q _ C A U S E ) ] @ m a i n m a s k
mov \ i r q n r , #0 @ default irqnr
@ find cause bits that are unmasked
ands \ i r q s t a t , \ i r q s t a t , \ t m p @ clear Z flag if any
clzne \ i r q n r , \ i r q s t a t @ calc irqnr
rsbne \ i r q n r , \ i r q n r , #31
.endm
