2011-07-14 08:35:48 +08:00
* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
Required properties:
2014-02-16 20:10:55 +01:00
- compatible : Should be one of
"fsl,imx25-sdma"
"fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
"fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
"fsl,imx51-sdma"
"fsl,imx53-sdma"
"fsl,imx6q-sdma"
2014-03-11 11:23:48 +01:00
The -to variants should be preferred since they allow to determine the
2014-02-16 20:10:55 +01:00
correct ROM script addresses needed for the driver to work without additional
firmware.
2011-07-14 08:35:48 +08:00
- reg : Should contain SDMA registers location and length
- interrupts : Should contain SDMA interrupt
2013-05-30 22:23:32 +08:00
- #dma-cells : Must be <3>.
The first cell specifies the DMA request/event ID. See details below
about the second and third cell.
2011-07-14 08:35:48 +08:00
- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
scripts firmware
2013-05-30 22:23:32 +08:00
The second cell of dma phandle specifies the peripheral type of DMA transfer.
The full ID of peripheral types can be found below.
ID transfer type
---------------------
0 MCU domain SSI
1 Shared SSI
2 MMC
3 SDHC
4 MCU domain UART
5 Shared UART
6 FIRI
7 MCU domain CSPI
8 Shared CSPI
9 SIM
10 ATA
11 CCM
12 External peripheral
13 Memory Stick Host Controller
14 Shared Memory Stick Host Controller
15 DSP
16 Memory
17 FIFO type Memory
18 SPDIF
19 IPU Memory
20 ASRC
21 ESAI
2013-11-13 22:55:25 +08:00
22 SSI Dual FIFO (needs firmware ver >= 2)
2014-06-16 11:31:05 +08:00
23 Shared ASRC
2013-05-30 22:23:32 +08:00
The third cell specifies the transfer priority as below.
ID transfer priority
-------------------------
0 High
1 Medium
2 Low
2011-07-14 08:35:48 +08:00
Examples:
sdma@83fb0000 {
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
2013-05-30 22:23:32 +08:00
#dma-cells = <3>;
2011-07-14 08:35:48 +08:00
fsl,sdma-ram-script-name = "sdma-imx51.bin";
};
2013-05-30 22:23:32 +08:00
DMA clients connected to the i.MX SDMA controller must use the format
described in the dma.txt file.
Examples:
ssi2: ssi@70014000 {
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x70014000 0x4000>;
interrupts = <30>;
clocks = <&clks 49>;
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
};