2012-06-13 19:01:28 +02:00
/*
* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
*
* Copyright (C) 2012 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* This file contains the definitions that are common to the Armada
* 370 and Armada XP SoC.
*/
2013-04-12 16:29:10 +02:00
/include/ "skeleton64.dtsi"
2012-06-13 19:01:28 +02:00
/ {
model = "Marvell Armada 370 and XP SoC";
2012-11-09 16:29:17 +01:00
compatible = "marvell,armada-370-xp";
2012-06-13 19:01:28 +02:00
cpus {
cpu@0 {
compatible = "marvell,sheeva-v7";
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&mpic>;
2013-04-12 16:29:10 +02:00
ranges = <0 0 0xd0000000 0x100000>;
2012-06-13 19:01:28 +02:00
2013-04-12 16:29:09 +02:00
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
mpic: interrupt-controller@20000 {
2013-04-12 16:29:08 +02:00
compatible = "marvell,mpic";
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
2013-04-12 16:29:09 +02:00
};
2013-04-12 16:29:07 +02:00
2013-04-12 16:29:09 +02:00
coherency-fabric@20200 {
2013-04-12 16:29:08 +02:00
compatible = "marvell,coherency-fabric";
2013-04-12 16:29:09 +02:00
reg = <0x20200 0xb0>, <0x21810 0x1c>;
};
2013-04-12 16:29:07 +02:00
2013-04-12 16:29:09 +02:00
serial@12000 {
2012-12-04 18:04:59 +01:00
compatible = "snps,dw-apb-uart";
2013-04-12 16:29:08 +02:00
reg = <0x12000 0x100>;
2012-06-13 19:01:28 +02:00
reg-shift = <2>;
interrupts = <41>;
2013-03-06 11:23:33 +01:00
reg-io-width = <1>;
2012-06-13 19:01:28 +02:00
status = "disabled";
2013-04-12 16:29:09 +02:00
};
serial@12100 {
2012-12-04 18:04:59 +01:00
compatible = "snps,dw-apb-uart";
2013-04-12 16:29:08 +02:00
reg = <0x12100 0x100>;
2012-06-13 19:01:28 +02:00
reg-shift = <2>;
interrupts = <42>;
2013-03-06 11:23:33 +01:00
reg-io-width = <1>;
2012-06-13 19:01:28 +02:00
status = "disabled";
2013-04-12 16:29:09 +02:00
};
timer@20300 {
compatible = "marvell,armada-370-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
clocks = <&coreclk 2>;
};
sata@a0000 {
compatible = "marvell,orion-sata";
reg = <0xa0000 0x2400>;
interrupts = <55>;
clocks = <&gateclk 15>, <&gateclk 30>;
clock-names = "0", "1";
status = "disabled";
};
2012-10-26 14:30:47 +02:00
2013-04-12 16:29:09 +02:00
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>;
};
2012-09-04 15:06:43 +02:00
2013-04-12 16:29:09 +02:00
ethernet@70000 {
2012-09-04 15:06:43 +02:00
compatible = "marvell,armada-370-neta";
2013-04-12 16:29:08 +02:00
reg = <0x70000 0x2500>;
2012-09-04 15:06:43 +02:00
interrupts = <8>;
2012-11-19 14:18:09 +01:00
clocks = <&gateclk 4>;
2012-09-04 15:06:43 +02:00
status = "disabled";
2013-04-12 16:29:09 +02:00
};
2012-09-04 15:06:43 +02:00
2013-04-12 16:29:09 +02:00
ethernet@74000 {
2012-09-04 15:06:43 +02:00
compatible = "marvell,armada-370-neta";
2013-04-12 16:29:08 +02:00
reg = <0x74000 0x2500>;
2012-09-04 15:06:43 +02:00
interrupts = <10>;
2012-11-19 14:18:09 +01:00
clocks = <&gateclk 3>;
2012-09-04 15:06:43 +02:00
status = "disabled";
2013-04-12 16:29:09 +02:00
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <31>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <32>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <50>;
};
mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <54>;
clocks = <&gateclk 17>;
status = "disabled";
};
2013-01-23 12:26:30 -03:00
2013-04-12 16:29:09 +02:00
usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};
2013-02-06 10:06:21 -03:00
2013-04-12 16:29:09 +02:00
usb@51000 {
compatible = "marvell,orion-ehci";
reg = <0x51000 0x500>;
interrupts = <46>;
status = "disabled";
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
2013-04-10 16:04:01 -03:00
2013-04-12 16:29:09 +02:00
devbus-bootcs@10400 {
compatible = "marvell,mvebu-devbus";
reg = <0x10400 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
2013-04-10 16:04:01 -03:00
2013-04-12 16:29:09 +02:00
devbus-cs0@10408 {
compatible = "marvell,mvebu-devbus";
reg = <0x10408 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
2013-04-10 16:04:01 -03:00
2013-04-12 16:29:09 +02:00
devbus-cs1@10410 {
compatible = "marvell,mvebu-devbus";
reg = <0x10410 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
2013-04-10 16:04:01 -03:00
2013-04-12 16:29:09 +02:00
devbus-cs2@10418 {
compatible = "marvell,mvebu-devbus";
reg = <0x10418 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
2013-04-10 16:04:01 -03:00
2013-04-12 16:29:09 +02:00
devbus-cs3@10420 {
compatible = "marvell,mvebu-devbus";
reg = <0x10420 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
2013-04-10 16:04:01 -03:00
};
2012-06-13 19:01:28 +02:00
};
2013-04-12 16:29:09 +02:00
};