2019-07-25 16:58:31 +09:00
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
2017-07-10 18:07:09 -07:00
/*
* Copyright ( C ) 2012 Regents of the University of California
*/
# ifndef _UAPI_ASM_RISCV_PTRACE_H
# define _UAPI_ASM_RISCV_PTRACE_H
# ifndef __ASSEMBLY__
# include <linux/types.h>
2023-07-11 23:07:54 +10:00
# define PTRACE_GETFDPIC 33
# define PTRACE_GETFDPIC_EXEC 0
# define PTRACE_GETFDPIC_INTERP 1
2017-07-10 18:07:09 -07:00
/*
* User - mode register state for core dumps , ptrace , sigcontext
*
* This decouples struct pt_regs from the userspace ABI .
* struct user_regs_struct must form a prefix of struct pt_regs .
*/
struct user_regs_struct {
unsigned long pc ;
unsigned long ra ;
unsigned long sp ;
unsigned long gp ;
unsigned long tp ;
unsigned long t0 ;
unsigned long t1 ;
unsigned long t2 ;
unsigned long s0 ;
unsigned long s1 ;
unsigned long a0 ;
unsigned long a1 ;
unsigned long a2 ;
unsigned long a3 ;
unsigned long a4 ;
unsigned long a5 ;
unsigned long a6 ;
unsigned long a7 ;
unsigned long s2 ;
unsigned long s3 ;
unsigned long s4 ;
unsigned long s5 ;
unsigned long s6 ;
unsigned long s7 ;
unsigned long s8 ;
unsigned long s9 ;
unsigned long s10 ;
unsigned long s11 ;
unsigned long t3 ;
unsigned long t4 ;
unsigned long t5 ;
unsigned long t6 ;
} ;
struct __riscv_f_ext_state {
__u32 f [ 32 ] ;
__u32 fcsr ;
} ;
struct __riscv_d_ext_state {
__u64 f [ 32 ] ;
__u32 fcsr ;
} ;
struct __riscv_q_ext_state {
__u64 f [ 64 ] __attribute__ ( ( aligned ( 16 ) ) ) ;
__u32 fcsr ;
/*
* Reserved for expansion of sigcontext structure . Currently zeroed
* upon signal , and must be zero upon sigreturn .
*/
__u32 reserved [ 3 ] ;
} ;
2023-06-05 11:07:11 +00:00
struct __riscv_ctx_hdr {
__u32 magic ;
__u32 size ;
} ;
struct __riscv_extra_ext_header {
__u32 __padding [ 129 ] __attribute__ ( ( aligned ( 16 ) ) ) ;
/*
* Reserved for expansion of sigcontext structure . Currently zeroed
* upon signal , and must be zero upon sigreturn .
*/
__u32 reserved ;
struct __riscv_ctx_hdr hdr ;
} ;
2017-07-10 18:07:09 -07:00
union __riscv_fp_state {
struct __riscv_f_ext_state f ;
struct __riscv_d_ext_state d ;
struct __riscv_q_ext_state q ;
} ;
2023-06-05 11:07:06 +00:00
struct __riscv_v_ext_state {
unsigned long vstart ;
unsigned long vl ;
unsigned long vtype ;
unsigned long vcsr ;
2023-08-16 15:54:49 +00:00
unsigned long vlenb ;
2023-06-05 11:07:06 +00:00
void * datap ;
/*
* In signal handler , datap will be set a correct user stack offset
* and vector registers will be copied to the address of datap
* pointer .
*/
} ;
2023-08-25 05:02:46 +00:00
struct __riscv_v_regset_state {
unsigned long vstart ;
unsigned long vl ;
unsigned long vtype ;
unsigned long vcsr ;
unsigned long vlenb ;
char vreg [ ] ;
} ;
2023-06-05 11:07:09 +00:00
/*
* According to spec : The number of bits in a single vector register ,
* VLEN > = ELEN , which must be a power of 2 , and must be no greater than
* 2 ^ 16 = 65536 bits = 8192 bytes
*/
# define RISCV_MAX_VLENB (8192)
2017-07-10 18:07:09 -07:00
# endif /* __ASSEMBLY__ */
# endif /* _UAPI_ASM_RISCV_PTRACE_H */