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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/ * low- l e v e l a s m f o r " i n t r i g u e " ( P A 8 5 0 0 - 8 7 0 0 C P U p e r f c o u n t e r s )
*
* Copyright ( C ) 2 0 0 1 R a n d o l p h C h u n g < t a u s q a t p a r i s c - l i n u x . o r g >
* Copyright ( C ) 2 0 0 1 H e w l e t t - P a c k a r d ( G r a n t G r u n d l e r )
* /
# include < a s m / a s s e m b l y . h >
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# include < l i n u x / i n i t . h >
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# include < l i n u x / l i n k a g e . h >
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# ifdef C O N F I G _ 6 4 B I T
.level 2 .0w
# endif / * C O N F I G _ 6 4 B I T * /
# define M T D I A G _ 1 ( g r ) . w o r d 0 x14 2 0 1 8 4 0 + g r * 0 x10 0 0 0
# define M T D I A G _ 2 ( g r ) . w o r d 0 x14 4 0 1 8 4 0 + g r * 0 x10 0 0 0
# define M F D I A G _ 1 ( g r ) . w o r d 0 x14 2 0 0 8 A 0 + g r
# define M F D I A G _ 2 ( g r ) . w o r d 0 x14 4 0 0 8 A 0 + g r
# define S T D I A G ( d r ) . w o r d 0 x14 0 0 0 A A 0 + d r * 0 x20 0 0 0 0
# define S F D I A G ( d r ) . w o r d 0 x14 0 0 0 B A 0 + d r * 0 x20 0 0 0 0
# define D R 2 _ S L O W _ R E T 5 3
;
; Enable the performance counters
;
; The coprocessor only needs to be enabled when
; starting/stopping the coprocessor with the pmenb/pmdis.
;
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.text
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ENTRY( p e r f _ i n t r i g u e _ e n a b l e _ p e r f _ c o u n t e r s )
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.proc
.callinfo frame=0 ,N O _ C A L L S
.entry
ldi 0 x20 ,% r25 ; load up perfmon bit
mfctl c c r ,% r26 ; get coprocessor register
or % r25 ,% r26 ,% r26 ; set bit
mtctl % r26 ,c c r ; turn on performance coprocessor
pmenb ; enable performance monitor
ssm 0 ,0 ; dummy op to ensure completion
sync ; follow ERS
andcm % r26 ,% r25 ,% r26 ; clear bit now
mtctl % r26 ,c c r ; turn off performance coprocessor
nop ; NOPs as specified in ERS
nop
nop
nop
nop
nop
nop
bve ( % r2 )
nop
.exit
.procend
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ENDPROC( p e r f _ i n t r i g u e _ e n a b l e _ p e r f _ c o u n t e r s )
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ENTRY( p e r f _ i n t r i g u e _ d i s a b l e _ p e r f _ c o u n t e r s )
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.proc
.callinfo frame=0 ,N O _ C A L L S
.entry
ldi 0 x20 ,% r25 ; load up perfmon bit
mfctl c c r ,% r26 ; get coprocessor register
or % r25 ,% r26 ,% r26 ; set bit
mtctl % r26 ,c c r ; turn on performance coprocessor
pmdis ; disable performance monitor
ssm 0 ,0 ; dummy op to ensure completion
andcm % r26 ,% r25 ,% r26 ; clear bit now
bve ( % r2 )
mtctl % r26 ,c c r ; turn off performance coprocessor
.exit
.procend
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ENDPROC( p e r f _ i n t r i g u e _ d i s a b l e _ p e r f _ c o u n t e r s )
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;***********************************************************************
;*
;* Name: perf_rdr_shift_in_W
;*
;* Description:
;* This routine shifts data in from the RDR in arg0 and returns
;* the result in ret0. If the RDR is <= 64 bits in length, it
;* is shifted shifted backup immediately. This is to compensate
;* for RDR10 which has bits that preclude PDC stack operations
;* when they are in the wrong state.
;*
;* Arguments:
;* arg0 : rdr to be read
;* arg1 : bit length of rdr
;*
;* Returns:
;* ret0 = next 64 bits of rdr data from staging register
;*
;* Register usage:
;* arg0 : rdr to be read
;* arg1 : bit length of rdr
;* %r24 - original DR2 value
;* %r1 - scratch
;* %r29 - scratch
;*
;* Returns:
;* ret0 = RDR data (right justified)
;*
;***********************************************************************
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ENTRY( p e r f _ r d r _ s h i f t _ i n _ W )
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.proc
.callinfo frame=0 ,N O _ C A L L S
.entry
;
; read(shift in) the RDR.
;
; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
; shifting is done, from or to, remote diagnose registers.
;
depdi,z 1 ,D R 2 _ S L O W _ R E T ,1 ,% r29
MFDIAG_ 2 ( 2 4 )
or % r24 ,% r29 ,% r29
MTDIAG_ 2 ( 2 9 ) ; set DR2_SLOW_RET
nop
nop
nop
nop
;
; Cacheline start (32-byte cacheline)
;
nop
nop
nop
extrd,u a r g 1 ,6 3 ,6 ,% r1 ; setup shift amount by bits to move
mtsar % r1
shladd a r g 0 ,2 ,% r0 ,% r1 ; %r1 = 4 * RDR number
blr % r1 ,% r0 ; branch to 8-instruction sequence
nop
;
; Cacheline start (32-byte cacheline)
;
;
; RDR 0 sequence
;
SFDIAG ( 0 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 ) ; mtdiag %dr1, %r1
STDIAG ( 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
;
; RDR 1 sequence
;
sync
ssm 0 ,0
SFDIAG ( 1 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
nop
;
; RDR 2 read sequence
;
SFDIAG ( 2 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 2 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
;
; RDR 3 read sequence
;
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
nop
nop
nop
nop
nop
nop
nop
;
; RDR 4 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 4 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 5 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 5 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 6 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 6 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 7 read sequence
;
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
nop
nop
nop
nop
nop
nop
nop
;
; RDR 8 read sequence
;
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
nop
nop
nop
nop
nop
nop
nop
;
; RDR 9 read sequence
;
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
nop
nop
nop
nop
nop
nop
nop
;
; RDR 10 read sequence
;
SFDIAG ( 1 0 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
;
; RDR 11 read sequence
;
SFDIAG ( 1 1 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
;
; RDR 12 read sequence
;
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
nop
nop
nop
nop
nop
nop
nop
;
; RDR 13 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 1 3 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 14 read sequence
;
SFDIAG ( 1 4 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 4 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
;
; RDR 15 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 1 5 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
nop
;
; RDR 16 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 1 6 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 17 read sequence
;
SFDIAG ( 1 7 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
;
; RDR 18 read sequence
;
SFDIAG ( 1 8 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 8 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
;
; RDR 19 read sequence
;
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
nop
nop
nop
nop
nop
nop
nop
;
; RDR 20 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 2 0 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 21 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 2 1 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 22 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 2 2 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 23 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 2 3 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 24 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 2 4 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 25 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 2 5 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 26 read sequence
;
SFDIAG ( 2 6 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 2 6 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
;
; RDR 27 read sequence
;
SFDIAG ( 2 7 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 2 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
;
; RDR 28 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 2 8 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 29 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 2 9 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 30 read sequence
;
SFDIAG ( 3 0 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 3 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ W _ l e a v e
;
; RDR 31 read sequence
;
sync
ssm 0 ,0
SFDIAG ( 3 1 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
nop
ssm 0 ,0
nop
;
; Fallthrough
;
perf_rdr_shift_in_W_leave :
bve ( % r2 )
.exit
MTDIAG_ 2 ( 2 4 ) ; restore DR2
.procend
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ENDPROC( p e r f _ r d r _ s h i f t _ i n _ W )
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;***********************************************************************
;*
;* Name: perf_rdr_shift_out_W
;*
;* Description:
;* This routine moves data to the RDR's. The double-word that
;* arg1 points to is loaded and moved into the staging register.
;* Then the STDIAG instruction for the RDR # in arg0 is called
;* to move the data to the RDR.
;*
;* Arguments:
;* arg0 = rdr number
;* arg1 = 64-bit value to write
;* %r24 - DR2 | DR2_SLOW_RET
;* %r23 - original DR2 value
;*
;* Returns:
;* None
;*
;* Register usage:
;*
;***********************************************************************
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ENTRY( p e r f _ r d r _ s h i f t _ o u t _ W )
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.proc
.callinfo frame=0 ,N O _ C A L L S
.entry
;
; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
; shifting is done, from or to, the remote diagnose registers.
;
depdi,z 1 ,D R 2 _ S L O W _ R E T ,1 ,% r24
MFDIAG_ 2 ( 2 3 )
or % r24 ,% r23 ,% r24
MTDIAG_ 2 ( 2 4 ) ; set DR2_SLOW_RET
MTDIAG_ 1 ( 2 5 ) ; data to the staging register
shladd a r g 0 ,2 ,% r0 ,% r1 ; %r1 = 4 * RDR number
blr % r1 ,% r0 ; branch to 8-instruction sequence
nop
;
; RDR 0 write sequence
;
sync ; RDR 0 write sequence
ssm 0 ,0
STDIAG ( 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 1 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 2 write sequence
;
sync
ssm 0 ,0
STDIAG ( 2 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 3 write sequence
;
sync
ssm 0 ,0
STDIAG ( 3 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 4 write sequence
;
sync
ssm 0 ,0
STDIAG ( 4 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 5 write sequence
;
sync
ssm 0 ,0
STDIAG ( 5 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 6 write sequence
;
sync
ssm 0 ,0
STDIAG ( 6 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 7 write sequence
;
sync
ssm 0 ,0
STDIAG ( 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 8 write sequence
;
sync
ssm 0 ,0
STDIAG ( 8 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 9 write sequence
;
sync
ssm 0 ,0
STDIAG ( 9 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 10 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 0 )
STDIAG ( 2 6 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 11 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 1 )
STDIAG ( 2 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 12 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 2 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 13 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 3 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 14 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 4 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 15 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 5 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 16 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 6 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 17 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 18 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 8 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 19 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 9 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 20 write sequence
;
sync
ssm 0 ,0
STDIAG ( 2 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 21 write sequence
;
sync
ssm 0 ,0
STDIAG ( 2 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 22 write sequence
;
sync
ssm 0 ,0
STDIAG ( 2 2 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 23 write sequence
;
sync
ssm 0 ,0
STDIAG ( 2 3 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 24 write sequence
;
sync
ssm 0 ,0
STDIAG ( 2 4 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 25 write sequence
;
sync
ssm 0 ,0
STDIAG ( 2 5 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 26 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 0 )
STDIAG ( 2 6 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 27 write sequence
;
sync
ssm 0 ,0
STDIAG ( 1 1 )
STDIAG ( 2 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
ssm 0 ,0
nop
;
; RDR 28 write sequence
;
sync
ssm 0 ,0
STDIAG ( 2 8 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 29 write sequence
;
sync
ssm 0 ,0
STDIAG ( 2 9 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 30 write sequence
;
sync
ssm 0 ,0
STDIAG ( 3 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
;
; RDR 31 write sequence
;
sync
ssm 0 ,0
STDIAG ( 3 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ W _ l e a v e
nop
ssm 0 ,0
nop
perf_rdr_shift_out_W_leave :
bve ( % r2 )
.exit
MTDIAG_ 2 ( 2 3 ) ; restore DR2
.procend
2007-01-25 00:36:32 +03:00
ENDPROC( p e r f _ r d r _ s h i f t _ o u t _ W )
2005-04-17 02:20:36 +04:00
;***********************************************************************
;*
;* Name: rdr_shift_in_U
;*
;* Description:
;* This routine shifts data in from the RDR in arg0 and returns
;* the result in ret0. If the RDR is <= 64 bits in length, it
;* is shifted shifted backup immediately. This is to compensate
;* for RDR10 which has bits that preclude PDC stack operations
;* when they are in the wrong state.
;*
;* Arguments:
;* arg0 : rdr to be read
;* arg1 : bit length of rdr
;*
;* Returns:
;* ret0 = next 64 bits of rdr data from staging register
;*
;* Register usage:
;* arg0 : rdr to be read
;* arg1 : bit length of rdr
;* %r24 - original DR2 value
;* %r23 - DR2 | DR2_SLOW_RET
;* %r1 - scratch
;*
;***********************************************************************
2007-01-25 00:36:32 +03:00
ENTRY( p e r f _ r d r _ s h i f t _ i n _ U )
2005-04-17 02:20:36 +04:00
.proc
.callinfo frame=0 ,N O _ C A L L S
.entry
; read(shift in) the RDR.
;
; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
; shifting is done, from or to, remote diagnose registers.
depdi,z 1 ,D R 2 _ S L O W _ R E T ,1 ,% r29
MFDIAG_ 2 ( 2 4 )
or % r24 ,% r29 ,% r29
MTDIAG_ 2 ( 2 9 ) ; set DR2_SLOW_RET
nop
nop
nop
nop
;
; Start of next 32-byte cacheline
;
nop
nop
nop
extrd,u a r g 1 ,6 3 ,6 ,% r1
mtsar % r1
shladd a r g 0 ,2 ,% r0 ,% r1 ; %r1 = 4 * RDR number
blr % r1 ,% r0 ; branch to 8-instruction sequence
nop
;
; Start of next 32-byte cacheline
;
SFDIAG ( 0 ) ; RDR 0 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
SFDIAG ( 1 ) ; RDR 1 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
sync ; RDR 2 read sequence
ssm 0 ,0
SFDIAG ( 4 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
sync ; RDR 3 read sequence
ssm 0 ,0
SFDIAG ( 3 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
sync ; RDR 4 read sequence
ssm 0 ,0
SFDIAG ( 4 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
sync ; RDR 5 read sequence
ssm 0 ,0
SFDIAG ( 5 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
sync ; RDR 6 read sequence
ssm 0 ,0
SFDIAG ( 6 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
sync ; RDR 7 read sequence
ssm 0 ,0
SFDIAG ( 7 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
nop
nop
nop
nop
nop
nop
nop
SFDIAG ( 9 ) ; RDR 9 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 9 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
SFDIAG ( 1 0 ) ; RDR 10 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
SFDIAG ( 1 1 ) ; RDR 11 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
SFDIAG ( 1 2 ) ; RDR 12 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 2 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
SFDIAG ( 1 3 ) ; RDR 13 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 3 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
SFDIAG ( 1 4 ) ; RDR 14 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 4 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
SFDIAG ( 1 5 ) ; RDR 15 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 5 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
sync ; RDR 16 read sequence
ssm 0 ,0
SFDIAG ( 1 6 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
SFDIAG ( 1 7 ) ; RDR 17 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
SFDIAG ( 1 8 ) ; RDR 18 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 1 8 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
nop
nop
nop
nop
nop
nop
nop
sync ; RDR 20 read sequence
ssm 0 ,0
SFDIAG ( 2 0 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
sync ; RDR 21 read sequence
ssm 0 ,0
SFDIAG ( 2 1 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
sync ; RDR 22 read sequence
ssm 0 ,0
SFDIAG ( 2 2 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
sync ; RDR 23 read sequence
ssm 0 ,0
SFDIAG ( 2 3 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
sync ; RDR 24 read sequence
ssm 0 ,0
SFDIAG ( 2 4 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
sync ; RDR 25 read sequence
ssm 0 ,0
SFDIAG ( 2 5 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
SFDIAG ( 2 6 ) ; RDR 26 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 2 6 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
SFDIAG ( 2 7 ) ; RDR 27 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 2 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
sync ; RDR 28 read sequence
ssm 0 ,0
SFDIAG ( 2 8 )
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
ssm 0 ,0
nop
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
nop
nop
nop
nop
nop
nop
nop
SFDIAG ( 3 0 ) ; RDR 30 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 3 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
SFDIAG ( 3 1 ) ; RDR 31 read sequence
ssm 0 ,0
MFDIAG_ 1 ( 2 8 )
shrpd r e t 0 ,% r0 ,% s a r ,% r1
MTDIAG_ 1 ( 1 )
STDIAG ( 3 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ i n _ U _ l e a v e
nop
perf_rdr_shift_in_U_leave :
bve ( % r2 )
.exit
MTDIAG_ 2 ( 2 4 ) ; restore DR2
.procend
2007-01-25 00:36:32 +03:00
ENDPROC( p e r f _ r d r _ s h i f t _ i n _ U )
2005-04-17 02:20:36 +04:00
;***********************************************************************
;*
;* Name: rdr_shift_out_U
;*
;* Description:
;* This routine moves data to the RDR's. The double-word that
;* arg1 points to is loaded and moved into the staging register.
;* Then the STDIAG instruction for the RDR # in arg0 is called
;* to move the data to the RDR.
;*
;* Arguments:
;* arg0 = rdr target
;* arg1 = buffer pointer
;*
;* Returns:
;* None
;*
;* Register usage:
;* arg0 = rdr target
;* arg1 = buffer pointer
;* %r24 - DR2 | DR2_SLOW_RET
;* %r23 - original DR2 value
;*
;***********************************************************************
2007-01-25 00:36:32 +03:00
ENTRY( p e r f _ r d r _ s h i f t _ o u t _ U )
2005-04-17 02:20:36 +04:00
.proc
.callinfo frame=0 ,N O _ C A L L S
.entry
;
; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
; shifting is done, from or to, the remote diagnose registers.
;
depdi,z 1 ,D R 2 _ S L O W _ R E T ,1 ,% r24
MFDIAG_ 2 ( 2 3 )
or % r24 ,% r23 ,% r24
MTDIAG_ 2 ( 2 4 ) ; set DR2_SLOW_RET
MTDIAG_ 1 ( 2 5 ) ; data to the staging register
shladd a r g 0 ,2 ,% r0 ,% r1 ; %r1 = 4 * RDR number
blr % r1 ,% r0 ; branch to 8-instruction sequence
nop
;
; 32-byte cachline aligned
;
sync ; RDR 0 write sequence
ssm 0 ,0
STDIAG ( 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 1 write sequence
ssm 0 ,0
STDIAG ( 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 2 write sequence
ssm 0 ,0
STDIAG ( 2 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 3 write sequence
ssm 0 ,0
STDIAG ( 3 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 4 write sequence
ssm 0 ,0
STDIAG ( 4 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 5 write sequence
ssm 0 ,0
STDIAG ( 5 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 6 write sequence
ssm 0 ,0
STDIAG ( 6 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 7 write sequence
ssm 0 ,0
STDIAG ( 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 8 write sequence
ssm 0 ,0
STDIAG ( 8 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 9 write sequence
ssm 0 ,0
STDIAG ( 9 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 10 write sequence
ssm 0 ,0
STDIAG ( 1 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 11 write sequence
ssm 0 ,0
STDIAG ( 1 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 12 write sequence
ssm 0 ,0
STDIAG ( 1 2 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 13 write sequence
ssm 0 ,0
STDIAG ( 1 3 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 14 write sequence
ssm 0 ,0
STDIAG ( 1 4 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 15 write sequence
ssm 0 ,0
STDIAG ( 1 5 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 16 write sequence
ssm 0 ,0
STDIAG ( 1 6 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 17 write sequence
ssm 0 ,0
STDIAG ( 1 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 18 write sequence
ssm 0 ,0
STDIAG ( 1 8 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 19 write sequence
ssm 0 ,0
STDIAG ( 1 9 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 20 write sequence
ssm 0 ,0
STDIAG ( 2 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 21 write sequence
ssm 0 ,0
STDIAG ( 2 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 22 write sequence
ssm 0 ,0
STDIAG ( 2 2 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 23 write sequence
ssm 0 ,0
STDIAG ( 2 3 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 24 write sequence
ssm 0 ,0
STDIAG ( 2 4 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 25 write sequence
ssm 0 ,0
STDIAG ( 2 5 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 26 write sequence
ssm 0 ,0
STDIAG ( 2 6 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 27 write sequence
ssm 0 ,0
STDIAG ( 2 7 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 28 write sequence
ssm 0 ,0
STDIAG ( 2 8 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 29 write sequence
ssm 0 ,0
STDIAG ( 2 9 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 30 write sequence
ssm 0 ,0
STDIAG ( 3 0 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
sync ; RDR 31 write sequence
ssm 0 ,0
STDIAG ( 3 1 )
ssm 0 ,0
b,n p e r f _ r d r _ s h i f t _ o u t _ U _ l e a v e
nop
ssm 0 ,0
nop
perf_rdr_shift_out_U_leave :
bve ( % r2 )
.exit
MTDIAG_ 2 ( 2 3 ) ; restore DR2
.procend
2007-01-25 00:36:32 +03:00
ENDPROC( p e r f _ r d r _ s h i f t _ o u t _ U )
2005-04-17 02:20:36 +04:00