License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 17:07:57 +03:00
// SPDX-License-Identifier: GPL-2.0
2005-04-17 02:20:36 +04:00
/*
* Low - Level PCI Support for PC - - Routing of Interrupts
*
* ( c ) 1999 - - 2000 Martin Mares < mj @ ucw . cz >
*/
# include <linux/types.h>
# include <linux/kernel.h>
# include <linux/pci.h>
# include <linux/init.h>
# include <linux/interrupt.h>
# include <linux/dmi.h>
2008-06-07 16:14:35 +04:00
# include <linux/io.h>
# include <linux/smp.h>
x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router
The ALi M1487 ISA Bus Controller (IBC), a part of the ALi FinALi 486
chipset, implements PCI interrupt steering with a PIRQ router[1] in the
form of four 4-bit mappings, spread across two PCI INTx Routing Table
Mapping Registers, available in the port I/O space accessible indirectly
via the index/data register pair at 0x22/0x23, located at indices 0x42
and 0x43 for the INT1/INT2 and INT3/INT4 lines respectively.
Additionally there is a separate PCI INTx Sensitivity Register at index
0x44 in the same port I/O space, whose bits 3:0 select the trigger mode
for INT[4:1] lines respectively[2]. Manufacturer's documentation says
that this register has to be set consistently with the relevant ELCR
register[3]. Add a router-specific hook then and use it to handle this
register.
Accesses to the port I/O space concerned here need to be unlocked by
writing the value of 0xc5 to the Lock Register at index 0x03
beforehand[4]. Do so then and then lock access after use for safety.
The IBC is implemented as a peer bridge on the host bus rather than a
southbridge on PCI and therefore it does not itself appear in the PCI
configuration space. It is complemented by the M1489 Cache-Memory PCI
Controller (CMP) host-to-PCI bridge, so use that device's identification
for determining the presence of the IBC.
References:
[1] "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
Inc., July 1997, Section 4: "Configuration Registers", pp. 76-77
[2] same, p. 77
[3] same, Section 5: "M1489/M1487 Software Programming Guide", pp.
99-100
[4] same, Section 4: "Configuration Registers", p. 37
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107191702020.9461@angie.orcam.me.uk
2021-07-20 06:27:54 +03:00
# include <linux/spinlock.h>
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# include <asm/io_apic.h>
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# include <linux/irq.h>
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# include <linux/acpi.h>
x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router
The ALi M1487 ISA Bus Controller (IBC), a part of the ALi FinALi 486
chipset, implements PCI interrupt steering with a PIRQ router[1] in the
form of four 4-bit mappings, spread across two PCI INTx Routing Table
Mapping Registers, available in the port I/O space accessible indirectly
via the index/data register pair at 0x22/0x23, located at indices 0x42
and 0x43 for the INT1/INT2 and INT3/INT4 lines respectively.
Additionally there is a separate PCI INTx Sensitivity Register at index
0x44 in the same port I/O space, whose bits 3:0 select the trigger mode
for INT[4:1] lines respectively[2]. Manufacturer's documentation says
that this register has to be set consistently with the relevant ELCR
register[3]. Add a router-specific hook then and use it to handle this
register.
Accesses to the port I/O space concerned here need to be unlocked by
writing the value of 0xc5 to the Lock Register at index 0x03
beforehand[4]. Do so then and then lock access after use for safety.
The IBC is implemented as a peer bridge on the host bus rather than a
southbridge on PCI and therefore it does not itself appear in the PCI
configuration space. It is complemented by the M1489 Cache-Memory PCI
Controller (CMP) host-to-PCI bridge, so use that device's identification
for determining the presence of the IBC.
References:
[1] "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
Inc., July 1997, Section 4: "Configuration Registers", pp. 76-77
[2] same, p. 77
[3] same, Section 5: "M1489/M1487 Software Programming Guide", pp.
99-100
[4] same, Section 4: "Configuration Registers", p. 37
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107191702020.9461@angie.orcam.me.uk
2021-07-20 06:27:54 +03:00
2021-07-20 06:28:09 +03:00
# include <asm/i8259.h>
x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router
The ALi M1487 ISA Bus Controller (IBC), a part of the ALi FinALi 486
chipset, implements PCI interrupt steering with a PIRQ router[1] in the
form of four 4-bit mappings, spread across two PCI INTx Routing Table
Mapping Registers, available in the port I/O space accessible indirectly
via the index/data register pair at 0x22/0x23, located at indices 0x42
and 0x43 for the INT1/INT2 and INT3/INT4 lines respectively.
Additionally there is a separate PCI INTx Sensitivity Register at index
0x44 in the same port I/O space, whose bits 3:0 select the trigger mode
for INT[4:1] lines respectively[2]. Manufacturer's documentation says
that this register has to be set consistently with the relevant ELCR
register[3]. Add a router-specific hook then and use it to handle this
register.
Accesses to the port I/O space concerned here need to be unlocked by
writing the value of 0xc5 to the Lock Register at index 0x03
beforehand[4]. Do so then and then lock access after use for safety.
The IBC is implemented as a peer bridge on the host bus rather than a
southbridge on PCI and therefore it does not itself appear in the PCI
configuration space. It is complemented by the M1489 Cache-Memory PCI
Controller (CMP) host-to-PCI bridge, so use that device's identification
for determining the presence of the IBC.
References:
[1] "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
Inc., July 1997, Section 4: "Configuration Registers", pp. 76-77
[2] same, p. 77
[3] same, Section 5: "M1489/M1487 Software Programming Guide", pp.
99-100
[4] same, Section 4: "Configuration Registers", p. 37
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107191702020.9461@angie.orcam.me.uk
2021-07-20 06:27:54 +03:00
# include <asm/pc-conf-reg.h>
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# include <asm/pci_x86.h>
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# define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
# define PIRQ_VERSION 0x0100
static int broken_hp_bios_irq9 ;
static int acer_tm360_irqrouting ;
static struct irq_routing_table * pirq_table ;
static int pirq_enable_irq ( struct pci_dev * dev ) ;
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static void pirq_disable_irq ( struct pci_dev * dev ) ;
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/*
* Never use : 0 , 1 , 2 ( timer , keyboard , and cascade )
* Avoid using : 13 , 14 and 15 ( FP error and IDE ) .
* Penalize : 3 , 4 , 6 , 7 , 12 ( known ISA uses : serial , floppy , parallel and mouse )
*/
unsigned int pcibios_irq_mask = 0xfff8 ;
static int pirq_penalty [ 16 ] = {
1000000 , 1000000 , 1000000 , 1000 , 1000 , 0 , 1000 , 1000 ,
0 , 0 , 0 , 0 , 1000 , 100000 , 100000 , 100000
} ;
struct irq_router {
char * name ;
u16 vendor , device ;
int ( * get ) ( struct pci_dev * router , struct pci_dev * dev , int pirq ) ;
2008-05-13 20:38:56 +04:00
int ( * set ) ( struct pci_dev * router , struct pci_dev * dev , int pirq ,
int new ) ;
x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router
The ALi M1487 ISA Bus Controller (IBC), a part of the ALi FinALi 486
chipset, implements PCI interrupt steering with a PIRQ router[1] in the
form of four 4-bit mappings, spread across two PCI INTx Routing Table
Mapping Registers, available in the port I/O space accessible indirectly
via the index/data register pair at 0x22/0x23, located at indices 0x42
and 0x43 for the INT1/INT2 and INT3/INT4 lines respectively.
Additionally there is a separate PCI INTx Sensitivity Register at index
0x44 in the same port I/O space, whose bits 3:0 select the trigger mode
for INT[4:1] lines respectively[2]. Manufacturer's documentation says
that this register has to be set consistently with the relevant ELCR
register[3]. Add a router-specific hook then and use it to handle this
register.
Accesses to the port I/O space concerned here need to be unlocked by
writing the value of 0xc5 to the Lock Register at index 0x03
beforehand[4]. Do so then and then lock access after use for safety.
The IBC is implemented as a peer bridge on the host bus rather than a
southbridge on PCI and therefore it does not itself appear in the PCI
configuration space. It is complemented by the M1489 Cache-Memory PCI
Controller (CMP) host-to-PCI bridge, so use that device's identification
for determining the presence of the IBC.
References:
[1] "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
Inc., July 1997, Section 4: "Configuration Registers", pp. 76-77
[2] same, p. 77
[3] same, Section 5: "M1489/M1487 Software Programming Guide", pp.
99-100
[4] same, Section 4: "Configuration Registers", p. 37
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107191702020.9461@angie.orcam.me.uk
2021-07-20 06:27:54 +03:00
int ( * lvl ) ( struct pci_dev * router , struct pci_dev * dev , int pirq ,
int irq ) ;
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} ;
struct irq_router_handler {
u16 vendor ;
int ( * probe ) ( struct irq_router * r , struct pci_dev * router , u16 device ) ;
} ;
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int ( * pcibios_enable_irq ) ( struct pci_dev * dev ) = pirq_enable_irq ;
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void ( * pcibios_disable_irq ) ( struct pci_dev * dev ) = pirq_disable_irq ;
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/*
* Check passed address for the PCI IRQ Routing Table signature
* and perform checksum verification .
*/
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static inline struct irq_routing_table * pirq_check_routing_table ( u8 * addr )
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{
struct irq_routing_table * rt ;
int i ;
u8 sum ;
rt = ( struct irq_routing_table * ) addr ;
if ( rt - > signature ! = PIRQ_SIGNATURE | |
rt - > version ! = PIRQ_VERSION | |
rt - > size % 16 | |
rt - > size < sizeof ( struct irq_routing_table ) )
return NULL ;
sum = 0 ;
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for ( i = 0 ; i < rt - > size ; i + + )
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sum + = addr [ i ] ;
if ( ! sum ) {
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DBG ( KERN_DEBUG " PCI: Interrupt Routing Table found at 0x%lx \n " ,
__pa ( rt ) ) ;
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return rt ;
}
return NULL ;
}
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/*
* Search 0xf0000 - - 0xfffff for the PCI IRQ Routing Table .
*/
static struct irq_routing_table * __init pirq_find_routing_table ( void )
{
u8 * addr ;
struct irq_routing_table * rt ;
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if ( pirq_table_addr ) {
rt = pirq_check_routing_table ( ( u8 * ) __va ( pirq_table_addr ) ) ;
if ( rt )
return rt ;
printk ( KERN_WARNING " PCI: PIRQ table NOT found at pirqaddr \n " ) ;
}
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for ( addr = ( u8 * ) __va ( 0xf0000 ) ; addr < ( u8 * ) __va ( 0x100000 ) ; addr + = 16 ) {
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rt = pirq_check_routing_table ( addr ) ;
if ( rt )
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return rt ;
}
return NULL ;
}
/*
* If we have a IRQ routing table , use it to search for peer host
* bridges . It ' s a gross hack , but since there are no other known
* ways how to get a list of buses , we have to go this way .
*/
static void __init pirq_peer_trick ( void )
{
struct irq_routing_table * rt = pirq_table ;
u8 busmap [ 256 ] ;
int i ;
struct irq_info * e ;
memset ( busmap , 0 , sizeof ( busmap ) ) ;
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for ( i = 0 ; i < ( rt - > size - sizeof ( struct irq_routing_table ) ) / sizeof ( struct irq_info ) ; i + + ) {
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e = & rt - > slots [ i ] ;
# ifdef DEBUG
{
int j ;
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DBG ( KERN_DEBUG " %02x:%02x.%x slot=%02x " ,
e - > bus , e - > devfn / 8 , e - > devfn % 8 , e - > slot ) ;
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for ( j = 0 ; j < 4 ; j + + )
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DBG ( " %d:%02x/%04x " , j , e - > irq [ j ] . link , e - > irq [ j ] . bitmap ) ;
DBG ( " \n " ) ;
}
# endif
busmap [ e - > bus ] = 1 ;
}
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for ( i = 1 ; i < 256 ; i + + ) {
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if ( ! busmap [ i ] | | pci_find_bus ( 0 , i ) )
continue ;
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pcibios_scan_root ( i ) ;
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}
pcibios_last_bus = - 1 ;
}
/*
* Code for querying and setting of IRQ routes on various interrupt routers .
2015-05-10 03:27:37 +03:00
* PIC Edge / Level Control Registers ( ELCR ) 0x4d0 & 0x4d1 .
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*/
2015-05-10 03:27:37 +03:00
void elcr_set_level_irq ( unsigned int irq )
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{
unsigned char mask = 1 < < ( irq & 7 ) ;
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unsigned int port = PIC_ELCR1 + ( irq > > 3 ) ;
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unsigned char val ;
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static u16 elcr_irq_mask ;
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2015-05-10 03:27:37 +03:00
if ( irq > = 16 | | ( 1 < < irq ) & elcr_irq_mask )
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return ;
2015-05-10 03:27:37 +03:00
elcr_irq_mask | = ( 1 < < irq ) ;
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printk ( KERN_DEBUG " PCI: setting IRQ %u as level-triggered \n " , irq ) ;
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val = inb ( port ) ;
if ( ! ( val & mask ) ) {
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DBG ( KERN_DEBUG " -> edge " ) ;
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outb ( val | mask , port ) ;
}
}
x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router
The ALi M1487 ISA Bus Controller (IBC), a part of the ALi FinALi 486
chipset, implements PCI interrupt steering with a PIRQ router[1] in the
form of four 4-bit mappings, spread across two PCI INTx Routing Table
Mapping Registers, available in the port I/O space accessible indirectly
via the index/data register pair at 0x22/0x23, located at indices 0x42
and 0x43 for the INT1/INT2 and INT3/INT4 lines respectively.
Additionally there is a separate PCI INTx Sensitivity Register at index
0x44 in the same port I/O space, whose bits 3:0 select the trigger mode
for INT[4:1] lines respectively[2]. Manufacturer's documentation says
that this register has to be set consistently with the relevant ELCR
register[3]. Add a router-specific hook then and use it to handle this
register.
Accesses to the port I/O space concerned here need to be unlocked by
writing the value of 0xc5 to the Lock Register at index 0x03
beforehand[4]. Do so then and then lock access after use for safety.
The IBC is implemented as a peer bridge on the host bus rather than a
southbridge on PCI and therefore it does not itself appear in the PCI
configuration space. It is complemented by the M1489 Cache-Memory PCI
Controller (CMP) host-to-PCI bridge, so use that device's identification
for determining the presence of the IBC.
References:
[1] "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
Inc., July 1997, Section 4: "Configuration Registers", pp. 76-77
[2] same, p. 77
[3] same, Section 5: "M1489/M1487 Software Programming Guide", pp.
99-100
[4] same, Section 4: "Configuration Registers", p. 37
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107191702020.9461@angie.orcam.me.uk
2021-07-20 06:27:54 +03:00
/*
* PIRQ routing for the M1487 ISA Bus Controller ( IBC ) ASIC used
* with the ALi FinALi 486 chipset . The IBC is not decoded in the
* PCI configuration space , so we identify it by the accompanying
* M1489 Cache - Memory PCI Controller ( CMP ) ASIC .
*
* There are four 4 - bit mappings provided , spread across two PCI
* INTx Routing Table Mapping Registers , available in the port I / O
* space accessible indirectly via the index / data register pair at
* 0x22 / 0x23 , located at indices 0x42 and 0x43 for the INT1 / INT2
* and INT3 / INT4 lines respectively . The INT1 / INT3 and INT2 / INT4
* lines are mapped in the low and the high 4 - bit nibble of the
* corresponding register as follows :
*
* 0000 : Disabled
* 0001 : IRQ9
* 0010 : IRQ3
* 0011 : IRQ10
* 0100 : IRQ4
* 0101 : IRQ5
* 0110 : IRQ7
* 0111 : IRQ6
* 1000 : Reserved
* 1001 : IRQ11
* 1010 : Reserved
* 1011 : IRQ12
* 1100 : Reserved
* 1101 : IRQ14
* 1110 : Reserved
* 1111 : IRQ15
*
* In addition to the usual ELCR register pair there is a separate
* PCI INTx Sensitivity Register at index 0x44 in the same port I / O
* space , whose bits 3 : 0 select the trigger mode for INT [ 4 : 1 ] lines
* respectively . Any bit set to 1 causes interrupts coming on the
* corresponding line to be passed to ISA as edge - triggered and
* otherwise they are passed as level - triggered . Manufacturer ' s
* documentation says this register has to be set consistently with
* the relevant ELCR register .
*
* Accesses to the port I / O space concerned here need to be unlocked
* by writing the value of 0xc5 to the Lock Register at index 0x03
* beforehand . Any other value written to said register prevents
* further accesses from reaching the register file , except for the
* Lock Register being written with 0xc5 again .
*
* References :
*
* " M1489/M1487: 486 PCI Chip Set " , Version 1.2 , Acer Laboratories
* Inc . , July 1997
*/
# define PC_CONF_FINALI_LOCK 0x03u
# define PC_CONF_FINALI_PCI_INTX_RT1 0x42u
# define PC_CONF_FINALI_PCI_INTX_RT2 0x43u
# define PC_CONF_FINALI_PCI_INTX_SENS 0x44u
# define PC_CONF_FINALI_LOCK_KEY 0xc5u
static u8 read_pc_conf_nybble ( u8 base , u8 index )
{
u8 reg = base + ( index > > 1 ) ;
u8 x ;
x = pc_conf_get ( reg ) ;
return index & 1 ? x > > 4 : x & 0xf ;
}
static void write_pc_conf_nybble ( u8 base , u8 index , u8 val )
{
u8 reg = base + ( index > > 1 ) ;
u8 x ;
x = pc_conf_get ( reg ) ;
x = index & 1 ? ( x & 0x0f ) | ( val < < 4 ) : ( x & 0xf0 ) | val ;
pc_conf_set ( reg , x ) ;
}
static int pirq_finali_get ( struct pci_dev * router , struct pci_dev * dev ,
int pirq )
{
static const u8 irqmap [ 16 ] = {
0 , 9 , 3 , 10 , 4 , 5 , 7 , 6 , 0 , 11 , 0 , 12 , 0 , 14 , 0 , 15
} ;
unsigned long flags ;
u8 x ;
raw_spin_lock_irqsave ( & pc_conf_lock , flags ) ;
pc_conf_set ( PC_CONF_FINALI_LOCK , PC_CONF_FINALI_LOCK_KEY ) ;
x = irqmap [ read_pc_conf_nybble ( PC_CONF_FINALI_PCI_INTX_RT1 , pirq - 1 ) ] ;
pc_conf_set ( PC_CONF_FINALI_LOCK , 0 ) ;
raw_spin_unlock_irqrestore ( & pc_conf_lock , flags ) ;
return x ;
}
static int pirq_finali_set ( struct pci_dev * router , struct pci_dev * dev ,
int pirq , int irq )
{
static const u8 irqmap [ 16 ] = {
0 , 0 , 0 , 2 , 4 , 5 , 7 , 6 , 0 , 1 , 3 , 9 , 11 , 0 , 13 , 15
} ;
u8 val = irqmap [ irq ] ;
unsigned long flags ;
if ( ! val )
return 0 ;
raw_spin_lock_irqsave ( & pc_conf_lock , flags ) ;
pc_conf_set ( PC_CONF_FINALI_LOCK , PC_CONF_FINALI_LOCK_KEY ) ;
write_pc_conf_nybble ( PC_CONF_FINALI_PCI_INTX_RT1 , pirq - 1 , val ) ;
pc_conf_set ( PC_CONF_FINALI_LOCK , 0 ) ;
raw_spin_unlock_irqrestore ( & pc_conf_lock , flags ) ;
return 1 ;
}
static int pirq_finali_lvl ( struct pci_dev * router , struct pci_dev * dev ,
int pirq , int irq )
{
u8 mask = ~ ( 1u < < ( pirq - 1 ) ) ;
unsigned long flags ;
u8 trig ;
elcr_set_level_irq ( irq ) ;
raw_spin_lock_irqsave ( & pc_conf_lock , flags ) ;
pc_conf_set ( PC_CONF_FINALI_LOCK , PC_CONF_FINALI_LOCK_KEY ) ;
trig = pc_conf_get ( PC_CONF_FINALI_PCI_INTX_SENS ) ;
trig & = mask ;
pc_conf_set ( PC_CONF_FINALI_PCI_INTX_SENS , trig ) ;
pc_conf_set ( PC_CONF_FINALI_LOCK , 0 ) ;
raw_spin_unlock_irqrestore ( & pc_conf_lock , flags ) ;
return 1 ;
}
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/*
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* Common IRQ routing practice : nibbles in config space ,
2005-04-17 02:20:36 +04:00
* offset by some magic constant .
*/
static unsigned int read_config_nybble ( struct pci_dev * router , unsigned offset , unsigned nr )
{
u8 x ;
unsigned reg = offset + ( nr > > 1 ) ;
pci_read_config_byte ( router , reg , & x ) ;
return ( nr & 1 ) ? ( x > > 4 ) : ( x & 0xf ) ;
}
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static void write_config_nybble ( struct pci_dev * router , unsigned offset ,
unsigned nr , unsigned int val )
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{
u8 x ;
unsigned reg = offset + ( nr > > 1 ) ;
pci_read_config_byte ( router , reg , & x ) ;
x = ( nr & 1 ) ? ( ( x & 0x0f ) | ( val < < 4 ) ) : ( ( x & 0xf0 ) | val ) ;
pci_write_config_byte ( router , reg , x ) ;
}
/*
* ALI pirq entries are damn ugly , and completely undocumented .
* This has been figured out from pirq tables , and it ' s not a pretty
* picture .
*/
static int pirq_ali_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
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static const unsigned char irqmap [ 16 ] = { 0 , 9 , 3 , 10 , 4 , 5 , 7 , 6 , 1 , 11 , 0 , 12 , 0 , 14 , 0 , 15 } ;
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WARN_ON_ONCE ( pirq > 16 ) ;
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return irqmap [ read_config_nybble ( router , 0x48 , pirq - 1 ) ] ;
}
static int pirq_ali_set ( struct pci_dev * router , struct pci_dev * dev , int pirq , int irq )
{
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static const unsigned char irqmap [ 16 ] = { 0 , 8 , 0 , 2 , 4 , 5 , 7 , 6 , 0 , 1 , 3 , 9 , 11 , 0 , 13 , 15 } ;
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unsigned int val = irqmap [ irq ] ;
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WARN_ON_ONCE ( pirq > 16 ) ;
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if ( val ) {
write_config_nybble ( router , 0x48 , pirq - 1 , val ) ;
return 1 ;
}
return 0 ;
}
x86/PCI: Add support for the Intel 82374EB/82374SB (ESC) PIRQ router
The Intel 82374EB/82374SB EISA System Component (ESC) devices implement
PCI interrupt steering with a PIRQ router[1] in the form of four PIRQ
Route Control registers, available in the port I/O space accessible
indirectly via the index/data register pair at 0x22/0x23, located at
indices 0x60/0x61/0x62/0x63 for the PIRQ0/1/2/3# lines respectively.
The semantics is the same as with the PIIX router, however it is not
clear if BIOSes use register indices or line numbers as the cookie to
identify PCI interrupts in their routing tables and therefore support
either scheme.
Accesses to the port I/O space concerned here need to be unlocked by
writing the value of 0x0f to the ESC ID Register at index 0x02
beforehand[2]. Do so then and then lock access after use for safety.
This locking could possibly interfere with accesses to the Intel MP spec
IMCR register, implemented by the 82374SB variant of the ESC only as the
PCI/APIC Control Register at index 0x70[3], for which leaving access to
the configuration space concerned unlocked may have been a requirement
for the BIOS to remain compliant with the MP spec. However we only poke
at the IMCR register if the APIC mode is used, in which case the PIRQ
router is not, so this arrangement is not going to interfere with IMCR
access code.
The ESC is implemented as a part of the combined southbridge also made
of 82375EB/82375SB PCI-EISA Bridge (PCEB) and does itself appear in the
PCI configuration space. Use the PCEB's device identification then for
determining the presence of the ESC.
References:
[1] "82374EB/82374SB EISA System Component (ESC)", Intel Corporation,
Order Number: 290476-004, March 1996, Section 3.1.12
"PIRQ[0:3]#--PIRQ Route Control Registers", pp. 44-45
[2] same, Section 3.1.1 "ESCID--ESC ID Register", p. 36
[3] same, Section 3.1.17 "PAC--PCI/APIC Control Register", p. 47
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107192023450.9461@angie.orcam.me.uk
2021-07-20 06:27:59 +03:00
/*
* PIRQ routing for the 82374 EB / 82374 SB EISA System Component ( ESC )
* ASIC used with the Intel 82420 and 82430 PCIsets . The ESC is not
* decoded in the PCI configuration space , so we identify it by the
* accompanying 82375 EB / 82375 SB PCI - EISA Bridge ( PCEB ) ASIC .
*
* There are four PIRQ Route Control registers , available in the
* port I / O space accessible indirectly via the index / data register
* pair at 0x22 / 0x23 , located at indices 0x60 / 0x61 / 0x62 / 0x63 for the
* PIRQ0 / 1 / 2 / 3 # lines respectively . The semantics is the same as
* with the PIIX router .
*
* Accesses to the port I / O space concerned here need to be unlocked
* by writing the value of 0x0f to the ESC ID Register at index 0x02
* beforehand . Any other value written to said register prevents
* further accesses from reaching the register file , except for the
* ESC ID Register being written with 0x0f again .
*
* References :
*
* " 82374EB/82374SB EISA System Component (ESC) " , Intel Corporation ,
* Order Number : 290476 - 004 , March 1996
*
* " 82375EB/82375SB PCI-EISA Bridge (PCEB) " , Intel Corporation , Order
* Number : 290477 - 004 , March 1996
*/
# define PC_CONF_I82374_ESC_ID 0x02u
# define PC_CONF_I82374_PIRQ_ROUTE_CONTROL 0x60u
# define PC_CONF_I82374_ESC_ID_KEY 0x0fu
static int pirq_esc_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
unsigned long flags ;
int reg ;
u8 x ;
reg = pirq ;
if ( reg > = 1 & & reg < = 4 )
reg + = PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1 ;
raw_spin_lock_irqsave ( & pc_conf_lock , flags ) ;
pc_conf_set ( PC_CONF_I82374_ESC_ID , PC_CONF_I82374_ESC_ID_KEY ) ;
x = pc_conf_get ( reg ) ;
pc_conf_set ( PC_CONF_I82374_ESC_ID , 0 ) ;
raw_spin_unlock_irqrestore ( & pc_conf_lock , flags ) ;
return ( x < 16 ) ? x : 0 ;
}
static int pirq_esc_set ( struct pci_dev * router , struct pci_dev * dev , int pirq ,
int irq )
{
unsigned long flags ;
int reg ;
reg = pirq ;
if ( reg > = 1 & & reg < = 4 )
reg + = PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1 ;
raw_spin_lock_irqsave ( & pc_conf_lock , flags ) ;
pc_conf_set ( PC_CONF_I82374_ESC_ID , PC_CONF_I82374_ESC_ID_KEY ) ;
pc_conf_set ( reg , irq ) ;
pc_conf_set ( PC_CONF_I82374_ESC_ID , 0 ) ;
raw_spin_unlock_irqrestore ( & pc_conf_lock , flags ) ;
return 1 ;
}
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/*
* The Intel PIIX4 pirq rules are fairly simple : " pirq " is
* just a pointer to the config space .
*/
static int pirq_piix_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
u8 x ;
pci_read_config_byte ( router , pirq , & x ) ;
return ( x < 16 ) ? x : 0 ;
}
static int pirq_piix_set ( struct pci_dev * router , struct pci_dev * dev , int pirq , int irq )
{
pci_write_config_byte ( router , pirq , irq ) ;
return 1 ;
}
x86/PCI: Add support for the Intel 82426EX PIRQ router
The Intel 82426EX ISA Bridge (IB), a part of the Intel 82420EX PCIset,
implements PCI interrupt steering with a PIRQ router in the form of two
PIRQ Route Control registers, available in the PCI configuration space
at locations 0x66 and 0x67 for the PIRQ0# and PIRQ1# lines respectively.
The semantics is the same as with the PIIX router, however it is not
clear if BIOSes use register indices or line numbers as the cookie to
identify PCI interrupts in their routing tables and therefore support
either scheme.
The IB is directly attached to the Intel 82425EX PCI System Controller
(PSC) component of the chipset via a dedicated PSC/IB Link interface
rather than the host bus or PCI. Therefore it does not itself appear in
the PCI configuration space even though it responds to configuration
cycles addressing registers it implements. Use 82425EX's identification
then for determining the presence of the IB.
References:
[1] "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC) and
82426EX ISA Bridge (IB)", Intel Corporation, Order Number:
290488-004, December 1995, Section 3.3.18 "PIRQ1RC/PIRQ0RC--PIRQ
Route Control Registers", p. 61
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107200213490.9461@angie.orcam.me.uk
2021-07-20 06:28:04 +03:00
/*
* PIRQ routing for the 82426 EX ISA Bridge ( IB ) ASIC used with the
* Intel 82420 EX PCIset .
*
* There are only two PIRQ Route Control registers , available in the
* combined 82425 EX / 82426 EX PCI configuration space , at 0x66 and 0x67
* for the PIRQ0 # and PIRQ1 # lines respectively . The semantics is
* the same as with the PIIX router .
*
* References :
*
* " 82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC)
* and 82426 EX ISA Bridge ( IB ) " , Intel Corporation, Order Number:
* 290488 - 004 , December 1995
*/
# define PCI_I82426EX_PIRQ_ROUTE_CONTROL 0x66u
static int pirq_ib_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
int reg ;
u8 x ;
reg = pirq ;
if ( reg > = 1 & & reg < = 2 )
reg + = PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1 ;
pci_read_config_byte ( router , reg , & x ) ;
return ( x < 16 ) ? x : 0 ;
}
static int pirq_ib_set ( struct pci_dev * router , struct pci_dev * dev , int pirq ,
int irq )
{
int reg ;
reg = pirq ;
if ( reg > = 1 & & reg < = 2 )
reg + = PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1 ;
pci_write_config_byte ( router , reg , irq ) ;
return 1 ;
}
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/*
* The VIA pirq rules are nibble - based , like ALI ,
* but without the ugly irq number munging .
* However , PIRQD is in the upper instead of lower 4 bits .
*/
static int pirq_via_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
return read_config_nybble ( router , 0x55 , pirq = = 4 ? 5 : pirq ) ;
}
static int pirq_via_set ( struct pci_dev * router , struct pci_dev * dev , int pirq , int irq )
{
write_config_nybble ( router , 0x55 , pirq = = 4 ? 5 : pirq , irq ) ;
return 1 ;
}
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/*
* The VIA pirq rules are nibble - based , like ALI ,
* but without the ugly irq number munging .
* However , for 82 C586 , nibble map is different .
*/
static int pirq_via586_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
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static const unsigned int pirqmap [ 5 ] = { 3 , 2 , 5 , 1 , 1 } ;
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WARN_ON_ONCE ( pirq > 5 ) ;
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return read_config_nybble ( router , 0x55 , pirqmap [ pirq - 1 ] ) ;
}
static int pirq_via586_set ( struct pci_dev * router , struct pci_dev * dev , int pirq , int irq )
{
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static const unsigned int pirqmap [ 5 ] = { 3 , 2 , 5 , 1 , 1 } ;
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WARN_ON_ONCE ( pirq > 5 ) ;
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write_config_nybble ( router , 0x55 , pirqmap [ pirq - 1 ] , irq ) ;
return 1 ;
}
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/*
* ITE 8330 G pirq rules are nibble - based
* FIXME : pirqmap may be { 1 , 0 , 3 , 2 } ,
* 2 + 3 are both mapped to irq 9 on my system
*/
static int pirq_ite_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
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static const unsigned char pirqmap [ 4 ] = { 1 , 0 , 2 , 3 } ;
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WARN_ON_ONCE ( pirq > 4 ) ;
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return read_config_nybble ( router , 0x43 , pirqmap [ pirq - 1 ] ) ;
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}
static int pirq_ite_set ( struct pci_dev * router , struct pci_dev * dev , int pirq , int irq )
{
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static const unsigned char pirqmap [ 4 ] = { 1 , 0 , 2 , 3 } ;
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2008-03-31 06:22:53 +04:00
WARN_ON_ONCE ( pirq > 4 ) ;
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write_config_nybble ( router , 0x43 , pirqmap [ pirq - 1 ] , irq ) ;
return 1 ;
}
/*
* OPTI : high four bits are nibble pointer . .
* I wonder what the low bits do ?
*/
static int pirq_opti_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
return read_config_nybble ( router , 0xb8 , pirq > > 4 ) ;
}
static int pirq_opti_set ( struct pci_dev * router , struct pci_dev * dev , int pirq , int irq )
{
write_config_nybble ( router , 0xb8 , pirq > > 4 , irq ) ;
return 1 ;
}
/*
* Cyrix : nibble offset 0x5C
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* 0x5C bits 7 : 4 is INTB bits 3 : 0 is INTA
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* 0x5D bits 7 : 4 is INTD bits 3 : 0 is INTC
*/
static int pirq_cyrix_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
return read_config_nybble ( router , 0x5C , ( pirq - 1 ) ^ 1 ) ;
}
static int pirq_cyrix_set ( struct pci_dev * router , struct pci_dev * dev , int pirq , int irq )
{
write_config_nybble ( router , 0x5C , ( pirq - 1 ) ^ 1 , irq ) ;
return 1 ;
}
/*
* PIRQ routing for SiS 85 C503 router used in several SiS chipsets .
* We have to deal with the following issues here :
* - vendors have different ideas about the meaning of link values
* - some onboard devices ( integrated in the chipset ) have special
* links and are thus routed differently ( i . e . not via PCI INTA - INTD )
* - different revision of the router have a different layout for
* the routing registers , particularly for the onchip devices
*
* For all routing registers the common thing is we have one byte
* per routeable link which is defined as :
* bit 7 IRQ mapping enabled ( 0 ) or disabled ( 1 )
* bits [ 6 : 4 ] reserved ( sometimes used for onchip devices )
* bits [ 3 : 0 ] IRQ to map to
* allowed : 3 - 7 , 9 - 12 , 14 - 15
* reserved : 0 , 1 , 2 , 8 , 13
*
* The config - space registers located at 0x41 / 0x42 / 0x43 / 0x44 are
* always used to route the normal PCI INT A / B / C / D respectively .
* Apparently there are systems implementing PCI routing table using
* link values 0x01 - 0x04 and others using 0x41 - 0x44 for PCI INTA . . D .
* We try our best to handle both link mappings .
2008-06-07 16:14:35 +04:00
*
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* Currently ( 2003 - 05 - 21 ) it appears most SiS chipsets follow the
* definition of routing registers from the SiS - 5595 southbridge .
* According to the SiS 5595 datasheets the revision id ' s of the
* router ( ISA - bridge ) should be 0x01 or 0xb0 .
*
* Furthermore we ' ve also seen lspci dumps with revision 0x00 and 0xb1 .
* Looks like these are used in a number of SiS 5 xx / 6 xx / 7 xx chipsets .
* They seem to work with the current routing code . However there is
* some concern because of the two USB - OHCI HCs ( original SiS 5595
* had only one ) . YMMV .
*
* Onchip routing for router rev - id 0x01 / 0xb0 and probably 0x00 / 0xb1 :
*
* 0x61 : IDEIRQ :
* bits [ 6 : 5 ] must be written 01
* bit 4 channel - select primary ( 0 ) , secondary ( 1 )
*
* 0x62 : USBIRQ :
* bit 6 OHCI function disabled ( 0 ) , enabled ( 1 )
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*
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* 0x6a : ACPI / SCI IRQ : bits 4 - 6 reserved
*
* 0x7e : Data Acq . Module IRQ - bits 4 - 6 reserved
*
* We support USBIRQ ( in addition to INTA - INTD ) and keep the
* IDE , ACPI and DAQ routing untouched as set by the BIOS .
*
* Currently the only reported exception is the new SiS 65 x chipset
* which includes the SiS 69 x southbridge . Here we have the 85 C503
* router revision 0x04 and there are changes in the register layout
* mostly related to the different USB HCs with USB 2.0 support .
*
* Onchip routing for router rev - id 0x04 ( try - and - error observation )
*
* 0x60 / 0x61 / 0x62 / 0x63 : 1 xEHCI and 3 xOHCI ( companion ) USB - HCs
* bit 6 - 4 are probably unused , not like 5595
*/
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# define PIRQ_SIS503_IRQ_MASK 0x0f
# define PIRQ_SIS503_IRQ_DISABLE 0x80
# define PIRQ_SIS503_USB_ENABLE 0x40
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static int pirq_sis503_get ( struct pci_dev * router , struct pci_dev * dev ,
int pirq )
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{
u8 x ;
int reg ;
reg = pirq ;
if ( reg > = 0x01 & & reg < = 0x04 )
reg + = 0x40 ;
pci_read_config_byte ( router , reg , & x ) ;
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return ( x & PIRQ_SIS503_IRQ_DISABLE ) ? 0 : ( x & PIRQ_SIS503_IRQ_MASK ) ;
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}
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static int pirq_sis503_set ( struct pci_dev * router , struct pci_dev * dev ,
int pirq , int irq )
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{
u8 x ;
int reg ;
reg = pirq ;
if ( reg > = 0x01 & & reg < = 0x04 )
reg + = 0x40 ;
pci_read_config_byte ( router , reg , & x ) ;
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x & = ~ ( PIRQ_SIS503_IRQ_MASK | PIRQ_SIS503_IRQ_DISABLE ) ;
x | = irq ? irq : PIRQ_SIS503_IRQ_DISABLE ;
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pci_write_config_byte ( router , reg , x ) ;
return 1 ;
}
/*
* VLSI : nibble offset 0x74 - educated guess due to routing table and
* config space of VLSI 82 C534 PCI - bridge / router ( 1004 : 0102 )
* Tested on HP OmniBook 800 covering PIRQ 1 , 2 , 4 , 8 for onboard
* devices , PIRQ 3 for non - pci ( ! ) soundchip and ( untested ) PIRQ 6
* for the busbridge to the docking station .
*/
static int pirq_vlsi_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
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WARN_ON_ONCE ( pirq > = 9 ) ;
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if ( pirq > 8 ) {
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dev_info ( & dev - > dev , " VLSI router PIRQ escape (%d) \n " , pirq ) ;
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return 0 ;
}
return read_config_nybble ( router , 0x74 , pirq - 1 ) ;
}
static int pirq_vlsi_set ( struct pci_dev * router , struct pci_dev * dev , int pirq , int irq )
{
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WARN_ON_ONCE ( pirq > = 9 ) ;
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if ( pirq > 8 ) {
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dev_info ( & dev - > dev , " VLSI router PIRQ escape (%d) \n " , pirq ) ;
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return 0 ;
}
write_config_nybble ( router , 0x74 , pirq - 1 , irq ) ;
return 1 ;
}
/*
* ServerWorks : PCI interrupts mapped to system IRQ lines through Index
* and Redirect I / O registers ( 0x0c00 and 0x0c01 ) . The Index register
* format is ( PCIIRQ # # | 0x10 ) , e . g . : PCIIRQ10 = 0x1a . The Redirect
* register is a straight binary coding of desired PIC IRQ ( low nibble ) .
*
* The ' link ' value in the PIRQ table is already in the correct format
* for the Index register . There are some special index values :
* 0x00 for ACPI ( SCI ) , 0x01 for USB , 0x02 for IDE0 , 0x04 for IDE1 ,
* and 0x03 for SMBus .
*/
static int pirq_serverworks_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
2008-01-30 15:33:14 +03:00
outb ( pirq , 0xc00 ) ;
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return inb ( 0xc01 ) & 0xf ;
}
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static int pirq_serverworks_set ( struct pci_dev * router , struct pci_dev * dev ,
int pirq , int irq )
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{
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outb ( pirq , 0xc00 ) ;
outb ( irq , 0xc01 ) ;
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return 1 ;
}
/* Support for AMD756 PCI IRQ Routing
* Jhon H . Caicedo < jhcaiced @ osso . org . co >
* Jun / 21 / 2001 0.2 .0 Release , fixed to use " nybble " functions . . . ( jhcaiced )
* Jun / 19 / 2001 Alpha Release 0.1 .0 ( jhcaiced )
* The AMD756 pirq rules are nibble - based
* offset 0x56 0 - 3 PIRQA 4 - 7 PIRQB
* offset 0x57 0 - 3 PIRQC 4 - 7 PIRQD
*/
static int pirq_amd756_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
u8 irq ;
irq = 0 ;
if ( pirq < = 4 )
irq = read_config_nybble ( router , 0x56 , pirq - 1 ) ;
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dev_info ( & dev - > dev ,
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" AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d \n " ,
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dev - > vendor , dev - > device , pirq , irq ) ;
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return irq ;
}
static int pirq_amd756_set ( struct pci_dev * router , struct pci_dev * dev , int pirq , int irq )
{
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dev_info ( & dev - > dev ,
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" AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d \n " ,
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dev - > vendor , dev - > device , pirq , irq ) ;
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if ( pirq < = 4 )
write_config_nybble ( router , 0x56 , pirq - 1 , irq ) ;
return 1 ;
}
2007-08-11 01:42:15 +04:00
/*
* PicoPower PT86C523
*/
static int pirq_pico_get ( struct pci_dev * router , struct pci_dev * dev , int pirq )
{
outb ( 0x10 + ( ( pirq - 1 ) > > 1 ) , 0x24 ) ;
return ( ( pirq - 1 ) & 1 ) ? ( inb ( 0x26 ) > > 4 ) : ( inb ( 0x26 ) & 0xf ) ;
}
static int pirq_pico_set ( struct pci_dev * router , struct pci_dev * dev , int pirq ,
int irq )
{
unsigned int x ;
outb ( 0x10 + ( ( pirq - 1 ) > > 1 ) , 0x24 ) ;
x = inb ( 0x26 ) ;
x = ( ( pirq - 1 ) & 1 ) ? ( ( x & 0x0f ) | ( irq < < 4 ) ) : ( ( x & 0xf0 ) | ( irq ) ) ;
outb ( x , 0x26 ) ;
return 1 ;
}
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# ifdef CONFIG_PCI_BIOS
static int pirq_bios_set ( struct pci_dev * router , struct pci_dev * dev , int pirq , int irq )
{
struct pci_dev * bridge ;
int pin = pci_get_interrupt_pin ( dev , & bridge ) ;
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return pcibios_set_irq_routing ( bridge , pin - 1 , irq ) ;
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}
# endif
static __init int intel_router_probe ( struct irq_router * r , struct pci_dev * router , u16 device )
{
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static struct pci_device_id __initdata pirq_440gx [ ] = {
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{ PCI_DEVICE ( PCI_VENDOR_ID_INTEL , PCI_DEVICE_ID_INTEL_82443GX_0 ) } ,
{ PCI_DEVICE ( PCI_VENDOR_ID_INTEL , PCI_DEVICE_ID_INTEL_82443GX_2 ) } ,
{ } ,
} ;
/* 440GX has a proprietary PIRQ router -- don't use it */
if ( pci_dev_present ( pirq_440gx ) )
return 0 ;
2008-06-07 16:14:35 +04:00
switch ( device ) {
x86/PCI: Add support for the Intel 82374EB/82374SB (ESC) PIRQ router
The Intel 82374EB/82374SB EISA System Component (ESC) devices implement
PCI interrupt steering with a PIRQ router[1] in the form of four PIRQ
Route Control registers, available in the port I/O space accessible
indirectly via the index/data register pair at 0x22/0x23, located at
indices 0x60/0x61/0x62/0x63 for the PIRQ0/1/2/3# lines respectively.
The semantics is the same as with the PIIX router, however it is not
clear if BIOSes use register indices or line numbers as the cookie to
identify PCI interrupts in their routing tables and therefore support
either scheme.
Accesses to the port I/O space concerned here need to be unlocked by
writing the value of 0x0f to the ESC ID Register at index 0x02
beforehand[2]. Do so then and then lock access after use for safety.
This locking could possibly interfere with accesses to the Intel MP spec
IMCR register, implemented by the 82374SB variant of the ESC only as the
PCI/APIC Control Register at index 0x70[3], for which leaving access to
the configuration space concerned unlocked may have been a requirement
for the BIOS to remain compliant with the MP spec. However we only poke
at the IMCR register if the APIC mode is used, in which case the PIRQ
router is not, so this arrangement is not going to interfere with IMCR
access code.
The ESC is implemented as a part of the combined southbridge also made
of 82375EB/82375SB PCI-EISA Bridge (PCEB) and does itself appear in the
PCI configuration space. Use the PCEB's device identification then for
determining the presence of the ESC.
References:
[1] "82374EB/82374SB EISA System Component (ESC)", Intel Corporation,
Order Number: 290476-004, March 1996, Section 3.1.12
"PIRQ[0:3]#--PIRQ Route Control Registers", pp. 44-45
[2] same, Section 3.1.1 "ESCID--ESC ID Register", p. 36
[3] same, Section 3.1.17 "PAC--PCI/APIC Control Register", p. 47
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107192023450.9461@angie.orcam.me.uk
2021-07-20 06:27:59 +03:00
case PCI_DEVICE_ID_INTEL_82375 :
r - > name = " PCEB/ESC " ;
r - > get = pirq_esc_get ;
r - > set = pirq_esc_set ;
return 1 ;
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case PCI_DEVICE_ID_INTEL_82371FB_0 :
case PCI_DEVICE_ID_INTEL_82371SB_0 :
case PCI_DEVICE_ID_INTEL_82371AB_0 :
case PCI_DEVICE_ID_INTEL_82371MX :
case PCI_DEVICE_ID_INTEL_82443MX_0 :
case PCI_DEVICE_ID_INTEL_82801AA_0 :
case PCI_DEVICE_ID_INTEL_82801AB_0 :
case PCI_DEVICE_ID_INTEL_82801BA_0 :
case PCI_DEVICE_ID_INTEL_82801BA_10 :
case PCI_DEVICE_ID_INTEL_82801CA_0 :
case PCI_DEVICE_ID_INTEL_82801CA_12 :
case PCI_DEVICE_ID_INTEL_82801DB_0 :
case PCI_DEVICE_ID_INTEL_82801E_0 :
case PCI_DEVICE_ID_INTEL_82801EB_0 :
case PCI_DEVICE_ID_INTEL_ESB_1 :
case PCI_DEVICE_ID_INTEL_ICH6_0 :
case PCI_DEVICE_ID_INTEL_ICH6_1 :
case PCI_DEVICE_ID_INTEL_ICH7_0 :
case PCI_DEVICE_ID_INTEL_ICH7_1 :
case PCI_DEVICE_ID_INTEL_ICH7_30 :
case PCI_DEVICE_ID_INTEL_ICH7_31 :
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case PCI_DEVICE_ID_INTEL_TGP_LPC :
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case PCI_DEVICE_ID_INTEL_ESB2_0 :
case PCI_DEVICE_ID_INTEL_ICH8_0 :
case PCI_DEVICE_ID_INTEL_ICH8_1 :
case PCI_DEVICE_ID_INTEL_ICH8_2 :
case PCI_DEVICE_ID_INTEL_ICH8_3 :
case PCI_DEVICE_ID_INTEL_ICH8_4 :
case PCI_DEVICE_ID_INTEL_ICH9_0 :
case PCI_DEVICE_ID_INTEL_ICH9_1 :
case PCI_DEVICE_ID_INTEL_ICH9_2 :
case PCI_DEVICE_ID_INTEL_ICH9_3 :
case PCI_DEVICE_ID_INTEL_ICH9_4 :
case PCI_DEVICE_ID_INTEL_ICH9_5 :
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case PCI_DEVICE_ID_INTEL_EP80579_0 :
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case PCI_DEVICE_ID_INTEL_ICH10_0 :
case PCI_DEVICE_ID_INTEL_ICH10_1 :
case PCI_DEVICE_ID_INTEL_ICH10_2 :
case PCI_DEVICE_ID_INTEL_ICH10_3 :
2010-11-17 22:12:08 +03:00
case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0 :
case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1 :
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r - > name = " PIIX/ICH " ;
r - > get = pirq_piix_get ;
r - > set = pirq_piix_set ;
return 1 ;
x86/PCI: Add support for the Intel 82426EX PIRQ router
The Intel 82426EX ISA Bridge (IB), a part of the Intel 82420EX PCIset,
implements PCI interrupt steering with a PIRQ router in the form of two
PIRQ Route Control registers, available in the PCI configuration space
at locations 0x66 and 0x67 for the PIRQ0# and PIRQ1# lines respectively.
The semantics is the same as with the PIIX router, however it is not
clear if BIOSes use register indices or line numbers as the cookie to
identify PCI interrupts in their routing tables and therefore support
either scheme.
The IB is directly attached to the Intel 82425EX PCI System Controller
(PSC) component of the chipset via a dedicated PSC/IB Link interface
rather than the host bus or PCI. Therefore it does not itself appear in
the PCI configuration space even though it responds to configuration
cycles addressing registers it implements. Use 82425EX's identification
then for determining the presence of the IB.
References:
[1] "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC) and
82426EX ISA Bridge (IB)", Intel Corporation, Order Number:
290488-004, December 1995, Section 3.3.18 "PIRQ1RC/PIRQ0RC--PIRQ
Route Control Registers", p. 61
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107200213490.9461@angie.orcam.me.uk
2021-07-20 06:28:04 +03:00
case PCI_DEVICE_ID_INTEL_82425 :
r - > name = " PSC/IB " ;
r - > get = pirq_ib_get ;
r - > set = pirq_ib_set ;
return 1 ;
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}
2008-08-29 02:40:59 +04:00
2011-01-11 00:08:37 +03:00
if ( ( device > = PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN & &
device < = PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX )
| | ( device > = PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN & &
device < = PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX )
| | ( device > = PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN & &
2011-04-20 03:35:15 +04:00
device < = PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX )
| | ( device > = PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN & &
device < = PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX ) ) {
2008-08-29 02:40:59 +04:00
r - > name = " PIIX/ICH " ;
r - > get = pirq_piix_get ;
r - > set = pirq_piix_set ;
return 1 ;
}
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return 0 ;
}
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static __init int via_router_probe ( struct irq_router * r ,
struct pci_dev * router , u16 device )
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{
/* FIXME: We should move some of the quirk fixup stuff here */
2005-07-28 12:07:33 +04:00
2005-10-31 01:59:36 +03:00
/*
2007-10-20 03:13:56 +04:00
* workarounds for some buggy BIOSes
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*/
if ( device = = PCI_DEVICE_ID_VIA_82C586_0 ) {
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switch ( router - > device ) {
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case PCI_DEVICE_ID_VIA_82C686 :
/*
* Asus k7m bios wrongly reports 82 C686A
* as 586 - compatible
*/
device = PCI_DEVICE_ID_VIA_82C686 ;
break ;
case PCI_DEVICE_ID_VIA_8235 :
/**
* Asus a7v - x bios wrongly reports 8235
* as 586 - compatible
*/
device = PCI_DEVICE_ID_VIA_8235 ;
break ;
2008-06-06 02:31:22 +04:00
case PCI_DEVICE_ID_VIA_8237 :
/**
* Asus a7v600 bios wrongly reports 8237
* as 586 - compatible
*/
device = PCI_DEVICE_ID_VIA_8237 ;
break ;
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}
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}
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switch ( device ) {
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case PCI_DEVICE_ID_VIA_82C586_0 :
r - > name = " VIA " ;
r - > get = pirq_via586_get ;
r - > set = pirq_via586_set ;
return 1 ;
case PCI_DEVICE_ID_VIA_82C596 :
case PCI_DEVICE_ID_VIA_82C686 :
case PCI_DEVICE_ID_VIA_8231 :
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case PCI_DEVICE_ID_VIA_8233A :
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case PCI_DEVICE_ID_VIA_8235 :
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case PCI_DEVICE_ID_VIA_8237 :
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/* FIXME: add new ones for 8233/5 */
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r - > name = " VIA " ;
r - > get = pirq_via_get ;
r - > set = pirq_via_set ;
return 1 ;
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}
return 0 ;
}
static __init int vlsi_router_probe ( struct irq_router * r , struct pci_dev * router , u16 device )
{
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switch ( device ) {
case PCI_DEVICE_ID_VLSI_82C534 :
r - > name = " VLSI 82C534 " ;
r - > get = pirq_vlsi_get ;
r - > set = pirq_vlsi_set ;
return 1 ;
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}
return 0 ;
}
2008-05-13 20:38:56 +04:00
static __init int serverworks_router_probe ( struct irq_router * r ,
struct pci_dev * router , u16 device )
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{
2008-06-07 16:14:35 +04:00
switch ( device ) {
case PCI_DEVICE_ID_SERVERWORKS_OSB4 :
case PCI_DEVICE_ID_SERVERWORKS_CSB5 :
r - > name = " ServerWorks " ;
r - > get = pirq_serverworks_get ;
r - > set = pirq_serverworks_set ;
return 1 ;
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}
return 0 ;
}
static __init int sis_router_probe ( struct irq_router * r , struct pci_dev * router , u16 device )
{
2022-03-31 10:10:39 +03:00
switch ( device ) {
case PCI_DEVICE_ID_SI_503 :
r - > name = " SiS85C503 " ;
r - > get = pirq_sis503_get ;
r - > set = pirq_sis503_set ;
return 1 ;
}
return 0 ;
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}
static __init int cyrix_router_probe ( struct irq_router * r , struct pci_dev * router , u16 device )
{
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switch ( device ) {
case PCI_DEVICE_ID_CYRIX_5520 :
r - > name = " NatSemi " ;
r - > get = pirq_cyrix_get ;
r - > set = pirq_cyrix_set ;
return 1 ;
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}
return 0 ;
}
static __init int opti_router_probe ( struct irq_router * r , struct pci_dev * router , u16 device )
{
2008-06-07 16:14:35 +04:00
switch ( device ) {
case PCI_DEVICE_ID_OPTI_82C700 :
r - > name = " OPTI " ;
r - > get = pirq_opti_get ;
r - > set = pirq_opti_set ;
return 1 ;
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}
return 0 ;
}
static __init int ite_router_probe ( struct irq_router * r , struct pci_dev * router , u16 device )
{
2008-06-07 16:14:35 +04:00
switch ( device ) {
case PCI_DEVICE_ID_ITE_IT8330G_0 :
r - > name = " ITE " ;
r - > get = pirq_ite_get ;
r - > set = pirq_ite_set ;
return 1 ;
2005-04-17 02:20:36 +04:00
}
return 0 ;
}
static __init int ali_router_probe ( struct irq_router * r , struct pci_dev * router , u16 device )
{
2008-06-07 16:14:35 +04:00
switch ( device ) {
x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router
The ALi M1487 ISA Bus Controller (IBC), a part of the ALi FinALi 486
chipset, implements PCI interrupt steering with a PIRQ router[1] in the
form of four 4-bit mappings, spread across two PCI INTx Routing Table
Mapping Registers, available in the port I/O space accessible indirectly
via the index/data register pair at 0x22/0x23, located at indices 0x42
and 0x43 for the INT1/INT2 and INT3/INT4 lines respectively.
Additionally there is a separate PCI INTx Sensitivity Register at index
0x44 in the same port I/O space, whose bits 3:0 select the trigger mode
for INT[4:1] lines respectively[2]. Manufacturer's documentation says
that this register has to be set consistently with the relevant ELCR
register[3]. Add a router-specific hook then and use it to handle this
register.
Accesses to the port I/O space concerned here need to be unlocked by
writing the value of 0xc5 to the Lock Register at index 0x03
beforehand[4]. Do so then and then lock access after use for safety.
The IBC is implemented as a peer bridge on the host bus rather than a
southbridge on PCI and therefore it does not itself appear in the PCI
configuration space. It is complemented by the M1489 Cache-Memory PCI
Controller (CMP) host-to-PCI bridge, so use that device's identification
for determining the presence of the IBC.
References:
[1] "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
Inc., July 1997, Section 4: "Configuration Registers", pp. 76-77
[2] same, p. 77
[3] same, Section 5: "M1489/M1487 Software Programming Guide", pp.
99-100
[4] same, Section 4: "Configuration Registers", p. 37
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107191702020.9461@angie.orcam.me.uk
2021-07-20 06:27:54 +03:00
case PCI_DEVICE_ID_AL_M1489 :
r - > name = " FinALi " ;
r - > get = pirq_finali_get ;
r - > set = pirq_finali_set ;
r - > lvl = pirq_finali_lvl ;
return 1 ;
2005-04-17 02:20:36 +04:00
case PCI_DEVICE_ID_AL_M1533 :
case PCI_DEVICE_ID_AL_M1563 :
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r - > name = " ALI " ;
r - > get = pirq_ali_get ;
r - > set = pirq_ali_set ;
return 1 ;
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}
return 0 ;
}
static __init int amd_router_probe ( struct irq_router * r , struct pci_dev * router , u16 device )
{
2008-06-07 16:14:35 +04:00
switch ( device ) {
case PCI_DEVICE_ID_AMD_VIPER_740B :
r - > name = " AMD756 " ;
break ;
case PCI_DEVICE_ID_AMD_VIPER_7413 :
r - > name = " AMD766 " ;
break ;
case PCI_DEVICE_ID_AMD_VIPER_7443 :
r - > name = " AMD768 " ;
break ;
default :
return 0 ;
2005-04-17 02:20:36 +04:00
}
r - > get = pirq_amd756_get ;
r - > set = pirq_amd756_set ;
return 1 ;
}
2008-06-07 16:14:35 +04:00
2007-08-11 01:42:15 +04:00
static __init int pico_router_probe ( struct irq_router * r , struct pci_dev * router , u16 device )
{
switch ( device ) {
case PCI_DEVICE_ID_PICOPOWER_PT86C523 :
r - > name = " PicoPower PT86C523 " ;
r - > get = pirq_pico_get ;
r - > set = pirq_pico_set ;
return 1 ;
case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP :
r - > name = " PicoPower PT86C523 rev. BB+ " ;
r - > get = pirq_pico_get ;
r - > set = pirq_pico_set ;
return 1 ;
}
return 0 ;
}
2005-04-17 02:20:36 +04:00
static __initdata struct irq_router_handler pirq_routers [ ] = {
{ PCI_VENDOR_ID_INTEL , intel_router_probe } ,
{ PCI_VENDOR_ID_AL , ali_router_probe } ,
{ PCI_VENDOR_ID_ITE , ite_router_probe } ,
{ PCI_VENDOR_ID_VIA , via_router_probe } ,
{ PCI_VENDOR_ID_OPTI , opti_router_probe } ,
{ PCI_VENDOR_ID_SI , sis_router_probe } ,
{ PCI_VENDOR_ID_CYRIX , cyrix_router_probe } ,
{ PCI_VENDOR_ID_VLSI , vlsi_router_probe } ,
{ PCI_VENDOR_ID_SERVERWORKS , serverworks_router_probe } ,
{ PCI_VENDOR_ID_AMD , amd_router_probe } ,
2007-08-11 01:42:15 +04:00
{ PCI_VENDOR_ID_PICOPOWER , pico_router_probe } ,
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/* Someone with docs needs to add the ATI Radeon IGP */
{ 0 , NULL }
} ;
static struct irq_router pirq_router ;
static struct pci_dev * pirq_router_dev ;
/*
* FIXME : should we have an option to say " generic for
* chipset " ?
*/
2008-06-07 16:14:35 +04:00
2005-04-17 02:20:36 +04:00
static void __init pirq_find_router ( struct irq_router * r )
{
struct irq_routing_table * rt = pirq_table ;
struct irq_router_handler * h ;
# ifdef CONFIG_PCI_BIOS
if ( ! rt - > signature ) {
printk ( KERN_INFO " PCI: Using BIOS for IRQ routing \n " ) ;
r - > set = pirq_bios_set ;
r - > name = " BIOS " ;
return ;
}
# endif
/* Default unless a driver reloads it */
r - > name = " default " ;
r - > get = NULL ;
r - > set = NULL ;
2008-06-07 16:14:35 +04:00
2008-08-26 01:44:59 +04:00
DBG ( KERN_DEBUG " PCI: Attempting to find IRQ router for [%04x:%04x] \n " ,
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rt - > rtr_vendor , rt - > rtr_device ) ;
2017-12-19 08:37:39 +03:00
pirq_router_dev = pci_get_domain_bus_and_slot ( 0 , rt - > rtr_bus ,
rt - > rtr_devfn ) ;
2005-04-17 02:20:36 +04:00
if ( ! pirq_router_dev ) {
2005-12-01 20:01:28 +03:00
DBG ( KERN_DEBUG " PCI: Interrupt router not found at "
" %02x:%02x \n " , rt - > rtr_bus , rt - > rtr_devfn ) ;
2005-04-17 02:20:36 +04:00
return ;
}
2008-06-07 16:14:35 +04:00
for ( h = pirq_routers ; h - > vendor ; h + + ) {
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/* First look for a router match */
2008-05-13 20:38:56 +04:00
if ( rt - > rtr_vendor = = h - > vendor & &
h - > probe ( r , pirq_router_dev , rt - > rtr_device ) )
2005-04-17 02:20:36 +04:00
break ;
/* Fall back to a device match */
2008-05-13 20:38:56 +04:00
if ( pirq_router_dev - > vendor = = h - > vendor & &
h - > probe ( r , pirq_router_dev , pirq_router_dev - > device ) )
2005-04-17 02:20:36 +04:00
break ;
}
2008-08-26 01:44:59 +04:00
dev_info ( & pirq_router_dev - > dev , " %s IRQ router [%04x:%04x] \n " ,
2008-07-24 03:00:13 +04:00
pirq_router . name ,
pirq_router_dev - > vendor , pirq_router_dev - > device ) ;
2006-12-07 04:14:03 +03:00
/* The device remains referenced for the kernel lifetime */
2005-04-17 02:20:36 +04:00
}
x86/PCI: Also match function number in $PIR table
Contrary to the PCI BIOS specification[1] some systems include the PCI
function number for onboard devices in their $PIR table. Consequently
the wrong entry can be matched leading to interrupt routing failures.
For example the Tyan Tomcat IV S1564D board has:
00:07.1 slot=00
0:00/deb8
1:00/deb8
2:00/deb8
3:00/deb8
00:07.2 slot=00
0:00/deb8
1:00/deb8
2:00/deb8
3:63/deb8
for its IDE interface and USB controller functions of the 82371SB PIIX3
southbridge. Consequently the first entry matches causing the inability
to route the USB interrupt in the `noapic' mode, in which case we need
to rely on the interrupt line set by the BIOS:
uhci_hcd 0000:00:07.2: runtime IRQ mapping not provided by arch
uhci_hcd 0000:00:07.2: PCI INT D not routed
uhci_hcd 0000:00:07.2: enabling bus mastering
uhci_hcd 0000:00:07.2: UHCI Host Controller
uhci_hcd 0000:00:07.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:07.2: irq 11, io base 0x00006000
Try to match the PCI device and function combined then and if that fails
move on to PCI device matching only. Compliant systems will only have a
single $PIR table entry per PCI device, so this update does not change
the semantics with them, while systems that have several entries for
individual functions of a single PCI device each will match the correct
entry:
uhci_hcd 0000:00:07.2: runtime IRQ mapping not provided by arch
uhci_hcd 0000:00:07.2: PCI INT D -> PIRQ 63, mask deb8, excl 0c20
uhci_hcd 0000:00:07.2: PCI INT D -> newirq 11
uhci_hcd 0000:00:07.2: found PCI INT D -> IRQ 11
uhci_hcd 0000:00:07.2: sharing IRQ 11 with 0000:00:11.0
uhci_hcd 0000:00:07.2: enabling bus mastering
uhci_hcd 0000:00:07.2: UHCI Host Controller
uhci_hcd 0000:00:07.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:07.2: irq 11, io base 0x00006000
[1] "PCI BIOS Specification", Revision 2.1, PCI Special Interest Group,
August 26, 1994, Table 4-1 "Layout of IRQ routing table entry.", p.
12
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301536020.22465@angie.orcam.me.uk
2022-03-31 10:10:21 +03:00
/*
* We ' re supposed to match on the PCI device only and not the function ,
* but some BIOSes build their tables with the PCI function included
* for motherboard devices , so if a complete match is found , then give
* it precedence over a slot match .
*/
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
static struct irq_info * pirq_get_dev_info ( struct pci_dev * dev )
2005-04-17 02:20:36 +04:00
{
struct irq_routing_table * rt = pirq_table ;
2008-05-13 20:38:56 +04:00
int entries = ( rt - > size - sizeof ( struct irq_routing_table ) ) /
sizeof ( struct irq_info ) ;
x86/PCI: Also match function number in $PIR table
Contrary to the PCI BIOS specification[1] some systems include the PCI
function number for onboard devices in their $PIR table. Consequently
the wrong entry can be matched leading to interrupt routing failures.
For example the Tyan Tomcat IV S1564D board has:
00:07.1 slot=00
0:00/deb8
1:00/deb8
2:00/deb8
3:00/deb8
00:07.2 slot=00
0:00/deb8
1:00/deb8
2:00/deb8
3:63/deb8
for its IDE interface and USB controller functions of the 82371SB PIIX3
southbridge. Consequently the first entry matches causing the inability
to route the USB interrupt in the `noapic' mode, in which case we need
to rely on the interrupt line set by the BIOS:
uhci_hcd 0000:00:07.2: runtime IRQ mapping not provided by arch
uhci_hcd 0000:00:07.2: PCI INT D not routed
uhci_hcd 0000:00:07.2: enabling bus mastering
uhci_hcd 0000:00:07.2: UHCI Host Controller
uhci_hcd 0000:00:07.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:07.2: irq 11, io base 0x00006000
Try to match the PCI device and function combined then and if that fails
move on to PCI device matching only. Compliant systems will only have a
single $PIR table entry per PCI device, so this update does not change
the semantics with them, while systems that have several entries for
individual functions of a single PCI device each will match the correct
entry:
uhci_hcd 0000:00:07.2: runtime IRQ mapping not provided by arch
uhci_hcd 0000:00:07.2: PCI INT D -> PIRQ 63, mask deb8, excl 0c20
uhci_hcd 0000:00:07.2: PCI INT D -> newirq 11
uhci_hcd 0000:00:07.2: found PCI INT D -> IRQ 11
uhci_hcd 0000:00:07.2: sharing IRQ 11 with 0000:00:11.0
uhci_hcd 0000:00:07.2: enabling bus mastering
uhci_hcd 0000:00:07.2: UHCI Host Controller
uhci_hcd 0000:00:07.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:07.2: irq 11, io base 0x00006000
[1] "PCI BIOS Specification", Revision 2.1, PCI Special Interest Group,
August 26, 1994, Table 4-1 "Layout of IRQ routing table entry.", p.
12
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301536020.22465@angie.orcam.me.uk
2022-03-31 10:10:21 +03:00
struct irq_info * slotinfo = NULL ;
2005-04-17 02:20:36 +04:00
struct irq_info * info ;
for ( info = rt - > slots ; entries - - ; info + + )
x86/PCI: Also match function number in $PIR table
Contrary to the PCI BIOS specification[1] some systems include the PCI
function number for onboard devices in their $PIR table. Consequently
the wrong entry can be matched leading to interrupt routing failures.
For example the Tyan Tomcat IV S1564D board has:
00:07.1 slot=00
0:00/deb8
1:00/deb8
2:00/deb8
3:00/deb8
00:07.2 slot=00
0:00/deb8
1:00/deb8
2:00/deb8
3:63/deb8
for its IDE interface and USB controller functions of the 82371SB PIIX3
southbridge. Consequently the first entry matches causing the inability
to route the USB interrupt in the `noapic' mode, in which case we need
to rely on the interrupt line set by the BIOS:
uhci_hcd 0000:00:07.2: runtime IRQ mapping not provided by arch
uhci_hcd 0000:00:07.2: PCI INT D not routed
uhci_hcd 0000:00:07.2: enabling bus mastering
uhci_hcd 0000:00:07.2: UHCI Host Controller
uhci_hcd 0000:00:07.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:07.2: irq 11, io base 0x00006000
Try to match the PCI device and function combined then and if that fails
move on to PCI device matching only. Compliant systems will only have a
single $PIR table entry per PCI device, so this update does not change
the semantics with them, while systems that have several entries for
individual functions of a single PCI device each will match the correct
entry:
uhci_hcd 0000:00:07.2: runtime IRQ mapping not provided by arch
uhci_hcd 0000:00:07.2: PCI INT D -> PIRQ 63, mask deb8, excl 0c20
uhci_hcd 0000:00:07.2: PCI INT D -> newirq 11
uhci_hcd 0000:00:07.2: found PCI INT D -> IRQ 11
uhci_hcd 0000:00:07.2: sharing IRQ 11 with 0000:00:11.0
uhci_hcd 0000:00:07.2: enabling bus mastering
uhci_hcd 0000:00:07.2: UHCI Host Controller
uhci_hcd 0000:00:07.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:07.2: irq 11, io base 0x00006000
[1] "PCI BIOS Specification", Revision 2.1, PCI Special Interest Group,
August 26, 1994, Table 4-1 "Layout of IRQ routing table entry.", p.
12
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301536020.22465@angie.orcam.me.uk
2022-03-31 10:10:21 +03:00
if ( info - > bus = = dev - > bus - > number ) {
if ( info - > devfn = = dev - > devfn )
return info ;
if ( ! slotinfo & &
PCI_SLOT ( info - > devfn ) = = PCI_SLOT ( dev - > devfn ) )
slotinfo = info ;
}
return slotinfo ;
2005-04-17 02:20:36 +04:00
}
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
/*
* Buses behind bridges are typically not listed in the PIRQ routing table .
* Do the usual dance then and walk the tree of bridges up adjusting the
* pin number accordingly on the way until the originating root bus device
* has been reached and then use its routing information .
*/
static struct irq_info * pirq_get_info ( struct pci_dev * dev , u8 * pin )
{
struct pci_dev * temp_dev = dev ;
struct irq_info * info ;
u8 temp_pin = * pin ;
u8 dpin = temp_pin ;
info = pirq_get_dev_info ( dev ) ;
while ( ! info & & temp_dev - > bus - > parent ) {
struct pci_dev * bridge = temp_dev - > bus - > self ;
temp_pin = pci_swizzle_interrupt_pin ( temp_dev , temp_pin ) ;
info = pirq_get_dev_info ( bridge ) ;
if ( info )
dev_warn ( & dev - > dev ,
" using bridge %s INT %c to get INT %c \n " ,
pci_name ( bridge ) ,
' A ' + temp_pin - 1 , ' A ' + dpin - 1 ) ;
temp_dev = bridge ;
}
* pin = temp_pin ;
return info ;
}
2005-04-17 02:20:36 +04:00
static int pcibios_lookup_irq ( struct pci_dev * dev , int assign )
{
struct irq_info * info ;
int i , pirq , newirq ;
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
u8 dpin , pin ;
2005-04-17 02:20:36 +04:00
int irq = 0 ;
u32 mask ;
struct irq_router * r = & pirq_router ;
struct pci_dev * dev2 = NULL ;
char * msg = NULL ;
/* Find IRQ pin */
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
pci_read_config_byte ( dev , PCI_INTERRUPT_PIN , & dpin ) ;
if ( ! dpin ) {
2008-07-24 03:00:13 +04:00
dev_dbg ( & dev - > dev , " no interrupt pin \n " ) ;
2005-04-17 02:20:36 +04:00
return 0 ;
}
2009-05-06 21:10:06 +04:00
if ( io_apic_assign_pci_irqs )
return 0 ;
2005-04-17 02:20:36 +04:00
/* Find IRQ routing entry */
if ( ! pirq_table )
return 0 ;
2008-06-07 16:14:35 +04:00
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
pin = dpin ;
info = pirq_get_info ( dev , & pin ) ;
2005-04-17 02:20:36 +04:00
if ( ! info ) {
2008-07-24 03:00:13 +04:00
dev_dbg ( & dev - > dev , " PCI INT %c not found in routing table \n " ,
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
' A ' + dpin - 1 ) ;
2005-04-17 02:20:36 +04:00
return 0 ;
}
2008-12-10 02:11:51 +03:00
pirq = info - > irq [ pin - 1 ] . link ;
mask = info - > irq [ pin - 1 ] . bitmap ;
2005-04-17 02:20:36 +04:00
if ( ! pirq ) {
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
dev_dbg ( & dev - > dev , " PCI INT %c not routed \n " , ' A ' + dpin - 1 ) ;
2005-04-17 02:20:36 +04:00
return 0 ;
}
2008-07-24 03:00:13 +04:00
dev_dbg ( & dev - > dev , " PCI INT %c -> PIRQ %02x, mask %04x, excl %04x " ,
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
' A ' + dpin - 1 , pirq , mask , pirq_table - > exclusive_irqs ) ;
2005-04-17 02:20:36 +04:00
mask & = pcibios_irq_mask ;
/* Work around broken HP Pavilion Notebooks which assign USB to
IRQ 9 even though it is actually wired to IRQ 11 */
if ( broken_hp_bios_irq9 & & pirq = = 0x59 & & dev - > irq = = 9 ) {
dev - > irq = 11 ;
pci_write_config_byte ( dev , PCI_INTERRUPT_LINE , 11 ) ;
r - > set ( pirq_router_dev , dev , pirq , 11 ) ;
}
/* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
2008-05-13 20:38:56 +04:00
if ( acer_tm360_irqrouting & & dev - > irq = = 11 & &
dev - > vendor = = PCI_VENDOR_ID_O2 ) {
2005-04-17 02:20:36 +04:00
pirq = 0x68 ;
mask = 0x400 ;
dev - > irq = r - > get ( pirq_router_dev , dev , pirq ) ;
pci_write_config_byte ( dev , PCI_INTERRUPT_LINE , dev - > irq ) ;
}
/*
* Find the best IRQ to assign : use the one
* reported by the device if possible .
*/
newirq = dev - > irq ;
2006-01-06 19:43:16 +03:00
if ( newirq & & ! ( ( 1 < < newirq ) & mask ) ) {
2008-06-07 16:14:35 +04:00
if ( pci_probe & PCI_USE_PIRQ_MASK )
newirq = 0 ;
else
2008-07-24 03:00:13 +04:00
dev_warn ( & dev - > dev , " IRQ %d doesn't match PIRQ mask "
" %#x; try pci=usepirqmask \n " , newirq , mask ) ;
2005-04-17 02:20:36 +04:00
}
if ( ! newirq & & assign ) {
for ( i = 0 ; i < 16 ; i + + ) {
if ( ! ( mask & ( 1 < < i ) ) )
continue ;
2008-05-13 20:38:56 +04:00
if ( pirq_penalty [ i ] < pirq_penalty [ newirq ] & &
can_request_irq ( i , IRQF_SHARED ) )
2005-04-17 02:20:36 +04:00
newirq = i ;
}
}
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
dev_dbg ( & dev - > dev , " PCI INT %c -> newirq %d " , ' A ' + dpin - 1 , newirq ) ;
2005-04-17 02:20:36 +04:00
/* Check if it is hardcoded */
if ( ( pirq & 0xf0 ) = = 0xf0 ) {
irq = pirq & 0xf ;
2008-07-24 03:00:13 +04:00
msg = " hardcoded " ;
2008-06-07 16:14:35 +04:00
} else if ( r - > get & & ( irq = r - > get ( pirq_router_dev , dev , pirq ) ) & & \
( ( ! ( pci_probe & PCI_USE_PIRQ_MASK ) ) | | ( ( 1 < < irq ) & mask ) ) ) {
2008-07-24 03:00:13 +04:00
msg = " found " ;
x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router
The ALi M1487 ISA Bus Controller (IBC), a part of the ALi FinALi 486
chipset, implements PCI interrupt steering with a PIRQ router[1] in the
form of four 4-bit mappings, spread across two PCI INTx Routing Table
Mapping Registers, available in the port I/O space accessible indirectly
via the index/data register pair at 0x22/0x23, located at indices 0x42
and 0x43 for the INT1/INT2 and INT3/INT4 lines respectively.
Additionally there is a separate PCI INTx Sensitivity Register at index
0x44 in the same port I/O space, whose bits 3:0 select the trigger mode
for INT[4:1] lines respectively[2]. Manufacturer's documentation says
that this register has to be set consistently with the relevant ELCR
register[3]. Add a router-specific hook then and use it to handle this
register.
Accesses to the port I/O space concerned here need to be unlocked by
writing the value of 0xc5 to the Lock Register at index 0x03
beforehand[4]. Do so then and then lock access after use for safety.
The IBC is implemented as a peer bridge on the host bus rather than a
southbridge on PCI and therefore it does not itself appear in the PCI
configuration space. It is complemented by the M1489 Cache-Memory PCI
Controller (CMP) host-to-PCI bridge, so use that device's identification
for determining the presence of the IBC.
References:
[1] "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
Inc., July 1997, Section 4: "Configuration Registers", pp. 76-77
[2] same, p. 77
[3] same, Section 5: "M1489/M1487 Software Programming Guide", pp.
99-100
[4] same, Section 4: "Configuration Registers", p. 37
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107191702020.9461@angie.orcam.me.uk
2021-07-20 06:27:54 +03:00
if ( r - > lvl )
r - > lvl ( pirq_router_dev , dev , pirq , irq ) ;
else
elcr_set_level_irq ( irq ) ;
2008-05-13 20:38:56 +04:00
} else if ( newirq & & r - > set & &
( dev - > class > > 8 ) ! = PCI_CLASS_DISPLAY_VGA ) {
2005-04-17 02:20:36 +04:00
if ( r - > set ( pirq_router_dev , dev , pirq , newirq ) ) {
x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router
The ALi M1487 ISA Bus Controller (IBC), a part of the ALi FinALi 486
chipset, implements PCI interrupt steering with a PIRQ router[1] in the
form of four 4-bit mappings, spread across two PCI INTx Routing Table
Mapping Registers, available in the port I/O space accessible indirectly
via the index/data register pair at 0x22/0x23, located at indices 0x42
and 0x43 for the INT1/INT2 and INT3/INT4 lines respectively.
Additionally there is a separate PCI INTx Sensitivity Register at index
0x44 in the same port I/O space, whose bits 3:0 select the trigger mode
for INT[4:1] lines respectively[2]. Manufacturer's documentation says
that this register has to be set consistently with the relevant ELCR
register[3]. Add a router-specific hook then and use it to handle this
register.
Accesses to the port I/O space concerned here need to be unlocked by
writing the value of 0xc5 to the Lock Register at index 0x03
beforehand[4]. Do so then and then lock access after use for safety.
The IBC is implemented as a peer bridge on the host bus rather than a
southbridge on PCI and therefore it does not itself appear in the PCI
configuration space. It is complemented by the M1489 Cache-Memory PCI
Controller (CMP) host-to-PCI bridge, so use that device's identification
for determining the presence of the IBC.
References:
[1] "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
Inc., July 1997, Section 4: "Configuration Registers", pp. 76-77
[2] same, p. 77
[3] same, Section 5: "M1489/M1487 Software Programming Guide", pp.
99-100
[4] same, Section 4: "Configuration Registers", p. 37
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107191702020.9461@angie.orcam.me.uk
2021-07-20 06:27:54 +03:00
if ( r - > lvl )
r - > lvl ( pirq_router_dev , dev , pirq , newirq ) ;
else
elcr_set_level_irq ( newirq ) ;
2008-07-24 03:00:13 +04:00
msg = " assigned " ;
2005-04-17 02:20:36 +04:00
irq = newirq ;
}
}
if ( ! irq ) {
if ( newirq & & mask = = ( 1 < < newirq ) ) {
2008-07-24 03:00:13 +04:00
msg = " guessed " ;
2005-04-17 02:20:36 +04:00
irq = newirq ;
2008-07-24 03:00:13 +04:00
} else {
dev_dbg ( & dev - > dev , " can't route interrupt \n " ) ;
2005-04-17 02:20:36 +04:00
return 0 ;
2008-07-24 03:00:13 +04:00
}
2005-04-17 02:20:36 +04:00
}
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
dev_info ( & dev - > dev , " %s PCI INT %c -> IRQ %d \n " ,
msg , ' A ' + dpin - 1 , irq ) ;
2005-04-17 02:20:36 +04:00
/* Update IRQ for all devices with the same pirq value */
2010-07-03 20:04:03 +04:00
for_each_pci_dev ( dev2 ) {
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
pci_read_config_byte ( dev2 , PCI_INTERRUPT_PIN , & dpin ) ;
if ( ! dpin )
2005-04-17 02:20:36 +04:00
continue ;
2008-12-10 02:11:51 +03:00
x86/PCI: Handle IRQ swizzling with PIRQ routers
Similarly to MP-tables PIRQ routing tables may not list devices behind
PCI-to-PCI bridges, leading to interrupt routing failures, e.g.:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: PCI INT A not found in routing table
pci 0000:02:01.0: PCI INT A not found in routing table
pci 0000:02:02.0: PCI INT A not found in routing table
pci 0000:04:00.0: PCI INT A not found in routing table
pci 0000:04:00.3: PCI INT D not found in routing table
pci 0000:06:05.0: PCI INT A not found in routing table
pci 0000:06:08.0: PCI INT A not found in routing table
pci 0000:06:08.1: PCI INT B not found in routing table
pci 0000:06:08.2: PCI INT C not found in routing table
and consequently non-working devices. Since PCI-to-PCI bridges have a
standardised way of routing interrupts by the means of swizzling do it
for configurations that use a PIRQ router as well, like with APIC-based
setups, and use the determined corresponding topmost bridge's interrupt
pin assignment to route a given device's interrupt:
pci 0000:00:07.0: PIIX/ICH IRQ router [8086:7000]
pci 0000:02:00.0: ignoring bogus IRQ 255
pci 0000:02:01.0: ignoring bogus IRQ 255
pci 0000:02:02.0: ignoring bogus IRQ 255
pci 0000:04:00.0: ignoring bogus IRQ 255
pci 0000:04:00.3: ignoring bogus IRQ 255
pci 0000:00:11.0: PCI INT A -> PIRQ 63, mask deb8, excl 0c20
pci 0000:00:11.0: PCI INT A -> newirq 0
PCI: setting IRQ 11 as level-triggered
pci 0000:00:11.0: found PCI INT A -> IRQ 11
pci 0000:00:11.0: sharing IRQ 11 with 0000:00:07.2
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:00:11.0: sharing IRQ 11 with 0000:02:00.0
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:00:11.0: sharing IRQ 11 with 0000:04:00.3
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:00:11.0: sharing IRQ 11 with 0000:06:08.2
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: PCI INT A -> PIRQ 60, mask deb8, excl 0c20
pci 0000:02:01.0: PCI INT A -> newirq 0
PCI: setting IRQ 10 as level-triggered
pci 0000:02:01.0: found PCI INT A -> IRQ 10
pci 0000:02:01.0: sharing IRQ 10 with 0000:00:14.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:01.0: sharing IRQ 10 with 0000:04:00.0
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: PCI INT A -> PIRQ 61, mask deb8, excl 0c20
pci 0000:02:02.0: PCI INT A -> newirq 0
PCI: setting IRQ 5 as level-triggered
pci 0000:02:02.0: found PCI INT A -> IRQ 5
pci 0000:02:02.0: sharing IRQ 5 with 0000:00:13.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:02:02.0: sharing IRQ 5 with 0000:06:08.0
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:05.0: PCI INT A -> PIRQ 62, mask deb8, excl 0c20
pci 0000:06:05.0: PCI INT A -> newirq 0
pci 0000:06:05.0: found PCI INT A -> IRQ 5
pci 0000:06:05.0: sharing IRQ 5 with 0000:00:12.0
pci 0000:02:00.0: using bridge 0000:00:11.0 INT A to get INT A
pci 0000:02:01.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:02:02.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:04:00.0: using bridge 0000:00:11.0 INT B to get INT A
pci 0000:04:00.3: using bridge 0000:00:11.0 INT A to get INT D
pci 0000:06:05.0: using bridge 0000:00:11.0 INT D to get INT A
pci 0000:06:08.0: using bridge 0000:00:11.0 INT C to get INT A
pci 0000:06:08.1: using bridge 0000:00:11.0 INT D to get INT B
pci 0000:06:05.0: sharing IRQ 5 with 0000:06:08.1
pci 0000:06:08.2: using bridge 0000:00:11.0 INT A to get INT C
Adjust log messages accordingly.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301538440.22465@angie.orcam.me.uk
2022-03-31 10:10:25 +03:00
pin = dpin ;
info = pirq_get_info ( dev2 , & pin ) ;
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if ( ! info )
continue ;
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if ( info - > irq [ pin - 1 ] . link = = pirq ) {
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/*
* We refuse to override the dev - > irq
* information . Give a warning !
*/
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if ( dev2 - > irq & & dev2 - > irq ! = irq & & \
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( ! ( pci_probe & PCI_USE_PIRQ_MASK ) | | \
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( ( 1 < < dev2 - > irq ) & mask ) ) ) {
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# ifndef CONFIG_PCI_MSI
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dev_info ( & dev2 - > dev , " IRQ routing conflict: "
" have IRQ %d, want IRQ %d \n " ,
dev2 - > irq , irq ) ;
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# endif
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continue ;
}
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dev2 - > irq = irq ;
pirq_penalty [ irq ] + + ;
if ( dev ! = dev2 )
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dev_info ( & dev - > dev , " sharing IRQ %d with %s \n " ,
irq , pci_name ( dev2 ) ) ;
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}
}
return 1 ;
}
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void __init pcibios_fixup_irqs ( void )
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{
struct pci_dev * dev = NULL ;
u8 pin ;
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DBG ( KERN_DEBUG " PCI: IRQ fixup \n " ) ;
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for_each_pci_dev ( dev ) {
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/*
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* If the BIOS has set an out of range IRQ number , just
* ignore it . Also keep track of which IRQ ' s are
* already in use .
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*/
if ( dev - > irq > = 16 ) {
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dev_dbg ( & dev - > dev , " ignoring bogus IRQ %d \n " , dev - > irq ) ;
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dev - > irq = 0 ;
}
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/*
* If the IRQ is already assigned to a PCI device ,
* ignore its ISA use penalty
*/
if ( pirq_penalty [ dev - > irq ] > = 100 & &
pirq_penalty [ dev - > irq ] < 100000 )
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pirq_penalty [ dev - > irq ] = 0 ;
pirq_penalty [ dev - > irq ] + + ;
}
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if ( io_apic_assign_pci_irqs )
return ;
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dev = NULL ;
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for_each_pci_dev ( dev ) {
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pci_read_config_byte ( dev , PCI_INTERRUPT_PIN , & pin ) ;
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if ( ! pin )
continue ;
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/*
* Still no IRQ ? Try to lookup one . . .
*/
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if ( ! dev - > irq )
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pcibios_lookup_irq ( dev , 0 ) ;
}
}
/*
* Work around broken HP Pavilion Notebooks which assign USB to
* IRQ 9 even though it is actually wired to IRQ 11
*/
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static int __init fix_broken_hp_bios_irq9 ( const struct dmi_system_id * d )
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{
if ( ! broken_hp_bios_irq9 ) {
broken_hp_bios_irq9 = 1 ;
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printk ( KERN_INFO " %s detected - fixing broken IRQ routing \n " ,
d - > ident ) ;
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}
return 0 ;
}
/*
* Work around broken Acer TravelMate 360 Notebooks which assign
* Cardbus to IRQ 11 even though it is actually wired to IRQ 10
*/
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static int __init fix_acer_tm360_irqrouting ( const struct dmi_system_id * d )
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{
if ( ! acer_tm360_irqrouting ) {
acer_tm360_irqrouting = 1 ;
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printk ( KERN_INFO " %s detected - fixing broken IRQ routing \n " ,
d - > ident ) ;
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}
return 0 ;
}
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static const struct dmi_system_id pciirq_dmi_table [ ] __initconst = {
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{
. callback = fix_broken_hp_bios_irq9 ,
. ident = " HP Pavilion N5400 Series Laptop " ,
. matches = {
DMI_MATCH ( DMI_SYS_VENDOR , " Hewlett-Packard " ) ,
DMI_MATCH ( DMI_BIOS_VERSION , " GE.M1.03 " ) ,
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DMI_MATCH ( DMI_PRODUCT_VERSION ,
" HP Pavilion Notebook Model GE " ) ,
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DMI_MATCH ( DMI_BOARD_VERSION , " OmniBook N32N-736 " ) ,
} ,
} ,
{
. callback = fix_acer_tm360_irqrouting ,
. ident = " Acer TravelMate 36x Laptop " ,
. matches = {
DMI_MATCH ( DMI_SYS_VENDOR , " Acer " ) ,
DMI_MATCH ( DMI_PRODUCT_NAME , " TravelMate 360 " ) ,
} ,
} ,
{ }
} ;
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void __init pcibios_irq_init ( void )
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{
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struct irq_routing_table * rtable = NULL ;
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DBG ( KERN_DEBUG " PCI: IRQ init \n " ) ;
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if ( raw_pci_ops = = NULL )
return ;
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dmi_check_system ( pciirq_dmi_table ) ;
pirq_table = pirq_find_routing_table ( ) ;
# ifdef CONFIG_PCI_BIOS
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if ( ! pirq_table & & ( pci_probe & PCI_BIOS_IRQ_SCAN ) ) {
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pirq_table = pcibios_get_irq_routing_table ( ) ;
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rtable = pirq_table ;
}
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# endif
if ( pirq_table ) {
pirq_peer_trick ( ) ;
pirq_find_router ( & pirq_router ) ;
if ( pirq_table - > exclusive_irqs ) {
int i ;
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for ( i = 0 ; i < 16 ; i + + )
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if ( ! ( pirq_table - > exclusive_irqs & ( 1 < < i ) ) )
pirq_penalty [ i ] + = 100 ;
}
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/*
* If we ' re using the I / O APIC , avoid using the PCI IRQ
* routing table
*/
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if ( io_apic_assign_pci_irqs ) {
kfree ( rtable ) ;
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pirq_table = NULL ;
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}
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}
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x86_init . pci . fixup_irqs ( ) ;
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if ( io_apic_assign_pci_irqs & & pci_routeirq ) {
struct pci_dev * dev = NULL ;
/*
* PCI IRQ routing is set up by pci_enable_device ( ) , but we
* also do it here in case there are still broken drivers that
* don ' t use pci_enable_device ( ) .
*/
printk ( KERN_INFO " PCI: Routing PCI interrupts for all devices because \" pci=routeirq \" specified \n " ) ;
for_each_pci_dev ( dev )
pirq_enable_irq ( dev ) ;
}
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}
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static void pirq_penalize_isa_irq ( int irq , int active )
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{
/*
* If any ISAPnP device reports an IRQ in its list of possible
* IRQ ' s , we try to avoid assigning it to PCI devices .
*/
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if ( irq < 16 ) {
if ( active )
pirq_penalty [ irq ] + = 1000 ;
else
pirq_penalty [ irq ] + = 100 ;
}
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}
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void pcibios_penalize_isa_irq ( int irq , int active )
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{
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# ifdef CONFIG_ACPI
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if ( ! acpi_noirq )
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acpi_penalize_isa_irq ( irq , active ) ;
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else
# endif
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pirq_penalize_isa_irq ( irq , active ) ;
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}
static int pirq_enable_irq ( struct pci_dev * dev )
{
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u8 pin = 0 ;
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pci_read_config_byte ( dev , PCI_INTERRUPT_PIN , & pin ) ;
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if ( pin & & ! pcibios_lookup_irq ( dev , 1 ) ) {
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char * msg = " " ;
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if ( ! io_apic_assign_pci_irqs & & dev - > irq )
return 0 ;
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if ( io_apic_assign_pci_irqs ) {
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# ifdef CONFIG_X86_IO_APIC
struct pci_dev * temp_dev ;
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int irq ;
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if ( dev - > irq_managed & & dev - > irq > 0 )
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return 0 ;
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irq = IO_APIC_get_PCI_irq_vector ( dev - > bus - > number ,
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PCI_SLOT ( dev - > devfn ) , pin - 1 ) ;
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/*
* Busses behind bridges are typically not listed in the MP - table .
* In this case we have to look up the IRQ based on the parent bus ,
* parent slot , and pin number . The SMP code detects such bridged
* busses itself so we should get into this branch reliably .
*/
temp_dev = dev ;
while ( irq < 0 & & dev - > bus - > parent ) { /* go back to the bridge */
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struct pci_dev * bridge = dev - > bus - > self ;
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pin = pci_swizzle_interrupt_pin ( dev , pin ) ;
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irq = IO_APIC_get_PCI_irq_vector ( bridge - > bus - > number ,
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PCI_SLOT ( bridge - > devfn ) ,
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pin - 1 ) ;
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if ( irq > = 0 )
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dev_warn ( & dev - > dev , " using bridge %s "
" INT %c to get IRQ %d \n " ,
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pci_name ( bridge ) , ' A ' + pin - 1 ,
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irq ) ;
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dev = bridge ;
}
dev = temp_dev ;
if ( irq > = 0 ) {
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dev - > irq_managed = 1 ;
dev - > irq = irq ;
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dev_info ( & dev - > dev , " PCI->APIC IRQ transform: "
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" INT %c -> IRQ %d \n " , ' A ' + pin - 1 , irq ) ;
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return 0 ;
} else
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msg = " ; probably buggy MP table " ;
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# endif
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} else if ( pci_probe & PCI_BIOS_IRQ_SCAN )
msg = " " ;
else
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msg = " ; please try using pci=biosirq " ;
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/*
* With IDE legacy devices the IRQ lookup failure is not
* a problem . .
*/
if ( dev - > class > > 8 = = PCI_CLASS_STORAGE_IDE & &
! ( dev - > class & 0x5 ) )
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return 0 ;
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dev_warn ( & dev - > dev , " can't find IRQ for PCI INT %c%s \n " ,
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' A ' + pin - 1 , msg ) ;
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}
return 0 ;
}
2014-06-09 12:20:08 +04:00
2016-02-17 21:26:42 +03:00
bool mp_should_keep_irq ( struct device * dev )
{
if ( dev - > power . is_prepared )
return true ;
# ifdef CONFIG_PM
if ( dev - > power . runtime_status = = RPM_SUSPENDING )
return true ;
# endif
return false ;
}
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static void pirq_disable_irq ( struct pci_dev * dev )
{
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if ( io_apic_assign_pci_irqs & & ! mp_should_keep_irq ( & dev - > dev ) & &
dev - > irq_managed & & dev - > irq ) {
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mp_unmap_irq ( dev - > irq ) ;
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dev - > irq = 0 ;
dev - > irq_managed = 0 ;
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}
}