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linux/drivers/phy/qualcomm/phy-qcom-qmp.h

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phy: qcom-qmp: Use the correct style for SPDX License Identifier This patch corrects the SPDX License Identifier style in header files related to PHY drivers for Qualcomm platforms. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used). Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-11-27 17:02:33 +03:00
/* SPDX-License-Identifier: GPL-2.0 */
phy: qcom-qmp: Move register offsets to header file New revision (v3) of QMP PHY uses different offsets for almost all of the registers. Hence, move these definitions to header file so that updated offsets can be added for QMP v3. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:05 +03:00
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#ifndef QCOM_PHY_QMP_H_
#define QCOM_PHY_QMP_H_
phy: qcom-qmp: move QSERDES registers to separate header Move QSERDES V2 registers to the separate header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-9-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:43:00 +03:00
#include "phy-qcom-qmp-qserdes-com.h"
#include "phy-qcom-qmp-qserdes-txrx.h"
phy: qcom-qmp: move QSERDES V3 registers to separate headers Move QSERDES V3 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-10-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:43:01 +03:00
#include "phy-qcom-qmp-qserdes-com-v3.h"
#include "phy-qcom-qmp-qserdes-txrx-v3.h"
phy: qcom-qmp: move QSERDES V4 registers to separate headers Move QSERDES V4 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-11-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:43:02 +03:00
#include "phy-qcom-qmp-qserdes-com-v4.h"
#include "phy-qcom-qmp-qserdes-txrx-v4.h"
phy: qcom-qmp: move QSERDES V5 registers to separate headers Move QSERDES V5 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-12-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:43:03 +03:00
#include "phy-qcom-qmp-qserdes-com-v5.h"
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
phy: qcom-qmp: move QSERDES PLL registers to separate header Move QSERDES PLL registers to the separate header. This register set is unique for the IPQ PCIe Gen3 PHYs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-13-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:43:04 +03:00
#include "phy-qcom-qmp-qserdes-pll.h"
phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx Based on code from downstream Codeaurora tree. The ipq60xx has one gen3 PCIe port. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/e24f2bedb8a7346018b58136bcb0a4004d8677a0.1620203062.git.baruch@tkos.co.il Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-05 12:18:31 +03:00
phy: qcom-qmp: move PCS V2 registers to separate header Move PCS V2 registers to the separate header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-14-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:43:05 +03:00
#include "phy-qcom-qmp-pcs-v2.h"
phy: qcom-qmp: Move register offsets to header file New revision (v3) of QMP PHY uses different offsets for almost all of the registers. Hence, move these definitions to header file so that updated offsets can be added for QMP v3. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:05 +03:00
phy: qcom-qmp: Add SM8150 QMP USB3 PHY support Add support for SM8150 QMP USB3 PHY with the necessary initialization sequences as well as additional QMP V4 register definitions. Signed-off-by: Jack Pham <jackp@codeaurora.org> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 02:54:25 +03:00
/* Only for QMP V3 & V4 PHY - DP COM registers */
phy: qcom-qmp: Add register offsets for QMP V3 PHY Registers offsets for QMP V3 PHY are changed from previous versions (1/2), update same in header file. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:06 +03:00
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
#define QPHY_V3_DP_COM_SW_RESET 0x04
#define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
#define QPHY_V3_DP_COM_SWI_CTRL 0x0c
#define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
phy: qcom-qmp: move QSERDES V3 registers to separate headers Move QSERDES V3 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-10-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:43:01 +03:00
/* QSERDES V3 COM bits */
phy: qcom-qmp: Add support for DP in USB3+DP combo phy Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy driver. We already have support for the USB3 part of the combo phy, so most additions are for the DP phy. Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, power on, power off, and exit functions that the common phy framework expects so that the DP phy can add even more phy ops like phy_calibrate() and phy_configure(). This allows us to initialize the DP PHY and configure the AUX channel before powering on the PHY at the link rate that was negotiated during link training. The general design is as follows: 1) DP controller calls phy_init() to initialize the PHY and configure the dp_com register region. 2) DP controller calls phy_configure() to tune the link rate and voltage swing and pre-emphasis settings. 3) DP controller calls phy_power_on() to enable the PLL and power on the phy. 4) DP controller calls phy_configure() again to tune the voltage swing and pre-emphasis settings determind during link training. 5) DP controller calls phy_calibrate() some number of times to change the aux settings if the aux channel times out during link training. 6) DP controller calls phy_power_off() if the link rate is to be changed and goes back to step 2 to try again at a different link rate. 5) DP controller calls phy_power_off() and then phy_exit() to power down the PHY when it is done. The DP PHY contains a PLL that is different from the one used for the USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk output from the DP PLL after going through various dividers. Introduce clk ops for these two clks that just tell the child clks what the frequency of the pixel and link are. When the phy link rate is configured we call clk_set_rate() to update the child clks in the display clk controller on what rate is in use. The clk frequencies always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or HBR3) so we simply store the link rate and use that to calculate the clk frequencies. The PLL enable sequence is a little different from other QMP phy PLLs so we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called from phy_power_on(). This should probably be split out better so that each phy has a way to run the final PLL/PHY enable sequence. This code is based on a submission of this phy and PLL in the drm subsystem. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-17 02:11:59 +03:00
# define QSERDES_V3_COM_BIAS_EN 0x0001
# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
# define QSERDES_V3_COM_CLKBUF_L_EN 0x0008
# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
phy: qcom-qmp: Add register offsets for QMP V3 PHY Registers offsets for QMP V3 PHY are changed from previous versions (1/2), update same in header file. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:06 +03:00
phy: qcom-qmp: move QSERDES V3 registers to separate headers Move QSERDES V3 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-10-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:43:01 +03:00
/* QSERDES V3 TX bits */
phy: qcom-qmp: Add support for DP in USB3+DP combo phy Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy driver. We already have support for the USB3 part of the combo phy, so most additions are for the DP phy. Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, power on, power off, and exit functions that the common phy framework expects so that the DP phy can add even more phy ops like phy_calibrate() and phy_configure(). This allows us to initialize the DP PHY and configure the AUX channel before powering on the PHY at the link rate that was negotiated during link training. The general design is as follows: 1) DP controller calls phy_init() to initialize the PHY and configure the dp_com register region. 2) DP controller calls phy_configure() to tune the link rate and voltage swing and pre-emphasis settings. 3) DP controller calls phy_power_on() to enable the PLL and power on the phy. 4) DP controller calls phy_configure() again to tune the voltage swing and pre-emphasis settings determind during link training. 5) DP controller calls phy_calibrate() some number of times to change the aux settings if the aux channel times out during link training. 6) DP controller calls phy_power_off() if the link rate is to be changed and goes back to step 2 to try again at a different link rate. 5) DP controller calls phy_power_off() and then phy_exit() to power down the PHY when it is done. The DP PHY contains a PLL that is different from the one used for the USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk output from the DP PLL after going through various dividers. Introduce clk ops for these two clks that just tell the child clks what the frequency of the pixel and link are. When the phy link rate is configured we call clk_set_rate() to update the child clks in the display clk controller on what rate is in use. The clk frequencies always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or HBR3) so we simply store the link rate and use that to calculate the clk frequencies. The PLL enable sequence is a little different from other QMP phy PLLs so we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called from phy_power_on(). This should probably be split out better so that each phy has a way to run the final PLL/PHY enable sequence. This code is based on a submission of this phy and PLL in the drm subsystem. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-17 02:11:59 +03:00
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
phy: qcom-qmp: Add register offsets for QMP V3 PHY Registers offsets for QMP V3 PHY are changed from previous versions (1/2), update same in header file. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:06 +03:00
/* Only for QMP V3 PHY - PCS registers */
#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
#define QPHY_V3_PCS_TXMGN_V0 0x00c
#define QPHY_V3_PCS_TXMGN_V1 0x010
#define QPHY_V3_PCS_TXMGN_V2 0x014
#define QPHY_V3_PCS_TXMGN_V3 0x018
#define QPHY_V3_PCS_TXMGN_V4 0x01c
#define QPHY_V3_PCS_TXMGN_LS 0x020
phy: Add QMP phy based UFS phy support for sdm845 Add UFS PHY support to make SDM845 UFS work with common PHY framework. Signed-off-by: Can Guo <cang@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-21 07:27:56 +03:00
#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
phy: qcom-qmp: Add register offsets for QMP V3 PHY Registers offsets for QMP V3 PHY are changed from previous versions (1/2), update same in header file. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:06 +03:00
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
phy: qcom-qmp: Add msm8998 PCIe QMP PHY support Documentation for this PHY, and the proper configuration settings, is *not* publicly available. Therefore the initialization sequence is copied wholesale from downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998-v2.dtsi?h=LE.UM.1.3.r3.25#n372 Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-09 15:48:22 +03:00
#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
phy: qcom-qmp: Add register offsets for QMP V3 PHY Registers offsets for QMP V3 PHY are changed from previous versions (1/2), update same in header file. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:06 +03:00
#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
phy: Add QMP phy based UFS phy support for sdm845 Add UFS PHY support to make SDM845 UFS work with common PHY framework. Signed-off-by: Can Guo <cang@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-21 07:27:56 +03:00
#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
phy: qcom-qmp: Add msm8998 PCIe QMP PHY support Documentation for this PHY, and the proper configuration settings, is *not* publicly available. Therefore the initialization sequence is copied wholesale from downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998-v2.dtsi?h=LE.UM.1.3.r3.25#n372 Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-09 15:48:22 +03:00
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
phy: Add QMP phy based UFS phy support for sdm845 Add UFS PHY support to make SDM845 UFS work with common PHY framework. Signed-off-by: Can Guo <cang@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-21 07:27:56 +03:00
#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
phy: qcom-qmp: Add register offsets for QMP V3 PHY Registers offsets for QMP V3 PHY are changed from previous versions (1/2), update same in header file. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:06 +03:00
#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
phy: qcom-qmp: Add msm8998 PCIe QMP PHY support Documentation for this PHY, and the proper configuration settings, is *not* publicly available. Therefore the initialization sequence is copied wholesale from downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998-v2.dtsi?h=LE.UM.1.3.r3.25#n372 Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-09 15:48:22 +03:00
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845 QMP V3 UNI PHY is a single lane USB3 PHY without support for DisplayPort (DP). Main difference from DP combo QMPv3 PHY is that UNI PHY doesn't have dual RX/TX lanes and no separate DP_COM block for configuration related to type-c or DP. Also remove "qcom,qmp-v3-usb3-phy" compatible string which was earlier added for sdm845 only as there wouldn't be any user of same. While at it, fix has_pwrdn_delay attribute for USB-DP PHY configuration and. Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-05-03 00:06:12 +03:00
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
phy: qcom-qmp: Add register offsets for QMP V3 PHY Registers offsets for QMP V3 PHY are changed from previous versions (1/2), update same in header file. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:06 +03:00
phy: qcom-qmp: Add support for runtime PM Disable clocks and enable PHY autonomous mode to detect wakeup events when PHY is suspended. Core driver should notify speed to PHY driver to enable LFPS and/or RX_DET interrupts. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:11 +03:00
/* Only for QMP V3 PHY - PCS_MISC registers */
#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
phy: qcom-qmp: Add msm8998 PCIe QMP PHY support Documentation for this PHY, and the proper configuration settings, is *not* publicly available. Therefore the initialization sequence is copied wholesale from downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998-v2.dtsi?h=LE.UM.1.3.r3.25#n372 Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-09 15:48:22 +03:00
#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
phy: qcom-qmp: Add support for runtime PM Disable clocks and enable PHY autonomous mode to detect wakeup events when PHY is suspended. Core driver should notify speed to PHY driver to enable LFPS and/or RX_DET interrupts. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:11 +03:00
phy: qcom-qmp: rename common registers A plenty of DP PHY registers are common between V3 and V4. To simplify V4 code, rename all common registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 18:16:11 +03:00
/* QMP PHY - DP PHY registers */
#define QSERDES_DP_PHY_REVISION_ID0 0x000
#define QSERDES_DP_PHY_REVISION_ID1 0x004
#define QSERDES_DP_PHY_REVISION_ID2 0x008
#define QSERDES_DP_PHY_REVISION_ID3 0x00c
#define QSERDES_DP_PHY_CFG 0x010
#define QSERDES_DP_PHY_PD_CTL 0x018
phy: qcom-qmp: Add support for DP in USB3+DP combo phy Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy driver. We already have support for the USB3 part of the combo phy, so most additions are for the DP phy. Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, power on, power off, and exit functions that the common phy framework expects so that the DP phy can add even more phy ops like phy_calibrate() and phy_configure(). This allows us to initialize the DP PHY and configure the AUX channel before powering on the PHY at the link rate that was negotiated during link training. The general design is as follows: 1) DP controller calls phy_init() to initialize the PHY and configure the dp_com register region. 2) DP controller calls phy_configure() to tune the link rate and voltage swing and pre-emphasis settings. 3) DP controller calls phy_power_on() to enable the PLL and power on the phy. 4) DP controller calls phy_configure() again to tune the voltage swing and pre-emphasis settings determind during link training. 5) DP controller calls phy_calibrate() some number of times to change the aux settings if the aux channel times out during link training. 6) DP controller calls phy_power_off() if the link rate is to be changed and goes back to step 2 to try again at a different link rate. 5) DP controller calls phy_power_off() and then phy_exit() to power down the PHY when it is done. The DP PHY contains a PLL that is different from the one used for the USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk output from the DP PLL after going through various dividers. Introduce clk ops for these two clks that just tell the child clks what the frequency of the pixel and link are. When the phy link rate is configured we call clk_set_rate() to update the child clks in the display clk controller on what rate is in use. The clk frequencies always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or HBR3) so we simply store the link rate and use that to calculate the clk frequencies. The PLL enable sequence is a little different from other QMP phy PLLs so we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called from phy_power_on(). This should probably be split out better so that each phy has a way to run the final PLL/PHY enable sequence. This code is based on a submission of this phy and PLL in the drm subsystem. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-17 02:11:59 +03:00
# define DP_PHY_PD_CTL_PWRDN 0x001
# define DP_PHY_PD_CTL_PSR_PWRDN 0x002
# define DP_PHY_PD_CTL_AUX_PWRDN 0x004
# define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008
# define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010
# define DP_PHY_PD_CTL_PLL_PWRDN 0x020
# define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040
phy: qcom-qmp: rename common registers A plenty of DP PHY registers are common between V3 and V4. To simplify V4 code, rename all common registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 18:16:11 +03:00
#define QSERDES_DP_PHY_MODE 0x01c
#define QSERDES_DP_PHY_AUX_CFG0 0x020
#define QSERDES_DP_PHY_AUX_CFG1 0x024
#define QSERDES_DP_PHY_AUX_CFG2 0x028
#define QSERDES_DP_PHY_AUX_CFG3 0x02c
#define QSERDES_DP_PHY_AUX_CFG4 0x030
#define QSERDES_DP_PHY_AUX_CFG5 0x034
#define QSERDES_DP_PHY_AUX_CFG6 0x038
#define QSERDES_DP_PHY_AUX_CFG7 0x03c
#define QSERDES_DP_PHY_AUX_CFG8 0x040
#define QSERDES_DP_PHY_AUX_CFG9 0x044
phy: qcom-qmp: Add support for DP in USB3+DP combo phy Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy driver. We already have support for the USB3 part of the combo phy, so most additions are for the DP phy. Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, power on, power off, and exit functions that the common phy framework expects so that the DP phy can add even more phy ops like phy_calibrate() and phy_configure(). This allows us to initialize the DP PHY and configure the AUX channel before powering on the PHY at the link rate that was negotiated during link training. The general design is as follows: 1) DP controller calls phy_init() to initialize the PHY and configure the dp_com register region. 2) DP controller calls phy_configure() to tune the link rate and voltage swing and pre-emphasis settings. 3) DP controller calls phy_power_on() to enable the PLL and power on the phy. 4) DP controller calls phy_configure() again to tune the voltage swing and pre-emphasis settings determind during link training. 5) DP controller calls phy_calibrate() some number of times to change the aux settings if the aux channel times out during link training. 6) DP controller calls phy_power_off() if the link rate is to be changed and goes back to step 2 to try again at a different link rate. 5) DP controller calls phy_power_off() and then phy_exit() to power down the PHY when it is done. The DP PHY contains a PLL that is different from the one used for the USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk output from the DP PLL after going through various dividers. Introduce clk ops for these two clks that just tell the child clks what the frequency of the pixel and link are. When the phy link rate is configured we call clk_set_rate() to update the child clks in the display clk controller on what rate is in use. The clk frequencies always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or HBR3) so we simply store the link rate and use that to calculate the clk frequencies. The PLL enable sequence is a little different from other QMP phy PLLs so we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called from phy_power_on(). This should probably be split out better so that each phy has a way to run the final PLL/PHY enable sequence. This code is based on a submission of this phy and PLL in the drm subsystem. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-17 02:11:59 +03:00
phy: qcom-qmp: rename common registers A plenty of DP PHY registers are common between V3 and V4. To simplify V4 code, rename all common registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 18:16:11 +03:00
/* Only for QMP V3 PHY - DP PHY registers */
phy: qcom-qmp: Add support for DP in USB3+DP combo phy Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy driver. We already have support for the USB3 part of the combo phy, so most additions are for the DP phy. Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, power on, power off, and exit functions that the common phy framework expects so that the DP phy can add even more phy ops like phy_calibrate() and phy_configure(). This allows us to initialize the DP PHY and configure the AUX channel before powering on the PHY at the link rate that was negotiated during link training. The general design is as follows: 1) DP controller calls phy_init() to initialize the PHY and configure the dp_com register region. 2) DP controller calls phy_configure() to tune the link rate and voltage swing and pre-emphasis settings. 3) DP controller calls phy_power_on() to enable the PLL and power on the phy. 4) DP controller calls phy_configure() again to tune the voltage swing and pre-emphasis settings determind during link training. 5) DP controller calls phy_calibrate() some number of times to change the aux settings if the aux channel times out during link training. 6) DP controller calls phy_power_off() if the link rate is to be changed and goes back to step 2 to try again at a different link rate. 5) DP controller calls phy_power_off() and then phy_exit() to power down the PHY when it is done. The DP PHY contains a PLL that is different from the one used for the USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk output from the DP PLL after going through various dividers. Introduce clk ops for these two clks that just tell the child clks what the frequency of the pixel and link are. When the phy link rate is configured we call clk_set_rate() to update the child clks in the display clk controller on what rate is in use. The clk frequencies always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or HBR3) so we simply store the link rate and use that to calculate the clk frequencies. The PLL enable sequence is a little different from other QMP phy PLLs so we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called from phy_power_on(). This should probably be split out better so that each phy has a way to run the final PLL/PHY enable sequence. This code is based on a submission of this phy and PLL in the drm subsystem. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-17 02:11:59 +03:00
#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048
# define PHY_AUX_STOP_ERR_MASK 0x01
# define PHY_AUX_DEC_ERR_MASK 0x02
# define PHY_AUX_SYNC_ERR_MASK 0x04
# define PHY_AUX_ALIGN_ERR_MASK 0x08
# define PHY_AUX_REQ_ERR_MASK 0x10
#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
#define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050
#define QSERDES_V3_DP_PHY_VCO_DIV 0x064
#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c
#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088
#define QSERDES_V3_DP_PHY_SPARE0 0x0ac
#define DP_PHY_SPARE0_MASK 0x0f
#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004)
#define QSERDES_V3_DP_PHY_STATUS 0x0c0
phy: qcom-qmp: Add SM8150 QMP UFS PHY support SM8150 UFS PHY is v4 of QMP phy. Add support for V4 QMP phy register defines and support for SM8150 QMP UFS PHY. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-10-24 10:48:02 +03:00
phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY The PCIe PHY version used in SDX55 is v4.20 which has different register offsets compared to the v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210427065400.18958-4-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-27 09:54:00 +03:00
/* Only for QMP V4_20 PHY - TX registers */
#define QSERDES_V4_20_TX_LANE_MODE_1 0x88
#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
#define QSERDES_V4_20_TX_LANE_MODE_3 0x90
#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
phy: qcom-qmp: add support for sm8250-usb3-dp phy Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 18:16:12 +03:00
/* Only for QMP V4 PHY - DP PHY registers */
#define QSERDES_V4_DP_PHY_CFG_1 0x014
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058
#define QSERDES_V4_DP_PHY_VCO_DIV 0x070
#define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078
#define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c
#define QSERDES_V4_DP_PHY_SPARE0 0x0c8
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY The PCIe PHY version used in SDX55 is v4.20 which has different register offsets compared to the v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210427065400.18958-4-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-27 09:54:00 +03:00
/* Only for QMP V4_20 PHY - RX registers */
#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
#define QSERDES_V4_20_RX_DFE_3 0x110
#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138
#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150
#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc
#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200
#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
phy: qcom-qmp: Add SM8150 QMP USB3 PHY support Add support for SM8150 QMP USB3 PHY with the necessary initialization sequences as well as additional QMP V4 register definitions. Signed-off-by: Jack Pham <jackp@codeaurora.org> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 02:54:25 +03:00
/* Only for QMP V4 PHY - UFS PCS registers */
phy: qcom-qmp: clean up define alignment Clean up the QMP defines by removing some stray white space and making sure values are aligned. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20220609120338.4080-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-09 15:03:37 +03:00
#define QPHY_V4_PCS_UFS_PHY_START 0x000
#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
#define QPHY_V4_PCS_UFS_SW_RESET 0x008
#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
phy: qcom-qmp: Rename UFS PCS QMP v4 registers The UFS QMP v4 PHY has a largely different register set versus USB and PCIe. Rename the register offsets to denote that the value is specific for the UFS PCS register. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-6-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 02:54:27 +03:00
#define QPHY_V4_PCS_UFS_READY_STATUS 0x180
phy: qcom-qmp: clean up define alignment Clean up the QMP defines by removing some stray white space and making sure values are aligned. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20220609120338.4080-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-09 15:03:37 +03:00
#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
phy: qcom-qmp: Add SM8150 QMP UFS PHY support SM8150 UFS PHY is v4 of QMP phy. Add support for V4 QMP phy register defines and support for SM8150 QMP UFS PHY. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-10-24 10:48:02 +03:00
phy: qcom: qmp: Add SDM845 QHP PCIe PHY Add the GEN3 QHP PCIe PHY found in SDM845. Tested-by: Julien Massot <jmassot@softbankrobotics.com> Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-06 11:18:21 +03:00
/* PCIE GEN3 COM registers */
#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
/* PCIE GEN3 QHP Lane registers */
#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
/* PCIE GEN3 PCS registers */
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
phy: qcom-qmp: Add SM8150 QMP USB3 PHY support Add support for SM8150 QMP USB3 PHY with the necessary initialization sequences as well as additional QMP V4 register definitions. Signed-off-by: Jack Pham <jackp@codeaurora.org> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 02:54:25 +03:00
/* Only for QMP V4 PHY - USB/PCIe PCS registers */
#define QPHY_V4_PCS_SW_RESET 0x000
#define QPHY_V4_PCS_REVISION_ID0 0x004
#define QPHY_V4_PCS_REVISION_ID1 0x008
#define QPHY_V4_PCS_REVISION_ID2 0x00c
#define QPHY_V4_PCS_REVISION_ID3 0x010
#define QPHY_V4_PCS_PCS_STATUS1 0x014
#define QPHY_V4_PCS_PCS_STATUS2 0x018
#define QPHY_V4_PCS_PCS_STATUS3 0x01c
#define QPHY_V4_PCS_PCS_STATUS4 0x020
#define QPHY_V4_PCS_PCS_STATUS5 0x024
#define QPHY_V4_PCS_PCS_STATUS6 0x028
#define QPHY_V4_PCS_PCS_STATUS7 0x02c
#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030
#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034
#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038
#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c
#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040
#define QPHY_V4_PCS_START_CONTROL 0x044
#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048
#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c
#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050
#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054
#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058
#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c
#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060
#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064
#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068
#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c
#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070
#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074
#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078
#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c
#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080
#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084
#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088
#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c
#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090
#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094
#define QPHY_V4_PCS_FLL_CNTRL1 0x098
#define QPHY_V4_PCS_FLL_CNTRL2 0x09c
#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0
#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4
#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8
#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac
#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0
#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4
#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8
#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc
#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8
#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc
#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0
#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4
#define QPHY_V4_PCS_BIST_CTRL 0x0e8
#define QPHY_V4_PCS_PRBS_POLY0 0x0ec
#define QPHY_V4_PCS_PRBS_POLY1 0x0f0
#define QPHY_V4_PCS_FIXED_PAT0 0x0f4
#define QPHY_V4_PCS_FIXED_PAT1 0x0f8
#define QPHY_V4_PCS_FIXED_PAT2 0x0fc
#define QPHY_V4_PCS_FIXED_PAT3 0x100
#define QPHY_V4_PCS_FIXED_PAT4 0x104
#define QPHY_V4_PCS_FIXED_PAT5 0x108
#define QPHY_V4_PCS_FIXED_PAT6 0x10c
#define QPHY_V4_PCS_FIXED_PAT7 0x110
#define QPHY_V4_PCS_FIXED_PAT8 0x114
#define QPHY_V4_PCS_FIXED_PAT9 0x118
#define QPHY_V4_PCS_FIXED_PAT10 0x11c
#define QPHY_V4_PCS_FIXED_PAT11 0x120
#define QPHY_V4_PCS_FIXED_PAT12 0x124
#define QPHY_V4_PCS_FIXED_PAT13 0x128
#define QPHY_V4_PCS_FIXED_PAT14 0x12c
#define QPHY_V4_PCS_FIXED_PAT15 0x130
#define QPHY_V4_PCS_TXMGN_CONFIG 0x134
#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138
#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c
#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140
#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144
#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148
#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c
#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150
#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154
#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158
#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c
#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160
#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164
#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168
#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170
#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174
#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178
#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c
#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180
#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198
#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c
#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac
#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0
#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4
#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8
#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc
#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8
#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc
#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0
#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8
#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc
#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0
#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
phy: qcom-qmp-combo,usb: add support for separate PCS_USB region Different QMP USB PHYs might have different offset from PCS to PCS_USB register space, but the same PCS_USB register layout. Add separate PCS_USB region space and merge related PCS_USB definitions. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:42:55 +03:00
/* Only for QMP V4 PHY - USB3 PCS registers */
#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028
#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c
#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030
#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034
#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038
#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c
#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040
#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044
#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048
#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c
#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050
#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054
#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058
phy: qcom-qmp: Add SM8150 QMP USB3 PHY support Add support for SM8150 QMP USB3 PHY with the necessary initialization sequences as well as additional QMP V4 register definitions. Signed-off-by: Jack Pham <jackp@codeaurora.org> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 02:54:25 +03:00
phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY The PCIe PHY version used in SDX55 is v4.20 which has different register offsets compared to the v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210427065400.18958-4-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-27 09:54:00 +03:00
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
phy: qcom-qmp: Add SM8150 QMP USB3 PHY support Add support for SM8150 QMP USB3 PHY with the necessary initialization sequences as well as additional QMP V4 register definitions. Signed-off-by: Jack Pham <jackp@codeaurora.org> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 02:54:25 +03:00
/* Only for QMP V4 PHY - PCS_MISC registers */
#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08
#define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c
#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
phy: qcom-qmp: Add SM8250 PCIe QMP PHYs SM8250 has multiple different PHY versions: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes QMP Modem PHY - 2 lanes Add support for these with relevant init sequence. In order to abstract the init sequence, this commit introduces secondary tables which can be used to factor out the unique sequence for each PHY while the former tables can have the common sequence. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201027170033.8475-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-10-27 20:00:30 +03:00
/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14
#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c
#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
phy: qcom-qmp: use QPHY_V4_PCS for ipq6018/ipq8074 PCIe gen3 PCS_COM_* symbols duplicate the QPHY_V4_PCS_*. PCS_PCIE_* symbols duplicate the QPHY_V4_PCS_PCIE_*. Use generic register names for the IPQ6018 and IPQ8074 tables and drop the custom PCS_COM_*/PCS_PCIE* names. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-8-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:42:59 +03:00
#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
phy: qcom-qmp: Add SM8250 PCIe QMP PHYs SM8250 has multiple different PHY versions: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes QMP Modem PHY - 2 lanes Add support for these with relevant init sequence. In order to abstract the init sequence, this commit introduces secondary tables which can be used to factor out the unique sequence for each PHY while the former tables can have the common sequence. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201027170033.8475-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-10-27 20:00:30 +03:00
#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY The PCIe PHY version used in SDX55 is v4.20 which has different register offsets compared to the v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210427065400.18958-4-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-27 09:54:00 +03:00
#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
phy: qcom-qmp: Add SM8450 PCIe1 PHY support There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the second PCIe phy. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211218141754.503661-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-18 17:17:55 +03:00
/* Only for QMP V5_20 PHY - TX registers */
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
/* Only for QMP V5_20 PHY - RX registers */
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
#define QSERDES_V5_20_RX_DFE_3 0x090
#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8
#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc
#define QSERDES_V5_20_RX_GM_CAL 0x0ec
#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0
#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4
#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
phy: qcom-qmp: Add SM8450 PCIe0 PHY support There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the first PCIe phy only, support for the second PCIe PHY is coming in next commits. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211214225846.2043361-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-15 01:58:39 +03:00
/* Only for QMP V5 PHY - USB/PCIe PCS registers */
#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
phy: qcom-qmp: Add SM8450 PCIe1 PHY support There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the second PCIe phy. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211218141754.503661-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-18 17:17:55 +03:00
#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
phy: qcom-qmp: Add SM8450 PCIe0 PHY support There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the first PCIe phy only, support for the second PCIe PHY is coming in next commits. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211214225846.2043361-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-15 01:58:39 +03:00
#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
phy: qcom-qmp: Add SM8450 PCIe1 PHY support There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the second PCIe phy. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211218141754.503661-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-18 17:17:55 +03:00
#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
phy: qcom-qmp: Add SM8450 PCIe0 PHY support There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the first PCIe phy only, support for the second PCIe PHY is coming in next commits. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211214225846.2043361-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-15 01:58:39 +03:00
/* Only for QMP V5 PHY - PCS_PCIE registers */
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
phy: qcom-qmp: Add SM8450 PCIe1 PHY support There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the second PCIe phy. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211218141754.503661-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-18 17:17:55 +03:00
/* Only for QMP V5_20 PHY - PCIe PCS registers */
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
phy: qcom-qmp: Add UFS V5 registers found in SM8350 Add the registers for UFS found in SM8350. The UFS phy used in SM8350 seems to have same offsets as V5 phy, although Documentation for that is lacking. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210204165805.62235-3-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04 19:58:04 +03:00
/* Only for QMP V5 PHY - UFS PCS registers */
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
phy: qcom-qmp: Add SM8350 USB QMP PHYs Add support for the USB DP & UNI PHYs found on SM8350. These use version 5.0.0 of the QMP PHY IP and thus require new "V5" definitions of the register offset macros for the QSERDES RX and TX blocks. The QSERDES common and QPHY PCS blocks' register offsets are largely unchanged from V4 so some of the existing macros can be reused. Signed-off-by: Jack Pham <jackp@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210115174723.7424-3-jackp@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-15 20:47:21 +03:00
/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
phy: qcom-qmp-combo,usb: add support for separate PCS_USB region Different QMP USB PHYs might have different offset from PCS to PCS_USB register space, but the same PCS_USB register layout. Add separate PCS_USB region space and merge related PCS_USB definitions. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05 12:42:55 +03:00
#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
phy: qcom-qmp: Add SM8350 USB QMP PHYs Add support for the USB DP & UNI PHYs found on SM8350. These use version 5.0.0 of the QMP PHY IP and thus require new "V5" definitions of the register offset macros for the QSERDES RX and TX blocks. The QSERDES common and QPHY PCS blocks' register offsets are largely unchanged from V4 so some of the existing macros can be reused. Signed-off-by: Jack Pham <jackp@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210115174723.7424-3-jackp@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-15 20:47:21 +03:00
phy: qcom-qmp: Move register offsets to header file New revision (v3) of QMP PHY uses different offsets for almost all of the registers. Hence, move these definitions to header file so that updated offsets can be added for QMP v3. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-01-16 13:57:05 +03:00
#endif
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