2008-05-20 03:52:27 +04:00
/ *
2005-04-17 02:20:36 +04:00
* trampoline. S : J u m p s t a r t s l a v e p r o c e s s o r s o n s p a r c64 .
*
* Copyright ( C ) 1 9 9 7 D a v i d S . M i l l e r ( d a v e m @caip.rutgers.edu)
* /
2008-02-21 09:22:16 +03:00
# include < l i n u x / i n i t . h >
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# include < a s m / h e a d . h >
# include < a s m / a s i . h >
# include < a s m / l s u . h >
# include < a s m / d c r . h >
# include < a s m / d c u . h >
# include < a s m / p s t a t e . h >
# include < a s m / p a g e . h >
# include < a s m / p g t a b l e . h >
# include < a s m / s p i t f i r e . h >
# include < a s m / p r o c e s s o r . h >
# include < a s m / t h r e a d _ i n f o . h >
# include < a s m / m m u . h >
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# include < a s m / h y p e r v i s o r . h >
2006-02-14 11:55:49 +03:00
# include < a s m / c p u d a t a . h >
2005-04-17 02:20:36 +04:00
.data
.align 8
call_method :
.asciz " call- m e t h o d "
.align 8
itlb_load :
.asciz " SUNW,i t l b - l o a d "
.align 8
dtlb_load :
.asciz " SUNW,d t l b - l o a d "
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 12:29:17 +03:00
/* XXX __cpuinit this thing XXX */
# define T R A M P _ S T A C K _ S I Z E 1 0 2 4
.align 16
tramp_stack :
.skip TRAMP_STACK_SIZE
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_ _ CPUINIT
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.align 8
.globl 6 4 _ c p u _ s t a r t u p , s p a r c64 _ c p u _ s t a r t u p _ e n d
sparc64_cpu_startup :
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BRANCH_ I F _ S U N 4 V ( g 1 , n i a g a r a _ s t a r t u p )
BRANCH_ I F _ C H E E T A H _ B A S E ( g 1 , g 5 , c h e e t a h _ s t a r t u p )
BRANCH_ I F _ C H E E T A H _ P L U S _ O R _ F O L L O W O N ( g 1 , g 5 , c h e e t a h _ p l u s _ s t a r t u p )
2005-04-17 02:20:36 +04:00
ba,p t % x c c , s p i t f i r e _ s t a r t u p
nop
cheetah_plus_startup :
/* Preserve OBP chosen DCU and DCR register settings. */
ba,p t % x c c , c h e e t a h _ g e n e r i c _ s t a r t u p
nop
cheetah_startup :
mov D C R _ B P E | D C R _ R P E | D C R _ S I | D C R _ I F P O E | D C R _ M S , % g 1
wr % g 1 , % a s r18
sethi % u h i ( D C U _ M E | D C U _ R E | D C U _ H P E | D C U _ S P E | D C U _ S L | D C U _ W E ) , % g 5
or % g 5 , % u l o ( D C U _ M E | D C U _ R E | D C U _ H P E | D C U _ S P E | D C U _ S L | D C U _ W E ) , % g 5
sllx % g 5 , 3 2 , % g 5
or % g 5 , D C U _ D M | D C U _ I M | D C U _ D C | D C U _ I C , % g 5
stxa % g 5 , [ % g 0 ] A S I _ D C U _ C O N T R O L _ R E G
membar #S y n c
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 12:29:17 +03:00
/* fallthru */
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cheetah_generic_startup :
mov T S B _ E X T E N S I O N _ P , % g 3
stxa % g 0 , [ % g 3 ] A S I _ D M M U
stxa % g 0 , [ % g 3 ] A S I _ I M M U
membar #S y n c
mov T S B _ E X T E N S I O N _ S , % g 3
stxa % g 0 , [ % g 3 ] A S I _ D M M U
membar #S y n c
mov T S B _ E X T E N S I O N _ N , % g 3
stxa % g 0 , [ % g 3 ] A S I _ D M M U
stxa % g 0 , [ % g 3 ] A S I _ I M M U
membar #S y n c
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/* fallthru */
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niagara_startup :
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/* Disable STICK_INT interrupts. */
sethi % h i ( 0 x80 0 0 0 0 0 0 ) , % g 5
sllx % g 5 , 3 2 , % g 5
wr % g 5 , % a s r25
ba,p t % x c c , s t a r t u p _ c o n t i n u e
nop
spitfire_startup :
mov ( L S U _ C O N T R O L _ I C | L S U _ C O N T R O L _ D C | L S U _ C O N T R O L _ I M | L S U _ C O N T R O L _ D M ) , % g 1
stxa % g 1 , [ % g 0 ] A S I _ L S U _ C O N T R O L
membar #S y n c
startup_continue :
2007-08-16 12:56:00 +04:00
mov % o 0 , % l 0
BRANCH_ I F _ S U N 4 V ( g 1 , n i a g a r a _ l o c k _ t l b )
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sethi % h i ( 0 x80 0 0 0 0 0 0 ) , % g 2
sllx % g 2 , 3 2 , % g 2
wr % g 2 , 0 , % t i c k _ c m p r
/ * Call O B P b y h a n d t o l o c k K E R N B A S E i n t o i / d t l b s .
2008-03-22 03:01:38 +03:00
* We l o c k ' n u m _ k e r n e l _ i m a g e _ m a p p i n g s ' c o n s e q u e t i v e e n t r i e s .
2005-04-17 02:20:36 +04:00
* /
sethi % h i ( p r o m _ e n t r y _ l o c k ) , % g 2
1 : ldstub [ % g 2 + % l o ( p r o m _ e n t r y _ l o c k ) ] , % g 1
brnz,p n % g 1 , 1 b
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 02:42:04 +04:00
nop
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sethi % h i ( p12 7 5 b u f ) , % g 2
or % g 2 , % l o ( p12 7 5 b u f ) , % g 2
ldx [ % g 2 + 0 x10 ] , % l 2
add % l 2 , - ( 1 9 2 + 1 2 8 ) , % s p
flushw
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/ * Setup t h e l o o p v a r i a b l e s :
* % l3 : VADDR b a s e
* % l4 : TTE b a s e
* % l5 : Loop i t e r a t o r , i t e r a t e s f r o m 0 t o ' n u m _ k e r n e l _ i m a g e _ m a p p i n g s '
* % l6 : Number o f T T E e n t r i e s t o m a p
* % l7 : Highest T T E e n t r y n u m b e r , w e c o u n t d o w n
* /
sethi % h i ( K E R N B A S E ) , % l 3
sethi % h i ( k e r n _ l o c k e d _ t t e _ d a t a ) , % l 4
ldx [ % l 4 + % l o ( k e r n _ l o c k e d _ t t e _ d a t a ) ] , % l 4
clr % l 5
sethi % h i ( n u m _ k e r n e l _ i m a g e _ m a p p i n g s ) , % l 6
lduw [ % l 6 + % l o ( n u m _ k e r n e l _ i m a g e _ m a p p i n g s ) ] , % l 6
add % l 6 , 1 , % l 6
mov 1 5 , % l 7
BRANCH_ I F _ A N Y _ C H E E T A H ( g 1 ,g 5 ,2 f )
mov 6 3 , % l 7
2 :
3 :
/* Lock into I-MMU */
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sethi % h i ( c a l l _ m e t h o d ) , % g 2
or % g 2 , % l o ( c a l l _ m e t h o d ) , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ]
mov 5 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ]
mov 1 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ]
sethi % h i ( i t l b _ l o a d ) , % g 2
or % g 2 , % l o ( i t l b _ l o a d ) , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ]
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
sethi % h i ( p r o m _ m m u _ i h a n d l e _ c a c h e ) , % g 2
lduw [ % g 2 + % l o ( p r o m _ m m u _ i h a n d l e _ c a c h e ) ] , % g 2
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stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ]
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/* Each TTE maps 4MB, convert index to offset. */
sllx % l 5 , 2 2 , % g 1
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2008-03-22 03:01:38 +03:00
add % l 3 , % g 1 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x28 ] ! V A D D R
add % l 4 , % g 1 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x30 ] ! T T E
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2008-03-22 03:01:38 +03:00
/* TTE index is highest minus loop index. */
sub % l 7 , % l 5 , % g 2
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stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x38 ]
2008-03-22 03:01:38 +03:00
2005-04-17 02:20:36 +04:00
sethi % h i ( p12 7 5 b u f ) , % g 2
or % g 2 , % l o ( p12 7 5 b u f ) , % g 2
ldx [ % g 2 + 0 x08 ] , % o 1
call % o 1
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0
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/* Lock into D-MMU */
2005-04-17 02:20:36 +04:00
sethi % h i ( c a l l _ m e t h o d ) , % g 2
or % g 2 , % l o ( c a l l _ m e t h o d ) , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ]
mov 5 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ]
mov 1 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ]
sethi % h i ( d t l b _ l o a d ) , % g 2
or % g 2 , % l o ( d t l b _ l o a d ) , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ]
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
sethi % h i ( p r o m _ m m u _ i h a n d l e _ c a c h e ) , % g 2
lduw [ % g 2 + % l o ( p r o m _ m m u _ i h a n d l e _ c a c h e ) ] , % g 2
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stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ]
2008-03-22 03:01:38 +03:00
/* Each TTE maps 4MB, convert index to offset. */
sllx % l 5 , 2 2 , % g 1
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2008-03-22 03:01:38 +03:00
add % l 3 , % g 1 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x28 ] ! V A D D R
add % l 4 , % g 1 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x30 ] ! T T E
2005-04-17 02:20:36 +04:00
2008-03-22 03:01:38 +03:00
/* TTE index is highest minus loop index. */
sub % l 7 , % l 5 , % g 2
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stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x38 ]
2008-03-22 03:01:38 +03:00
2005-04-17 02:20:36 +04:00
sethi % h i ( p12 7 5 b u f ) , % g 2
or % g 2 , % l o ( p12 7 5 b u f ) , % g 2
ldx [ % g 2 + 0 x08 ] , % o 1
call % o 1
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0
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add % l 5 , 1 , % l 5
cmp % l 5 , % l 6
bne,p t % x c c , 3 b
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nop
sethi % h i ( p r o m _ e n t r y _ l o c k ) , % g 2
stb % g 0 , [ % g 2 + % l o ( p r o m _ e n t r y _ l o c k ) ]
2006-02-09 13:52:44 +03:00
ba,p t % x c c , a f t e r _ l o c k _ t l b
nop
niagara_lock_tlb :
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sethi % h i ( K E R N B A S E ) , % l 3
sethi % h i ( k e r n _ l o c k e d _ t t e _ d a t a ) , % l 4
ldx [ % l 4 + % l o ( k e r n _ l o c k e d _ t t e _ d a t a ) ] , % l 4
clr % l 5
sethi % h i ( n u m _ k e r n e l _ i m a g e _ m a p p i n g s ) , % l 6
lduw [ % l 6 + % l o ( n u m _ k e r n e l _ i m a g e _ m a p p i n g s ) ] , % l 6
add % l 6 , 1 , % l 6
1 :
2006-02-10 09:57:21 +03:00
mov H V _ F A S T _ M M U _ M A P _ P E R M _ A D D R , % o 5
2008-03-22 03:01:38 +03:00
sllx % l 5 , 2 2 , % g 2
add % l 3 , % g 2 , % o 0
2006-02-10 09:57:21 +03:00
clr % o 1
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add % l 4 , % g 2 , % o 2
2006-02-10 09:57:21 +03:00
mov H V _ M M U _ I M M U , % o 3
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ta H V _ F A S T _ T R A P
2006-02-10 09:57:21 +03:00
mov H V _ F A S T _ M M U _ M A P _ P E R M _ A D D R , % o 5
2008-03-22 03:01:38 +03:00
sllx % l 5 , 2 2 , % g 2
add % l 3 , % g 2 , % o 0
2006-02-10 09:57:21 +03:00
clr % o 1
2008-03-22 03:01:38 +03:00
add % l 4 , % g 2 , % o 2
2006-02-10 09:57:21 +03:00
mov H V _ M M U _ D M M U , % o 3
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ta H V _ F A S T _ T R A P
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add % l 5 , 1 , % l 5
cmp % l 5 , % l 6
bne,p t % x c c , 1 b
2006-02-09 13:52:44 +03:00
nop
after_lock_tlb :
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wrpr % g 0 , ( P S T A T E _ P R I V | P S T A T E _ P E F ) , % p s t a t e
wr % g 0 , 0 , % f p r s
wr % g 0 , A S I _ P , % a s i
mov P R I M A R Y _ C O N T E X T , % g 7
2006-02-08 09:13:05 +03:00
661 : stxa % g 0 , [ % g 7 ] A S I _ D M M U
.section .sun4v_1insn_patch , " ax"
.word 661b
stxa % g 0 , [ % g 7 ] A S I _ M M U
.previous
2005-04-17 02:20:36 +04:00
membar #S y n c
mov S E C O N D A R Y _ C O N T E X T , % g 7
2006-02-08 09:13:05 +03:00
661 : stxa % g 0 , [ % g 7 ] A S I _ D M M U
.section .sun4v_1insn_patch , " ax"
.word 661b
stxa % g 0 , [ % g 7 ] A S I _ M M U
.previous
2005-04-17 02:20:36 +04:00
membar #S y n c
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 12:29:17 +03:00
/ * Everything w e d o h e r e , u n t i l w e p r o p e r l y t a k e o v e r t h e
* trap t a b l e , m u s t b e d o n e w i t h e x t r e m e c a r e . W e c a n n o t
* make a n y r e f e r e n c e s t o % g 6 ( c u r r e n t t h r e a d p o i n t e r ) ,
* % g4 ( c u r r e n t t a s k p o i n t e r ) , o r % g 5 ( b a s e o f c u r r e n t c p u ' s
* per- c p u a r e a ) u n t i l w e p r o p e r l y t a k e o v e r t h e t r a p t a b l e
* from t h e f i r m w a r e a n d h y p e r v i s o r .
*
* Get o n t o t e m p o r a r y s t a c k w h i c h i s i n t h e l o c k e d k e r n e l i m a g e .
* /
sethi % h i ( t r a m p _ s t a c k ) , % g 1
or % g 1 , % l o ( t r a m p _ s t a c k ) , % g 1
add % g 1 , T R A M P _ S T A C K _ S I Z E , % g 1
2007-09-16 22:51:15 +04:00
sub % g 1 , S T A C K F R A M E _ S Z + S T A C K _ B I A S + 2 5 6 , % s p
2005-04-17 02:20:36 +04:00
mov 0 , % f p
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 12:29:17 +03:00
/* Put garbage in these registers to trap any access to them. */
set 0 x d e a d b e e f , % g 4
set 0 x d e a d b e e f , % g 5
set 0 x d e a d b e e f , % g 6
2005-04-17 02:20:36 +04:00
call i n i t _ i r q w o r k _ c u r c p u
nop
2006-02-08 11:08:23 +03:00
sethi % h i ( t l b _ t y p e ) , % g 3
lduw [ % g 3 + % l o ( t l b _ t y p e ) ] , % g 2
cmp % g 2 , 3
bne,p t % i c c , 1 f
nop
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 12:29:17 +03:00
call h a r d _ s m p _ p r o c e s s o r _ i d
nop
2007-08-09 04:32:33 +04:00
call s u n 4 v _ r e g i s t e r _ m o n d o _ q u e u e s
nop
2006-02-08 11:08:23 +03:00
1 : call i n i t _ c u r _ c p u _ t r a p
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 12:29:17 +03:00
ldx [ % l 0 ] , % o 0
2005-04-17 02:20:36 +04:00
2005-10-05 02:23:20 +04:00
/* Start using proper page size encodings in ctx register. */
2006-02-08 09:13:05 +03:00
sethi % h i ( s p a r c64 _ k e r n _ p r i _ c o n t e x t ) , % g 3
ldx [ % g 3 + % l o ( s p a r c64 _ k e r n _ p r i _ c o n t e x t ) ] , % g 2
mov P R I M A R Y _ C O N T E X T , % g 1
661 : stxa % g 2 , [ % g 1 ] A S I _ D M M U
.section .sun4v_1insn_patch , " ax"
.word 661b
stxa % g 2 , [ % g 1 ] A S I _ M M U
.previous
membar #S y n c
2005-04-17 02:20:36 +04:00
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 12:29:17 +03:00
wrpr % g 0 , 0 , % w s t a t e
2008-10-20 10:33:03 +04:00
sethi % h i ( p r o m _ e n t r y _ l o c k ) , % g 2
1 : ldstub [ % g 2 + % l o ( p r o m _ e n t r y _ l o c k ) ] , % g 1
brnz,p n % g 1 , 1 b
nop
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 12:29:17 +03:00
/ * As a h a c k , p u t & i n i t _ t h r e a d _ u n i o n i n t o % g 6 .
* prom_ w o r l d ( ) l o a d s f r o m h e r e t o r e s t o r e t h e % a s i
* register.
* /
sethi % h i ( i n i t _ t h r e a d _ u n i o n ) , % g 6
or % g 6 , % l o ( i n i t _ t h r e a d _ u n i o n ) , % g 6
2005-04-17 02:20:36 +04:00
2006-02-11 02:39:51 +03:00
sethi % h i ( i s _ s u n 4 v ) , % o 0
lduw [ % o 0 + % l o ( i s _ s u n 4 v ) ] , % o 0
2008-10-20 10:33:03 +04:00
brz,p t % o 0 , 2 f
2006-02-11 02:39:51 +03:00
nop
TRAP_ L O A D _ T R A P _ B L O C K ( % g 2 , % g 3 )
add % g 2 , T R A P _ P E R _ C P U _ F A U L T _ I N F O , % g 2
stxa % g 2 , [ % g 0 ] A S I _ S C R A T C H P A D
/ * Compute p h y s i c a l a d d r e s s :
*
* paddr = k e r n _ b a s e + ( m m f s a _ v a d d r - K E R N B A S E )
* /
sethi % h i ( K E R N B A S E ) , % g 3
sub % g 2 , % g 3 , % g 2
sethi % h i ( k e r n _ b a s e ) , % g 3
ldx [ % g 3 + % l o ( k e r n _ b a s e ) ] , % g 3
add % g 2 , % g 3 , % o 1
2007-09-16 22:51:15 +04:00
sethi % h i ( s p a r c64 _ t t a b l e _ t l 0 ) , % o 0
2006-02-11 02:39:51 +03:00
2007-09-16 22:51:15 +04:00
set p r o m _ s e t _ t r a p _ t a b l e _ n a m e , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ]
mov 2 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ]
mov 0 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ]
stx % o 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ]
stx % o 1 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ]
sethi % h i ( p12 7 5 b u f ) , % g 2
or % g 2 , % l o ( p12 7 5 b u f ) , % g 2
ldx [ % g 2 + 0 x08 ] , % o 1
call % o 1
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0
2006-02-11 02:39:51 +03:00
2008-10-20 10:33:03 +04:00
ba,p t % x c c , 3 f
2006-02-11 02:39:51 +03:00
nop
2008-10-20 10:33:03 +04:00
2 : sethi % h i ( s p a r c64 _ t t a b l e _ t l 0 ) , % o 0
2007-09-16 22:51:15 +04:00
set p r o m _ s e t _ t r a p _ t a b l e _ n a m e , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ]
mov 1 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ]
mov 0 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ]
stx % o 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ]
sethi % h i ( p12 7 5 b u f ) , % g 2
or % g 2 , % l o ( p12 7 5 b u f ) , % g 2
ldx [ % g 2 + 0 x08 ] , % o 1
call % o 1
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0
2005-04-17 02:20:36 +04:00
2008-10-20 10:33:03 +04:00
3 : sethi % h i ( p r o m _ e n t r y _ l o c k ) , % g 2
stb % g 0 , [ % g 2 + % l o ( p r o m _ e n t r y _ l o c k ) ]
ldx [ % l 0 ] , % g 6
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 12:29:17 +03:00
ldx [ % g 6 + T I _ T A S K ] , % g 4
mov 1 , % g 5
sllx % g 5 , T H R E A D _ S H I F T , % g 5
sub % g 5 , ( S T A C K F R A M E _ S Z + S T A C K _ B I A S ) , % g 5
add % g 6 , % g 5 , % s p
mov 0 , % f p
rdpr % p s t a t e , % o 1
or % o 1 , P S T A T E _ I E , % o 1
wrpr % o 1 , 0 , % p s t a t e
call s m p _ c a l l i n
2005-04-17 02:20:36 +04:00
nop
call c p u _ i d l e
mov 0 , % o 0
call c p u _ p a n i c
nop
1 : b,a ,p t % x c c , 1 b
.align 8
sparc64_cpu_startup_end :
