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/ *
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* trampoline. S : S M P c p u b o o t - u p t r a m p o l i n e c o d e .
*
* Copyright ( C ) 1 9 9 5 D a v i d S . M i l l e r ( d a v e m @caip.rutgers.edu)
* Copyright ( C ) 1 9 9 8 J a k u b J e l i n e k ( j j @sunsite.mff.cuni.cz)
* /
# include < l i n u x / i n i t . h >
# include < a s m / h e a d . h >
# include < a s m / p s r . h >
# include < a s m / p a g e . h >
# include < a s m / a s i . h >
# include < a s m / p t r a c e . h >
# include < a s m / v a d d r s . h >
# include < a s m / c o n t r e g s . h >
# include < a s m / t h r e a d _ i n f o . h >
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.globl 4 m _ c p u _ s t a r t u p , _ _ s m p4 m _ p r o c e s s o r _ i d , _ _ l e o n _ p r o c e s s o r _ i d
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.globl 4 d _ c p u _ s t a r t u p , _ _ s m p4 d _ p r o c e s s o r _ i d
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_ _ CPUINIT
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.align 4
/ * When w e s t a r t u p a c p u f o r t h e f i r s t t i m e i t e n t e r s t h i s r o u t i n e .
* This i n i t i a l i z e s t h e c h i p f r o m w h a t e v e r s t a t e t h e p r o m l e f t i t
* in a n d s e t s P I L i n % p s r t o 1 5 , n o i r q s .
* /
sun4m_cpu_startup :
cpu1_startup :
sethi % h i ( t r a p b a s e _ c p u 1 ) , % g 3
b 1 f
or % g 3 , % l o ( t r a p b a s e _ c p u 1 ) , % g 3
cpu2_startup :
sethi % h i ( t r a p b a s e _ c p u 2 ) , % g 3
b 1 f
or % g 3 , % l o ( t r a p b a s e _ c p u 2 ) , % g 3
cpu3_startup :
sethi % h i ( t r a p b a s e _ c p u 3 ) , % g 3
b 1 f
or % g 3 , % l o ( t r a p b a s e _ c p u 3 ) , % g 3
1 :
/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
set ( P S R _ P I L | P S R _ S | P S R _ P S ) , % g 1
wr % g 1 , 0 x0 , % p s r ! t r a p s o f f t h o u g h
WRITE_ P A U S E
/* Our %wim is one behind CWP */
mov 2 , % g 1
wr % g 1 , 0 x0 , % w i m
WRITE_ P A U S E
/* This identifies "this cpu". */
wr % g 3 , 0 x0 , % t b r
WRITE_ P A U S E
/* Give ourselves a stack and curptr. */
set c u r r e n t _ s e t , % g 5
srl % g 3 , 1 0 , % g 4
and % g 4 , 0 x c , % g 4
ld [ % g 5 + % g 4 ] , % g 6
sethi % h i ( T H R E A D _ S I Z E - S T A C K F R A M E _ S Z ) , % s p
or % s p , % l o ( T H R E A D _ S I Z E - S T A C K F R A M E _ S Z ) , % s p
add % g 6 , % s p , % s p
/* Turn on traps (PSR_ET). */
rd % p s r , % g 1
wr % g 1 , P S R _ E T , % p s r ! t r a p s o n
WRITE_ P A U S E
/* Init our caches, etc. */
set p o k e _ s r m m u , % g 5
ld [ % g 5 ] , % g 5
call % g 5
nop
/* Start this processor. */
call s m p4 m _ c a l l i n
nop
b,a s m p _ d o _ c p u _ i d l e
.text
.align 4
smp_do_cpu_idle :
call c p u _ i d l e
mov 0 , % o 0
call c p u _ p a n i c
nop
__smp4m_processor_id :
rd % t b r , % g 2
srl % g 2 , 1 2 , % g 2
and % g 2 , 3 , % g 2
retl
mov % g 1 , % o 7
__smp4d_processor_id :
lda [ % g 0 ] A S I _ M _ V I K I N G _ T M P 1 , % g 2
retl
mov % g 1 , % o 7
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__leon_processor_id :
rd % a s r17 ,% g 2
srl % g 2 ,2 8 ,% g 2
retl
mov % g 1 , % o 7
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/* CPUID in bootbus can be found at PA 0xff0140000 */
# define S U N 4 D _ B O O T B U S _ C P U I D 0 x f01 4 0 0 0 0
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_ _ CPUINIT
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.align 4
sun4d_cpu_startup :
/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
set ( P S R _ P I L | P S R _ S | P S R _ P S ) , % g 1
wr % g 1 , 0 x0 , % p s r ! t r a p s o f f t h o u g h
WRITE_ P A U S E
/* Our %wim is one behind CWP */
mov 2 , % g 1
wr % g 1 , 0 x0 , % w i m
WRITE_ P A U S E
/* Set tbr - we use just one trap table. */
set t r a p b a s e , % g 1
wr % g 1 , 0 x0 , % t b r
WRITE_ P A U S E
/* Get our CPU id out of bootbus */
set S U N 4 D _ B O O T B U S _ C P U I D , % g 3
lduba [ % g 3 ] A S I _ M _ C T L , % g 3
and % g 3 , 0 x f8 , % g 3
srl % g 3 , 3 , % g 1
sta % g 1 , [ % g 0 ] A S I _ M _ V I K I N G _ T M P 1
/* Give ourselves a stack and curptr. */
set c u r r e n t _ s e t , % g 5
srl % g 3 , 1 , % g 4
ld [ % g 5 + % g 4 ] , % g 6
sethi % h i ( T H R E A D _ S I Z E - S T A C K F R A M E _ S Z ) , % s p
or % s p , % l o ( T H R E A D _ S I Z E - S T A C K F R A M E _ S Z ) , % s p
add % g 6 , % s p , % s p
/* Turn on traps (PSR_ET). */
rd % p s r , % g 1
wr % g 1 , P S R _ E T , % p s r ! t r a p s o n
WRITE_ P A U S E
/* Init our caches, etc. */
set p o k e _ s r m m u , % g 5
ld [ % g 5 ] , % g 5
call % g 5
nop
/* Start this processor. */
call s m p4 d _ c a l l i n
nop
b,a s m p _ d o _ c p u _ i d l e
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# ifdef C O N F I G _ S P A R C _ L E O N
_ _ CPUINIT
.align 4
.global _ s m p _ c p u _ s t a r t u p , s m p _ p e n g u i n _ c t a b l e
leon_smp_cpu_startup :
set s m p _ p e n g u i n _ c t a b l e ,% g 1
ld [ % g 1 + 4 ] ,% g 1
srl % g 1 ,4 ,% g 1
set 0 x00 0 0 0 1 0 0 ,% g 5 / * S R M M U _ C T X T B L _ P T R * /
sta % g 1 , [ % g 5 ] A S I _ M _ M M U R E G S
/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
set ( P S R _ P I L | P S R _ S | P S R _ P S ) , % g 1
wr % g 1 , 0 x0 , % p s r ! t r a p s o f f t h o u g h
WRITE_ P A U S E
/* Our %wim is one behind CWP */
mov 2 , % g 1
wr % g 1 , 0 x0 , % w i m
WRITE_ P A U S E
/* Set tbr - we use just one trap table. */
set t r a p b a s e , % g 1
wr % g 1 , 0 x0 , % t b r
WRITE_ P A U S E
/* Get our CPU id */
rd % a s r17 ,% g 3
/* Give ourselves a stack and curptr. */
set c u r r e n t _ s e t , % g 5
srl % g 3 , 2 8 , % g 4
sll % g 4 , 2 , % g 4
ld [ % g 5 + % g 4 ] , % g 6
sethi % h i ( T H R E A D _ S I Z E - S T A C K F R A M E _ S Z ) , % s p
or % s p , % l o ( T H R E A D _ S I Z E - S T A C K F R A M E _ S Z ) , % s p
add % g 6 , % s p , % s p
/* Turn on traps (PSR_ET). */
rd % p s r , % g 1
wr % g 1 , P S R _ E T , % p s r ! t r a p s o n
WRITE_ P A U S E
/* Init our caches, etc. */
set p o k e _ s r m m u , % g 5
ld [ % g 5 ] , % g 5
call % g 5
nop
/* Start this processor. */
call l e o n _ c a l l i n
nop
b,a s m p _ d o _ c p u _ i d l e
# endif
