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linux/drivers/net/dsa/sja1105/sja1105_mdio.c

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net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-08 12:25:38 +03:00
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2021, NXP Semiconductors
*/
net: dsa: sja1105: migrate to xpcs for SGMII There is a desire to use the generic driver for the Synopsys XPCS located in drivers/net/pcs, and to achieve that, the sja1105 driver must expose an MDIO bus for the SGMII PCS, because the XPCS probes as an mdio_device. In preparation of the SJA1110 which in fact has a different access procedure for the SJA1105, we register this PCS MDIO bus once in the common code, but we implement function pointers for the read and write methods. In this patch there is a single implementation for them. There is exactly one MDIO bus for the PCS, this will contain all PCSes at MDIO addresses equal to the port number. We delete a bunch of hardware support code because the xpcs driver already does what we need. We need to hack up the MDIO reads for the PHY ID, since our XPCS instantiation returns zeroes and there are some specific fixups which need to be applied by the xpcs driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11 23:05:28 +03:00
#include <linux/pcs/pcs-xpcs.h>
net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-08 12:25:38 +03:00
#include <linux/of_mdio.h>
#include "sja1105.h"
net: dsa: sja1105: register the PCS MDIO bus for SJA1110 On the SJA1110, the PCS of each SERDES-capable port is accessed through a different memory window which is 0x100 bytes in size, denoted by "pcs_base". In each PCS register access window, the XPCS MMDs are accessed in an indirect way: in pages/banks of up to 0x100 addresses each. Changing the page/bank is done by writing to a special register at the end of the access window. The MDIO register map accessed indirectly through the indirect banked method described above is similar to what SJA1105 has: upper 5 bits are the MMD, lower 16 bits are the MDIO address within that MMD. Since the PHY ID reported by the XPCS inside SJA1110 is also all zeroes (like SJA1105), we need to trap those reads and return a fake PHY ID so that the xpcs driver can apply some specific fixups for our integration. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11 23:05:29 +03:00
#define SJA1110_PCS_BANK_REG SJA1110_SPI_ADDR(0x3fc)
net: dsa: sja1105: migrate to xpcs for SGMII There is a desire to use the generic driver for the Synopsys XPCS located in drivers/net/pcs, and to achieve that, the sja1105 driver must expose an MDIO bus for the SGMII PCS, because the XPCS probes as an mdio_device. In preparation of the SJA1110 which in fact has a different access procedure for the SJA1105, we register this PCS MDIO bus once in the common code, but we implement function pointers for the read and write methods. In this patch there is a single implementation for them. There is exactly one MDIO bus for the PCS, this will contain all PCSes at MDIO addresses equal to the port number. We delete a bunch of hardware support code because the xpcs driver already does what we need. We need to hack up the MDIO reads for the PHY ID, since our XPCS instantiation returns zeroes and there are some specific fixups which need to be applied by the xpcs driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11 23:05:28 +03:00
int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg)
{
struct sja1105_mdio_private *mdio_priv = bus->priv;
struct sja1105_private *priv = mdio_priv->priv;
u64 addr;
u32 tmp;
u16 mmd;
int rc;
if (!(reg & MII_ADDR_C45))
return -EINVAL;
mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;
addr = (mmd << 16) | (reg & GENMASK(15, 0));
if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2)
return 0xffff;
if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1)
return NXP_SJA1105_XPCS_ID >> 16;
if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2)
return NXP_SJA1105_XPCS_ID & GENMASK(15, 0);
rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
if (rc < 0)
return rc;
return tmp & 0xffff;
}
int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
{
struct sja1105_mdio_private *mdio_priv = bus->priv;
struct sja1105_private *priv = mdio_priv->priv;
u64 addr;
u32 tmp;
u16 mmd;
if (!(reg & MII_ADDR_C45))
return -EINVAL;
mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;
addr = (mmd << 16) | (reg & GENMASK(15, 0));
tmp = val;
if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2)
return -EINVAL;
return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
}
net: dsa: sja1105: register the PCS MDIO bus for SJA1110 On the SJA1110, the PCS of each SERDES-capable port is accessed through a different memory window which is 0x100 bytes in size, denoted by "pcs_base". In each PCS register access window, the XPCS MMDs are accessed in an indirect way: in pages/banks of up to 0x100 addresses each. Changing the page/bank is done by writing to a special register at the end of the access window. The MDIO register map accessed indirectly through the indirect banked method described above is similar to what SJA1105 has: upper 5 bits are the MMD, lower 16 bits are the MDIO address within that MMD. Since the PHY ID reported by the XPCS inside SJA1110 is also all zeroes (like SJA1105), we need to trap those reads and return a fake PHY ID so that the xpcs driver can apply some specific fixups for our integration. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11 23:05:29 +03:00
int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg)
{
struct sja1105_mdio_private *mdio_priv = bus->priv;
struct sja1105_private *priv = mdio_priv->priv;
const struct sja1105_regs *regs = priv->info->regs;
int offset, bank;
u64 addr;
u32 tmp;
u16 mmd;
int rc;
if (!(reg & MII_ADDR_C45))
return -EINVAL;
if (regs->pcs_base[phy] == SJA1105_RSV_ADDR)
return -ENODEV;
mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;
addr = (mmd << 16) | (reg & GENMASK(15, 0));
if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1)
return NXP_SJA1110_XPCS_ID >> 16;
if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2)
return NXP_SJA1110_XPCS_ID & GENMASK(15, 0);
bank = addr >> 8;
offset = addr & GENMASK(7, 0);
/* This addressing scheme reserves register 0xff for the bank address
* register, so that can never be addressed.
*/
if (WARN_ON(offset == 0xff))
return -ENODEV;
tmp = bank;
rc = sja1105_xfer_u32(priv, SPI_WRITE,
regs->pcs_base[phy] + SJA1110_PCS_BANK_REG,
&tmp, NULL);
if (rc < 0)
return rc;
rc = sja1105_xfer_u32(priv, SPI_READ, regs->pcs_base[phy] + offset,
&tmp, NULL);
if (rc < 0)
return rc;
return tmp & 0xffff;
}
int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
{
struct sja1105_mdio_private *mdio_priv = bus->priv;
struct sja1105_private *priv = mdio_priv->priv;
const struct sja1105_regs *regs = priv->info->regs;
int offset, bank;
u64 addr;
u32 tmp;
u16 mmd;
int rc;
if (!(reg & MII_ADDR_C45))
return -EINVAL;
if (regs->pcs_base[phy] == SJA1105_RSV_ADDR)
return -ENODEV;
mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;
addr = (mmd << 16) | (reg & GENMASK(15, 0));
bank = addr >> 8;
offset = addr & GENMASK(7, 0);
/* This addressing scheme reserves register 0xff for the bank address
* register, so that can never be addressed.
*/
if (WARN_ON(offset == 0xff))
return -ENODEV;
tmp = bank;
rc = sja1105_xfer_u32(priv, SPI_WRITE,
regs->pcs_base[phy] + SJA1110_PCS_BANK_REG,
&tmp, NULL);
if (rc < 0)
return rc;
tmp = val;
return sja1105_xfer_u32(priv, SPI_WRITE, regs->pcs_base[phy] + offset,
&tmp, NULL);
}
net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-08 12:25:38 +03:00
enum sja1105_mdio_opcode {
SJA1105_C45_ADDR = 0,
SJA1105_C22 = 1,
SJA1105_C45_DATA = 2,
SJA1105_C45_DATA_AUTOINC = 3,
};
static u64 sja1105_base_t1_encode_addr(struct sja1105_private *priv,
int phy, enum sja1105_mdio_opcode op,
int xad)
{
const struct sja1105_regs *regs = priv->info->regs;
return regs->mdio_100base_t1 | (phy << 7) | (op << 5) | (xad << 0);
}
static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg)
{
struct sja1105_mdio_private *mdio_priv = bus->priv;
struct sja1105_private *priv = mdio_priv->priv;
u64 addr;
u32 tmp;
int rc;
if (reg & MII_ADDR_C45) {
u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;
addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR,
mmd);
tmp = reg & MII_REGADDR_C45_MASK;
rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
if (rc < 0)
return rc;
addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA,
mmd);
rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
if (rc < 0)
return rc;
return tmp & 0xffff;
}
/* Clause 22 read */
addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);
rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
if (rc < 0)
return rc;
return tmp & 0xffff;
}
static int sja1105_base_t1_mdio_write(struct mii_bus *bus, int phy, int reg,
u16 val)
{
struct sja1105_mdio_private *mdio_priv = bus->priv;
struct sja1105_private *priv = mdio_priv->priv;
u64 addr;
u32 tmp;
int rc;
if (reg & MII_ADDR_C45) {
u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;
addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR,
mmd);
tmp = reg & MII_REGADDR_C45_MASK;
rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
if (rc < 0)
return rc;
addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA,
mmd);
tmp = val & 0xffff;
rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
if (rc < 0)
return rc;
return 0;
}
/* Clause 22 write */
addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);
tmp = val & 0xffff;
return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
}
static int sja1105_base_tx_mdio_read(struct mii_bus *bus, int phy, int reg)
{
struct sja1105_mdio_private *mdio_priv = bus->priv;
struct sja1105_private *priv = mdio_priv->priv;
const struct sja1105_regs *regs = priv->info->regs;
u32 tmp;
int rc;
rc = sja1105_xfer_u32(priv, SPI_READ, regs->mdio_100base_tx + reg,
&tmp, NULL);
if (rc < 0)
return rc;
return tmp & 0xffff;
}
static int sja1105_base_tx_mdio_write(struct mii_bus *bus, int phy, int reg,
u16 val)
{
struct sja1105_mdio_private *mdio_priv = bus->priv;
struct sja1105_private *priv = mdio_priv->priv;
const struct sja1105_regs *regs = priv->info->regs;
u32 tmp = val;
return sja1105_xfer_u32(priv, SPI_WRITE, regs->mdio_100base_tx + reg,
&tmp, NULL);
}
static int sja1105_mdiobus_base_tx_register(struct sja1105_private *priv,
struct device_node *mdio_node)
{
struct sja1105_mdio_private *mdio_priv;
struct device_node *np;
struct mii_bus *bus;
int rc = 0;
net: dsa: sja1105: fix use-after-free after calling of_find_compatible_node, or worse It seems that of_find_compatible_node has a weird calling convention in which it calls of_node_put() on the "from" node argument, instead of leaving that up to the caller. This comes from the fact that of_find_compatible_node with a non-NULL "from" argument it only supposed to be used as the iterator function of for_each_compatible_node(). OF iterator functions call of_node_get on the next OF node and of_node_put() on the previous one. When of_find_compatible_node calls of_node_put, it actually never expects the refcount to drop to zero, because the call is done under the atomic devtree_lock context, and when the refcount drops to zero it triggers a kobject and a sysfs file deletion, which assume blocking context. So any driver call to of_find_compatible_node is probably buggy because an unexpected of_node_put() takes place. What should be done is to use the of_get_compatible_child() function. Fixes: 5a8f09748ee7 ("net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX") Link: https://lore.kernel.org/netdev/20210814010139.kzryimmp4rizlznt@skbuf/ Suggested-by: Frank Rowand <frowand.list@gmail.com> Suggested-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-17 17:52:45 +03:00
np = of_get_compatible_child(mdio_node, "nxp,sja1110-base-tx-mdio");
net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-08 12:25:38 +03:00
if (!np)
return 0;
if (!of_device_is_available(np))
goto out_put_np;
bus = mdiobus_alloc_size(sizeof(*mdio_priv));
if (!bus) {
rc = -ENOMEM;
goto out_put_np;
}
bus->name = "SJA1110 100base-TX MDIO bus";
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-base-tx",
dev_name(priv->ds->dev));
bus->read = sja1105_base_tx_mdio_read;
bus->write = sja1105_base_tx_mdio_write;
bus->parent = priv->ds->dev;
mdio_priv = bus->priv;
mdio_priv->priv = priv;
rc = of_mdiobus_register(bus, np);
if (rc) {
mdiobus_free(bus);
goto out_put_np;
}
priv->mdio_base_tx = bus;
out_put_np:
of_node_put(np);
net: dsa: sja1105: Fix assigned yet unused return code rc The return code variable rc is being set to return error values in two places in sja1105_mdiobus_base_tx_register and yet it is not being returned, the function always returns 0 instead. Fix this by replacing the return 0 with the return code rc. Addresses-Coverity: ("Unused value") Fixes: 5a8f09748ee7 ("net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX") Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-09 18:43:53 +01:00
return rc;
net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-08 12:25:38 +03:00
}
static void sja1105_mdiobus_base_tx_unregister(struct sja1105_private *priv)
{
if (!priv->mdio_base_tx)
return;
mdiobus_unregister(priv->mdio_base_tx);
mdiobus_free(priv->mdio_base_tx);
priv->mdio_base_tx = NULL;
}
static int sja1105_mdiobus_base_t1_register(struct sja1105_private *priv,
struct device_node *mdio_node)
{
struct sja1105_mdio_private *mdio_priv;
struct device_node *np;
struct mii_bus *bus;
int rc = 0;
net: dsa: sja1105: fix use-after-free after calling of_find_compatible_node, or worse It seems that of_find_compatible_node has a weird calling convention in which it calls of_node_put() on the "from" node argument, instead of leaving that up to the caller. This comes from the fact that of_find_compatible_node with a non-NULL "from" argument it only supposed to be used as the iterator function of for_each_compatible_node(). OF iterator functions call of_node_get on the next OF node and of_node_put() on the previous one. When of_find_compatible_node calls of_node_put, it actually never expects the refcount to drop to zero, because the call is done under the atomic devtree_lock context, and when the refcount drops to zero it triggers a kobject and a sysfs file deletion, which assume blocking context. So any driver call to of_find_compatible_node is probably buggy because an unexpected of_node_put() takes place. What should be done is to use the of_get_compatible_child() function. Fixes: 5a8f09748ee7 ("net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX") Link: https://lore.kernel.org/netdev/20210814010139.kzryimmp4rizlznt@skbuf/ Suggested-by: Frank Rowand <frowand.list@gmail.com> Suggested-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-17 17:52:45 +03:00
np = of_get_compatible_child(mdio_node, "nxp,sja1110-base-t1-mdio");
net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-08 12:25:38 +03:00
if (!np)
return 0;
if (!of_device_is_available(np))
goto out_put_np;
bus = mdiobus_alloc_size(sizeof(*mdio_priv));
if (!bus) {
rc = -ENOMEM;
goto out_put_np;
}
bus->name = "SJA1110 100base-T1 MDIO bus";
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-base-t1",
dev_name(priv->ds->dev));
bus->read = sja1105_base_t1_mdio_read;
bus->write = sja1105_base_t1_mdio_write;
bus->parent = priv->ds->dev;
mdio_priv = bus->priv;
mdio_priv->priv = priv;
rc = of_mdiobus_register(bus, np);
if (rc) {
mdiobus_free(bus);
goto out_put_np;
}
priv->mdio_base_t1 = bus;
out_put_np:
of_node_put(np);
return rc;
}
static void sja1105_mdiobus_base_t1_unregister(struct sja1105_private *priv)
{
if (!priv->mdio_base_t1)
return;
mdiobus_unregister(priv->mdio_base_t1);
mdiobus_free(priv->mdio_base_t1);
priv->mdio_base_t1 = NULL;
}
net: dsa: sja1105: migrate to xpcs for SGMII There is a desire to use the generic driver for the Synopsys XPCS located in drivers/net/pcs, and to achieve that, the sja1105 driver must expose an MDIO bus for the SGMII PCS, because the XPCS probes as an mdio_device. In preparation of the SJA1110 which in fact has a different access procedure for the SJA1105, we register this PCS MDIO bus once in the common code, but we implement function pointers for the read and write methods. In this patch there is a single implementation for them. There is exactly one MDIO bus for the PCS, this will contain all PCSes at MDIO addresses equal to the port number. We delete a bunch of hardware support code because the xpcs driver already does what we need. We need to hack up the MDIO reads for the PHY ID, since our XPCS instantiation returns zeroes and there are some specific fixups which need to be applied by the xpcs driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11 23:05:28 +03:00
static int sja1105_mdiobus_pcs_register(struct sja1105_private *priv)
{
struct sja1105_mdio_private *mdio_priv;
struct dsa_switch *ds = priv->ds;
struct mii_bus *bus;
int rc = 0;
int port;
if (!priv->info->pcs_mdio_read || !priv->info->pcs_mdio_write)
return 0;
bus = mdiobus_alloc_size(sizeof(*mdio_priv));
if (!bus)
return -ENOMEM;
bus->name = "SJA1105 PCS MDIO bus";
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-pcs",
dev_name(ds->dev));
bus->read = priv->info->pcs_mdio_read;
bus->write = priv->info->pcs_mdio_write;
bus->parent = ds->dev;
/* There is no PHY on this MDIO bus => mask out all PHY addresses
* from auto probing.
*/
bus->phy_mask = ~0;
mdio_priv = bus->priv;
mdio_priv->priv = priv;
rc = mdiobus_register(bus);
if (rc) {
mdiobus_free(bus);
return rc;
}
for (port = 0; port < ds->num_ports; port++) {
struct mdio_device *mdiodev;
struct dw_xpcs *xpcs;
if (dsa_is_unused_port(ds, port))
continue;
net: dsa: sja1105: plug in support for 2500base-x The MAC treats 2500base-x same as SGMII (yay for that) except that it must be set to a different speed. Extend all places that check for SGMII to also check for 2500base-x. Also add the missing 2500base-x compatibility matrix entry for SJA1110D. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11 23:05:31 +03:00
if (priv->phy_mode[port] != PHY_INTERFACE_MODE_SGMII &&
priv->phy_mode[port] != PHY_INTERFACE_MODE_2500BASEX)
net: dsa: sja1105: migrate to xpcs for SGMII There is a desire to use the generic driver for the Synopsys XPCS located in drivers/net/pcs, and to achieve that, the sja1105 driver must expose an MDIO bus for the SGMII PCS, because the XPCS probes as an mdio_device. In preparation of the SJA1110 which in fact has a different access procedure for the SJA1105, we register this PCS MDIO bus once in the common code, but we implement function pointers for the read and write methods. In this patch there is a single implementation for them. There is exactly one MDIO bus for the PCS, this will contain all PCSes at MDIO addresses equal to the port number. We delete a bunch of hardware support code because the xpcs driver already does what we need. We need to hack up the MDIO reads for the PHY ID, since our XPCS instantiation returns zeroes and there are some specific fixups which need to be applied by the xpcs driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11 23:05:28 +03:00
continue;
mdiodev = mdio_device_create(bus, port);
if (IS_ERR(mdiodev)) {
rc = PTR_ERR(mdiodev);
goto out_pcs_free;
}
xpcs = xpcs_create(mdiodev, priv->phy_mode[port]);
if (IS_ERR(xpcs)) {
rc = PTR_ERR(xpcs);
goto out_pcs_free;
}
priv->xpcs[port] = xpcs;
}
priv->mdio_pcs = bus;
return 0;
out_pcs_free:
for (port = 0; port < ds->num_ports; port++) {
if (!priv->xpcs[port])
continue;
mdio_device_free(priv->xpcs[port]->mdiodev);
xpcs_destroy(priv->xpcs[port]);
priv->xpcs[port] = NULL;
}
mdiobus_unregister(bus);
mdiobus_free(bus);
return rc;
}
static void sja1105_mdiobus_pcs_unregister(struct sja1105_private *priv)
{
struct dsa_switch *ds = priv->ds;
int port;
if (!priv->mdio_pcs)
return;
for (port = 0; port < ds->num_ports; port++) {
if (!priv->xpcs[port])
continue;
mdio_device_free(priv->xpcs[port]->mdiodev);
xpcs_destroy(priv->xpcs[port]);
priv->xpcs[port] = NULL;
}
mdiobus_unregister(priv->mdio_pcs);
mdiobus_free(priv->mdio_pcs);
priv->mdio_pcs = NULL;
}
net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-08 12:25:38 +03:00
int sja1105_mdiobus_register(struct dsa_switch *ds)
{
struct sja1105_private *priv = ds->priv;
const struct sja1105_regs *regs = priv->info->regs;
struct device_node *switch_node = ds->dev->of_node;
struct device_node *mdio_node;
int rc;
net: dsa: sja1105: migrate to xpcs for SGMII There is a desire to use the generic driver for the Synopsys XPCS located in drivers/net/pcs, and to achieve that, the sja1105 driver must expose an MDIO bus for the SGMII PCS, because the XPCS probes as an mdio_device. In preparation of the SJA1110 which in fact has a different access procedure for the SJA1105, we register this PCS MDIO bus once in the common code, but we implement function pointers for the read and write methods. In this patch there is a single implementation for them. There is exactly one MDIO bus for the PCS, this will contain all PCSes at MDIO addresses equal to the port number. We delete a bunch of hardware support code because the xpcs driver already does what we need. We need to hack up the MDIO reads for the PHY ID, since our XPCS instantiation returns zeroes and there are some specific fixups which need to be applied by the xpcs driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11 23:05:28 +03:00
rc = sja1105_mdiobus_pcs_register(priv);
if (rc)
return rc;
net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-08 12:25:38 +03:00
mdio_node = of_get_child_by_name(switch_node, "mdios");
if (!mdio_node)
return 0;
if (!of_device_is_available(mdio_node))
goto out_put_mdio_node;
if (regs->mdio_100base_tx != SJA1105_RSV_ADDR) {
rc = sja1105_mdiobus_base_tx_register(priv, mdio_node);
if (rc)
goto err_put_mdio_node;
}
if (regs->mdio_100base_t1 != SJA1105_RSV_ADDR) {
rc = sja1105_mdiobus_base_t1_register(priv, mdio_node);
if (rc)
goto err_free_base_tx_mdiobus;
}
out_put_mdio_node:
of_node_put(mdio_node);
return 0;
err_free_base_tx_mdiobus:
sja1105_mdiobus_base_tx_unregister(priv);
err_put_mdio_node:
of_node_put(mdio_node);
net: dsa: sja1105: migrate to xpcs for SGMII There is a desire to use the generic driver for the Synopsys XPCS located in drivers/net/pcs, and to achieve that, the sja1105 driver must expose an MDIO bus for the SGMII PCS, because the XPCS probes as an mdio_device. In preparation of the SJA1110 which in fact has a different access procedure for the SJA1105, we register this PCS MDIO bus once in the common code, but we implement function pointers for the read and write methods. In this patch there is a single implementation for them. There is exactly one MDIO bus for the PCS, this will contain all PCSes at MDIO addresses equal to the port number. We delete a bunch of hardware support code because the xpcs driver already does what we need. We need to hack up the MDIO reads for the PHY ID, since our XPCS instantiation returns zeroes and there are some specific fixups which need to be applied by the xpcs driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11 23:05:28 +03:00
sja1105_mdiobus_pcs_unregister(priv);
net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-08 12:25:38 +03:00
return rc;
}
void sja1105_mdiobus_unregister(struct dsa_switch *ds)
{
struct sja1105_private *priv = ds->priv;
sja1105_mdiobus_base_t1_unregister(priv);
sja1105_mdiobus_base_tx_unregister(priv);
net: dsa: sja1105: migrate to xpcs for SGMII There is a desire to use the generic driver for the Synopsys XPCS located in drivers/net/pcs, and to achieve that, the sja1105 driver must expose an MDIO bus for the SGMII PCS, because the XPCS probes as an mdio_device. In preparation of the SJA1110 which in fact has a different access procedure for the SJA1105, we register this PCS MDIO bus once in the common code, but we implement function pointers for the read and write methods. In this patch there is a single implementation for them. There is exactly one MDIO bus for the PCS, this will contain all PCSes at MDIO addresses equal to the port number. We delete a bunch of hardware support code because the xpcs driver already does what we need. We need to hack up the MDIO reads for the PHY ID, since our XPCS instantiation returns zeroes and there are some specific fixups which need to be applied by the xpcs driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11 23:05:28 +03:00
sja1105_mdiobus_pcs_unregister(priv);
net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-08 12:25:38 +03:00
}
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