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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
* cs42l42 . h - - CS42L42 ALSA SoC audio driver header
*
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* Copyright 2016 - 2022 Cirrus Logic , Inc .
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*
* Author : James Schulman < james . schulman @ cirrus . com >
* Author : Brian Austin < brian . austin @ cirrus . com >
* Author : Michael White < michael . white @ cirrus . com >
*/
# ifndef __CS42L42_H__
# define __CS42L42_H__
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# include <dt-bindings/sound/cs42l42.h>
# include <linux/device.h>
# include <linux/gpio.h>
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# include <linux/mutex.h>
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# include <linux/regmap.h>
# include <linux/regulator/consumer.h>
ASoC: cs42l42: Add SoundWire support
This adds support for using CS42L42 as a SoundWire device.
SoundWire-specifics are kept separate from the I2S implementation as
much as possible, aiming to limit the risk of breaking the I2C+I2S
support.
There are some important differences in the silicon behaviour between
I2S and SoundWire mode that are reflected in the implementation:
- ASP (I2S) most not be used in SoundWire mode because the two interfaces
share pins.
- The SoundWire capture (record) port only supports 1 channel. It does
not have left-to-right duplication like the ASP.
- DP2 can only be prepared if the HP has powered-up. DP1 can only be
prepared if the ADC has powered-up. (This ordering restriction does
not exist for ASPs.) The SoundWire core port-prepare step is
triggered by the DAI-link prepare(). This happens before the
codec DAI prepare() or the DAPM sequence so these cannot be used
to enable HP/ADC. Instead the HP/ADC enable/disable are done during
the port_prep callback.
- The SRCs are an integral part of the audio chain but in silicon their
power control is linked to the ASP. There is no equivalent power link
to SoundWire DPs so the driver must take "manual" control of SRC power.
- The SoundWire control registers occupy the lower part of the SoundWire
address space so cs42l42 registers are offset by 0x8000 (non-paged) in
SoundWire mode.
- Register addresses are 8-bit paged in I2C mode but 16-bit unpaged in
SoundWire.
- Special procedures are needed on register read/writes to (a) ensure
that the previous internal bus transaction has completed, and
(b) handle delayed read results, when the read value could not be
returned within the SoundWire read command.
There are also some differences in driver implementation between I2S
and SoundWire operation:
- CS42L42 I2S does not runtime_suspend, but runtime_suspend/resume support
has been added into the driver in SoundWire mode as the most convenient
way to power-up the bus manager and to handle the unattach_request
condition, though the CS42L42 chip does not itself suspend or resume.
- Intel SoundWire host controllers have a low-power clock-stop mode that
requires resetting all peripherals when resuming. This means that the
interrupt registers will be reset in between the interrupt being
generated and the interrupt being handled, and since the interrupt
status is debounced, these values may not be accurate immediately,
and may cause spurious unplug events before settling.
- As in I2S mode, the PLL is only used while audio is active because
of clocking quirks in the silicon. For SoundWire the cs42l42_pll_config()
is deferred until the DAI prepare(), to allow the cs42l42_bus_config()
callback to set the SCLK.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-7-sbinding@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-01-27 16:51:09 +00:00
# include <linux/soundwire/sdw.h>
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# include <sound/jack.h>
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# include <sound/cs42l42.h>
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# include <sound/soc-component.h>
# include <sound/soc-dai.h>
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struct cs42l42_private {
struct regmap * regmap ;
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struct device * dev ;
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struct regulator_bulk_data supplies [ CS42L42_NUM_SUPPLIES ] ;
struct gpio_desc * reset_gpio ;
struct completion pdn_done ;
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struct snd_soc_jack * jack ;
ASoC: cs42l42: Add SoundWire support
This adds support for using CS42L42 as a SoundWire device.
SoundWire-specifics are kept separate from the I2S implementation as
much as possible, aiming to limit the risk of breaking the I2C+I2S
support.
There are some important differences in the silicon behaviour between
I2S and SoundWire mode that are reflected in the implementation:
- ASP (I2S) most not be used in SoundWire mode because the two interfaces
share pins.
- The SoundWire capture (record) port only supports 1 channel. It does
not have left-to-right duplication like the ASP.
- DP2 can only be prepared if the HP has powered-up. DP1 can only be
prepared if the ADC has powered-up. (This ordering restriction does
not exist for ASPs.) The SoundWire core port-prepare step is
triggered by the DAI-link prepare(). This happens before the
codec DAI prepare() or the DAPM sequence so these cannot be used
to enable HP/ADC. Instead the HP/ADC enable/disable are done during
the port_prep callback.
- The SRCs are an integral part of the audio chain but in silicon their
power control is linked to the ASP. There is no equivalent power link
to SoundWire DPs so the driver must take "manual" control of SRC power.
- The SoundWire control registers occupy the lower part of the SoundWire
address space so cs42l42 registers are offset by 0x8000 (non-paged) in
SoundWire mode.
- Register addresses are 8-bit paged in I2C mode but 16-bit unpaged in
SoundWire.
- Special procedures are needed on register read/writes to (a) ensure
that the previous internal bus transaction has completed, and
(b) handle delayed read results, when the read value could not be
returned within the SoundWire read command.
There are also some differences in driver implementation between I2S
and SoundWire operation:
- CS42L42 I2S does not runtime_suspend, but runtime_suspend/resume support
has been added into the driver in SoundWire mode as the most convenient
way to power-up the bus manager and to handle the unattach_request
condition, though the CS42L42 chip does not itself suspend or resume.
- Intel SoundWire host controllers have a low-power clock-stop mode that
requires resetting all peripherals when resuming. This means that the
interrupt registers will be reset in between the interrupt being
generated and the interrupt being handled, and since the interrupt
status is debounced, these values may not be accurate immediately,
and may cause spurious unplug events before settling.
- As in I2S mode, the PLL is only used while audio is active because
of clocking quirks in the silicon. For SoundWire the cs42l42_pll_config()
is deferred until the DAI prepare(), to allow the cs42l42_bus_config()
callback to set the SCLK.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-7-sbinding@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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struct sdw_slave * sdw_peripheral ;
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struct mutex irq_lock ;
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int devid ;
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int irq ;
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int pll_config ;
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u32 sclk ;
ASoC: cs42l42: Add SoundWire support
This adds support for using CS42L42 as a SoundWire device.
SoundWire-specifics are kept separate from the I2S implementation as
much as possible, aiming to limit the risk of breaking the I2C+I2S
support.
There are some important differences in the silicon behaviour between
I2S and SoundWire mode that are reflected in the implementation:
- ASP (I2S) most not be used in SoundWire mode because the two interfaces
share pins.
- The SoundWire capture (record) port only supports 1 channel. It does
not have left-to-right duplication like the ASP.
- DP2 can only be prepared if the HP has powered-up. DP1 can only be
prepared if the ADC has powered-up. (This ordering restriction does
not exist for ASPs.) The SoundWire core port-prepare step is
triggered by the DAI-link prepare(). This happens before the
codec DAI prepare() or the DAPM sequence so these cannot be used
to enable HP/ADC. Instead the HP/ADC enable/disable are done during
the port_prep callback.
- The SRCs are an integral part of the audio chain but in silicon their
power control is linked to the ASP. There is no equivalent power link
to SoundWire DPs so the driver must take "manual" control of SRC power.
- The SoundWire control registers occupy the lower part of the SoundWire
address space so cs42l42 registers are offset by 0x8000 (non-paged) in
SoundWire mode.
- Register addresses are 8-bit paged in I2C mode but 16-bit unpaged in
SoundWire.
- Special procedures are needed on register read/writes to (a) ensure
that the previous internal bus transaction has completed, and
(b) handle delayed read results, when the read value could not be
returned within the SoundWire read command.
There are also some differences in driver implementation between I2S
and SoundWire operation:
- CS42L42 I2S does not runtime_suspend, but runtime_suspend/resume support
has been added into the driver in SoundWire mode as the most convenient
way to power-up the bus manager and to handle the unattach_request
condition, though the CS42L42 chip does not itself suspend or resume.
- Intel SoundWire host controllers have a low-power clock-stop mode that
requires resetting all peripherals when resuming. This means that the
interrupt registers will be reset in between the interrupt being
generated and the interrupt being handled, and since the interrupt
status is debounced, these values may not be accurate immediately,
and may cause spurious unplug events before settling.
- As in I2S mode, the PLL is only used while audio is active because
of clocking quirks in the silicon. For SoundWire the cs42l42_pll_config()
is deferred until the DAI prepare(), to allow the cs42l42_bus_config()
callback to set the SCLK.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-7-sbinding@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-01-27 16:51:09 +00:00
u32 sample_rate ;
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u32 bclk_ratio ;
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u8 plug_state ;
u8 hs_type ;
u8 ts_inv ;
u8 ts_dbnc_rise ;
u8 ts_dbnc_fall ;
u8 btn_det_init_dbnce ;
u8 btn_det_event_dbnce ;
u8 bias_thresholds [ CS42L42_NUM_BIASES ] ;
u8 hs_bias_ramp_rate ;
u8 hs_bias_ramp_time ;
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u8 hs_bias_sense_en ;
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u8 stream_use ;
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bool hp_adc_up_pending ;
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bool suspended ;
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bool sdw_waiting_first_unattach ;
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bool init_done ;
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} ;
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extern const struct regmap_range_cfg cs42l42_page_range ;
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extern const struct regmap_config cs42l42_regmap ;
extern const struct snd_soc_component_driver cs42l42_soc_component ;
extern struct snd_soc_dai_driver cs42l42_dai ;
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bool cs42l42_readable_register ( struct device * dev , unsigned int reg ) ;
bool cs42l42_volatile_register ( struct device * dev , unsigned int reg ) ;
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int cs42l42_pll_config ( struct snd_soc_component * component ,
unsigned int clk , unsigned int sample_rate ) ;
void cs42l42_src_config ( struct snd_soc_component * component , unsigned int sample_rate ) ;
int cs42l42_mute_stream ( struct snd_soc_dai * dai , int mute , int stream ) ;
irqreturn_t cs42l42_irq_thread ( int irq , void * data ) ;
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int cs42l42_suspend ( struct device * dev ) ;
int cs42l42_resume ( struct device * dev ) ;
void cs42l42_resume_restore ( struct device * dev ) ;
int cs42l42_common_probe ( struct cs42l42_private * cs42l42 ,
const struct snd_soc_component_driver * component_drv ,
struct snd_soc_dai_driver * dai ) ;
int cs42l42_init ( struct cs42l42_private * cs42l42 ) ;
void cs42l42_common_remove ( struct cs42l42_private * cs42l42 ) ;
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# endif /* __CS42L42_H__ */
