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linux/drivers/clk/ti/clk-54xx.c

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-04 10:11:33 +02:00
// SPDX-License-Identifier: GPL-2.0-only
CLK: TI: add omap5 clock init file clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 17:15:51 +03:00
/*
* OMAP5 Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo (t-kristo@ti.com)
*/
#include <linux/kernel.h>
#include <linux/list.h>
clk: ti: Drop use of clk-private.h These modules don't need to include clk-private.h. Replace the include with clk.h because these modules are clock consumers and also include clk-provider.h in clk/ti.h because struct clk_hw_omap has a struct clk_hw embedded in it. Cc: Tero Kristo <t-kristo@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-22 15:40:20 -08:00
#include <linux/clk.h>
CLK: TI: add omap5 clock init file clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 17:15:51 +03:00
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/clk/ti.h>
clk: ti: omap5: add clkctrl clock data Add data for omap5 clkctrl clocks, and register it within the clkctrl driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2017-07-31 12:16:24 +03:00
#include <dt-bindings/clock/omap5.h>
CLK: TI: add omap5 clock init file clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 17:15:51 +03:00
clk: ti: move some public definitions to private header Several exported TI clock driver features are no longer needed outside the clock driver itself, thus move all of these to the driver private header file. Also, update some of the driver files to actually include this header. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2015-03-04 21:02:05 +02:00
#include "clock.h"
CLK: TI: add omap5 clock init file clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 17:15:51 +03:00
#define OMAP5_DPLL_ABE_DEFFREQ 98304000
CLK: TI: omap5: Initialize USB_DPLL at boot USB_DPLL must be initialized and locked at boot so that USB modules can work. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-24 16:30:55 +03:00
/*
* OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
* states it must be at 960MHz
*/
#define OMAP5_DPLL_USB_DEFFREQ 960000000
clk: ti: omap5: add clkctrl clock data Add data for omap5 clkctrl clocks, and register it within the clkctrl driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2017-07-31 12:16:24 +03:00
static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
{ OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
{ OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" },
{ 0 },
};
static const char * const omap5_dmic_gfclk_parents[] __initconst = {
"abe_cm:clk:0018:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
"abe_24m_fclk",
"dss_syc_gfclk_div",
"func_24m_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
"abe_cm:clk:0028:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
"abe_cm:clk:0030:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
"abe_cm:clk:0038:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
"dss_syc_gfclk_div",
"sys_32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
{ OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
{ OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
{ OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
{ OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
{ OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
{ OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
{ OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
{ OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
{ OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
{ OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ 0 },
};
static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
"sys_clkin",
"sys_32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
"sys_32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
{ OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
{ OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ 0 },
};
static const char * const omap5_dss_dss_clk_parents[] __initconst = {
"dpll_per_h12x2_ck",
NULL,
};
static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
"func_48m_fclk",
NULL,
};
static const char * const omap5_dss_sys_clk_parents[] __initconst = {
"dss_syc_gfclk_div",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
{ 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
{ 0 },
};
static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
"func_128m_clk",
"dpll_per_m2x2_ck",
NULL,
};
static const char * const omap5_mmc1_fclk_parents[] __initconst = {
"l3init_cm:clk:0008:24",
NULL,
};
static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
.max_div = 2,
};
static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
{ 0 },
};
static const char * const omap5_mmc2_fclk_parents[] __initconst = {
"l3init_cm:clk:0010:24",
NULL,
};
static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
.max_div = 2,
};
static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
{ 0 },
};
static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
"l3init_60m_fclk",
NULL,
};
static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
"dpll_usb_m2_ck",
NULL,
};
static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
"l3init_cm:clk:0038:24",
NULL,
};
static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
"l3init_cm:clk:0038:25",
NULL,
};
static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
"l3init_60m_fclk",
"xclk60mhsp1_ck",
NULL,
};
static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
"l3init_60m_fclk",
"xclk60mhsp2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
{ 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
{ 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
{ 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
{ 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 0 },
};
static const char * const omap5_sata_ref_clk_parents[] __initconst = {
"sys_clkin",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
{ 0 },
};
static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
"dpll_usb_clkdcoldo",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
{ OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
{ OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
{ OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
{ OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
{ 0x4a004320, omap5_mpu_clkctrl_regs },
{ 0x4a004420, omap5_dsp_clkctrl_regs },
{ 0x4a004520, omap5_abe_clkctrl_regs },
{ 0x4a008720, omap5_l3main1_clkctrl_regs },
{ 0x4a008820, omap5_l3main2_clkctrl_regs },
{ 0x4a008920, omap5_ipu_clkctrl_regs },
{ 0x4a008a20, omap5_dma_clkctrl_regs },
{ 0x4a008b20, omap5_emif_clkctrl_regs },
{ 0x4a008d20, omap5_l4cfg_clkctrl_regs },
{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
{ 0x4a009020, omap5_l4per_clkctrl_regs },
{ 0x4a009420, omap5_dss_clkctrl_regs },
{ 0x4a009620, omap5_l3init_clkctrl_regs },
{ 0x4ae07920, omap5_wkupaon_clkctrl_regs },
{ 0 },
};
CLK: TI: add omap5 clock init file clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 17:15:51 +03:00
static struct ti_dt_clk omap54xx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
clk: ti: dra7: fix kernel boot with arg 'clocksource=gp_timer' The OMAP Platform code provides possibility to select GP Timer as default clocksource instead of counter_32K by using bootcmd parameter 'clocksource', but the system will crash during early boot when this option is used on dra7 or omap5 platforms, because it will hit BUG() statement: omap2_gptimer_clocksource_init ->BUG_ON(res); This happens because clk_dev alias "sys_clkin_ck" is not registered. Hence, fix it by adding missing "sys_clkin_ck" clk_dev aliases definitions for omap5 and dra7. Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-10 19:03:45 +02:00
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
clk: ti: omap5: add clkctrl clock data Add data for omap5 clkctrl clocks, and register it within the clkctrl driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2017-07-31 12:16:24 +03:00
DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
CLK: TI: add omap5 clock init file clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 17:15:51 +03:00
{ .node_name = NULL },
};
int __init omap5xxx_dt_clk_init(void)
{
int rc;
CLK: TI: omap5: Initialize USB_DPLL at boot USB_DPLL must be initialized and locked at boot so that USB modules can work. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-24 16:30:55 +03:00
struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
CLK: TI: add omap5 clock init file clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 17:15:51 +03:00
ti_dt_clocks_register(omap54xx_clks);
omap2_clk_disable_autoidle_all();
clk: ti: omap5: cleanup unnecessary clock aliases Most of the clock aliases are no longer needed, only leave the ones required by OMAP timer code in place. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2017-08-21 11:05:46 +03:00
ti_clk_add_aliases();
CLK: TI: add omap5 clock init file clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 17:15:51 +03:00
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck In order to get correct clock dividers for AESS/ABE we need to set the dpll_abe_m2x2_ck rate to be double of dpll_abe_ck. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-04-30 14:39:37 +03:00
abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
if (rc)
pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
CLK: TI: omap5: Initialize USB_DPLL at boot USB_DPLL must be initialized and locked at boot so that USB modules can work. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-24 16:30:55 +03:00
usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
if (rc)
pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
CLK: TI: add omap5 clock init file clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 17:15:51 +03:00
return 0;
}
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