2007-10-09 12:37:13 -05:00
/ *
* Enter a n d l e a v e d e e p s l e e p s t a t e o n M P C 8 3 x x
*
* Copyright ( c ) 2 0 0 6 - 2 0 0 8 F r e e s c a l e S e m i c o n d u c t o r , I n c .
* Author : Scott W o o d < s c o t t w o o d @freescale.com>
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify it
* under t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e v e r s i o n 2 a s p u b l i s h e d
* by t h e F r e e S o f t w a r e F o u n d a t i o n .
* /
# include < a s m / p a g e . h >
# include < a s m / p p c _ a s m . h >
# include < a s m / r e g . h >
# include < a s m / a s m - o f f s e t s . h >
# define S S _ M E M S A V E 0 x00 / * F i r s t 8 b y t e s o f R A M * /
# define S S _ H I D 0 x08 / * 3 H I D s * /
# define S S _ I A B R 0 x14 / * 2 I A B R s * /
# define S S _ I B C R 0 x1 c
# define S S _ D A B R 0 x20 / * 2 D A B R s * /
# define S S _ D B C R 0 x28
# define S S _ S P 0 x2 c
# define S S _ S R 0 x30 / * 1 6 s e g m e n t r e g i s t e r s * /
# define S S _ R 2 0 x70
# define S S _ M S R 0 x74
# define S S _ S D R 1 0 x78
# define S S _ L R 0 x7 c
# define S S _ S P R G 0 x80 / * 4 S P R G s * /
# define S S _ D B A T 0 x90 / * 8 D B A T s * /
# define S S _ I B A T 0 x d0 / * 8 I B A T s * /
# define S S _ T B 0 x11 0
# define S S _ C R 0 x11 8
# define S S _ G P R E G 0 x11 c / * r12 - r31 * /
# define S T A T E _ S A V E _ S I Z E 0 x16 c
.section .data
.align 5
mpc83xx_sleep_save_area :
.space STATE_SAVE_SIZE
immrbase :
.long 0
.section .text
.align 5
/* r3 = physical address of IMMR */
_ GLOBAL( m p c83 x x _ e n t e r _ d e e p _ s l e e p )
lis r4 , i m m r b a s e @ha
stw r3 , i m m r b a s e @l(r4)
/ * The f i r s t 2 w o r d s o f m e m o r y a r e u s e d t o c o m m u n i c a t e w i t h t h e
* bootloader, t o t e l l i t h o w t o r e s u m e .
*
* The f i r s t w o r d i s t h e m a g i c n u m b e r 0 x f51 5 3 a e 5 , a n d t h e s e c o n d
* is t h e p o i n t e r t o m p c83 x x _ d e e p _ r e s u m e .
*
* The o r i g i n a l c o n t e n t o f t h e s e t w o w o r d s i s s a v e d i n S S _ M E M S A V E .
* /
lis r3 , m p c83 x x _ s l e e p _ s a v e _ a r e a @h
ori r3 , r3 , m p c83 x x _ s l e e p _ s a v e _ a r e a @l
lis r4 , K E R N E L B A S E @h
lwz r5 , 0 ( r4 )
lwz r6 , 4 ( r4 )
stw r5 , S S _ M E M S A V E + 0 ( r3 )
stw r6 , S S _ M E M S A V E + 4 ( r3 )
mfspr r5 , S P R N _ H I D 0
mfspr r6 , S P R N _ H I D 1
mfspr r7 , S P R N _ H I D 2
stw r5 , S S _ H I D + 0 ( r3 )
stw r6 , S S _ H I D + 4 ( r3 )
stw r7 , S S _ H I D + 8 ( r3 )
mfspr r4 , S P R N _ I A B R
mfspr r5 , S P R N _ I A B R 2
mfspr r6 , S P R N _ I B C R
mfspr r7 , S P R N _ D A B R
mfspr r8 , S P R N _ D A B R 2
mfspr r9 , S P R N _ D B C R
stw r4 , S S _ I A B R + 0 ( r3 )
stw r5 , S S _ I A B R + 4 ( r3 )
stw r6 , S S _ I B C R ( r3 )
stw r7 , S S _ D A B R + 0 ( r3 )
stw r8 , S S _ D A B R + 4 ( r3 )
stw r9 , S S _ D B C R ( r3 )
mfspr r4 , S P R N _ S P R G 0
mfspr r5 , S P R N _ S P R G 1
mfspr r6 , S P R N _ S P R G 2
mfspr r7 , S P R N _ S P R G 3
mfsdr1 r8
stw r4 , S S _ S P R G + 0 ( r3 )
stw r5 , S S _ S P R G + 4 ( r3 )
stw r6 , S S _ S P R G + 8 ( r3 )
stw r7 , S S _ S P R G + 1 2 ( r3 )
stw r8 , S S _ S D R 1 ( r3 )
mfspr r4 , S P R N _ D B A T 0 U
mfspr r5 , S P R N _ D B A T 0 L
mfspr r6 , S P R N _ D B A T 1 U
mfspr r7 , S P R N _ D B A T 1 L
stw r4 , S S _ D B A T + 0 x00 ( r3 )
stw r5 , S S _ D B A T + 0 x04 ( r3 )
stw r6 , S S _ D B A T + 0 x08 ( r3 )
stw r7 , S S _ D B A T + 0 x0 c ( r3 )
mfspr r4 , S P R N _ D B A T 2 U
mfspr r5 , S P R N _ D B A T 2 L
mfspr r6 , S P R N _ D B A T 3 U
mfspr r7 , S P R N _ D B A T 3 L
stw r4 , S S _ D B A T + 0 x10 ( r3 )
stw r5 , S S _ D B A T + 0 x14 ( r3 )
stw r6 , S S _ D B A T + 0 x18 ( r3 )
stw r7 , S S _ D B A T + 0 x1 c ( r3 )
mfspr r4 , S P R N _ D B A T 4 U
mfspr r5 , S P R N _ D B A T 4 L
mfspr r6 , S P R N _ D B A T 5 U
mfspr r7 , S P R N _ D B A T 5 L
stw r4 , S S _ D B A T + 0 x20 ( r3 )
stw r5 , S S _ D B A T + 0 x24 ( r3 )
stw r6 , S S _ D B A T + 0 x28 ( r3 )
stw r7 , S S _ D B A T + 0 x2 c ( r3 )
mfspr r4 , S P R N _ D B A T 6 U
mfspr r5 , S P R N _ D B A T 6 L
mfspr r6 , S P R N _ D B A T 7 U
mfspr r7 , S P R N _ D B A T 7 L
stw r4 , S S _ D B A T + 0 x30 ( r3 )
stw r5 , S S _ D B A T + 0 x34 ( r3 )
stw r6 , S S _ D B A T + 0 x38 ( r3 )
stw r7 , S S _ D B A T + 0 x3 c ( r3 )
mfspr r4 , S P R N _ I B A T 0 U
mfspr r5 , S P R N _ I B A T 0 L
mfspr r6 , S P R N _ I B A T 1 U
mfspr r7 , S P R N _ I B A T 1 L
stw r4 , S S _ I B A T + 0 x00 ( r3 )
stw r5 , S S _ I B A T + 0 x04 ( r3 )
stw r6 , S S _ I B A T + 0 x08 ( r3 )
stw r7 , S S _ I B A T + 0 x0 c ( r3 )
mfspr r4 , S P R N _ I B A T 2 U
mfspr r5 , S P R N _ I B A T 2 L
mfspr r6 , S P R N _ I B A T 3 U
mfspr r7 , S P R N _ I B A T 3 L
stw r4 , S S _ I B A T + 0 x10 ( r3 )
stw r5 , S S _ I B A T + 0 x14 ( r3 )
stw r6 , S S _ I B A T + 0 x18 ( r3 )
stw r7 , S S _ I B A T + 0 x1 c ( r3 )
mfspr r4 , S P R N _ I B A T 4 U
mfspr r5 , S P R N _ I B A T 4 L
mfspr r6 , S P R N _ I B A T 5 U
mfspr r7 , S P R N _ I B A T 5 L
stw r4 , S S _ I B A T + 0 x20 ( r3 )
stw r5 , S S _ I B A T + 0 x24 ( r3 )
stw r6 , S S _ I B A T + 0 x28 ( r3 )
stw r7 , S S _ I B A T + 0 x2 c ( r3 )
mfspr r4 , S P R N _ I B A T 6 U
mfspr r5 , S P R N _ I B A T 6 L
mfspr r6 , S P R N _ I B A T 7 U
mfspr r7 , S P R N _ I B A T 7 L
stw r4 , S S _ I B A T + 0 x30 ( r3 )
stw r5 , S S _ I B A T + 0 x34 ( r3 )
stw r6 , S S _ I B A T + 0 x38 ( r3 )
stw r7 , S S _ I B A T + 0 x3 c ( r3 )
mfmsr r4
mflr r5
mfcr r6
stw r4 , S S _ M S R ( r3 )
stw r5 , S S _ L R ( r3 )
stw r6 , S S _ C R ( r3 )
stw r1 , S S _ S P ( r3 )
stw r2 , S S _ R 2 ( r3 )
1 : mftbu r4
mftb r5
mftbu r6
cmpw r4 , r6
bne 1 b
stw r4 , S S _ T B + 0 ( r3 )
stw r5 , S S _ T B + 4 ( r3 )
stmw r12 , S S _ G P R E G ( r3 )
li r4 , 0
addi r6 , r3 , S S _ S R - 4
1 : mfsrin r5 , r4
stwu r5 , 4 ( r6 )
addis r4 , r4 , 0 x10 0 0
cmpwi r4 , 0
bne 1 b
/* Disable machine checks and critical exceptions */
mfmsr r4
rlwinm r4 , r4 , 0 , ~ M S R _ C E
rlwinm r4 , r4 , 0 , ~ M S R _ M E
mtmsr r4
isync
# define T M P _ V I R T _ I M M R 0 x f00 0 0 0 0 0
# define D E F A U L T _ I M M R _ V A L U E 0 x f f40 0 0 0 0
# define I M M R B A R _ B A S E 0 x00 0 0
lis r4 , i m m r b a s e @ha
lwz r4 , i m m r b a s e @l(r4)
/* Use DBAT0 to address the current IMMR space */
ori r4 , r4 , 0 x00 2 a
mtspr S P R N _ D B A T 0 L , r4
lis r8 , T M P _ V I R T _ I M M R @h
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01 15:38:34 -04:00
ori r4 , r8 , 0 x00 1 e / * 1 M B y t e a c c e s s i b l e f r o m K e r n e l S p a c e o n l y * /
2007-10-09 12:37:13 -05:00
mtspr S P R N _ D B A T 0 U , r4
isync
/* Use DBAT1 to address the original IMMR space */
lis r4 , D E F A U L T _ I M M R _ V A L U E @h
ori r4 , r4 , 0 x00 2 a
mtspr S P R N _ D B A T 1 L , r4
lis r9 , ( T M P _ V I R T _ I M M R + 0 x01 0 0 0 0 0 0 ) @h
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01 15:38:34 -04:00
ori r4 , r9 , 0 x00 1 e / * 1 M B y t e a c c e s s i b l e f r o m K e r n e l S p a c e o n l y * /
2007-10-09 12:37:13 -05:00
mtspr S P R N _ D B A T 1 U , r4
isync
/ * Use D B A T 2 t o a d d r e s s t h e b e g i n n i n g o f R A M . T h i s i s n ' t d o n e
* using t h e n o r m a l v i r t u a l m a p p i n g , b e c a u s e w i t h p a g e d e b u g g i n g
* enabled i t w i l l b e r e a d - o n l y .
* /
li r4 , 0 x00 0 2
mtspr S P R N _ D B A T 2 L , r4
lis r4 , K E R N E L B A S E @h
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01 15:38:34 -04:00
ori r4 , r4 , 0 x00 1 e / * 1 M B y t e a c c e s s i b l e f r o m K e r n e l S p a c e o n l y * /
2007-10-09 12:37:13 -05:00
mtspr S P R N _ D B A T 2 U , r4
isync
/ * Flush t h e c a c h e w i t h o u r B A T , a s t h e r e w i l l b e T L B m i s s e s
* otherwise i f p a g e d e b u g g i n g i s e n a b l e d , a n d t h e s e m i s s e s
* will d i s t u r b t h e P L R U a l g o r i t h m .
* /
bl _ _ f l u s h _ d i s a b l e _ L 1
/ * Keep t h e i - c a c h e e n a b l e d , s o t h e h a c k b e l o w f o r l o w - b o o t
* flash w i l l w o r k .
* /
mfspr r3 , S P R N _ H I D 0
ori r3 , r3 , H I D 0 _ I C E
mtspr S P R N _ H I D 0 , r3
isync
lis r6 , 0 x f51 5
ori r6 , r6 , 0 x3 a e 5
lis r7 , m p c83 x x _ d e e p _ r e s u m e @h
ori r7 , r7 , m p c83 x x _ d e e p _ r e s u m e @l
tophys( r7 , r7 )
lis r5 , K E R N E L B A S E @h
stw r6 , 0 ( r5 )
stw r7 , 4 ( r5 )
/* Reset BARs */
li r4 , 0
stw r4 , 0 x00 2 4 ( r8 )
stw r4 , 0 x00 2 c ( r8 )
stw r4 , 0 x00 3 4 ( r8 )
stw r4 , 0 x00 3 c ( r8 )
stw r4 , 0 x00 6 4 ( r8 )
stw r4 , 0 x00 6 c ( r8 )
/ * Rev 1 o f t h e 8 3 1 3 h a s p r o b l e m s w i t h w a k e u p e v e n t s t h a t a r e
* pending d u r i n g t h e t r a n s i t i o n t o d e e p s l e e p s t a t e ( s u c h a s i f
* the P C I h o s t s e t s t h e s t a t e t o D 3 a n d t h e n D 0 i n r a p i d
* succession) . T h i s c h e c k s h r i n k s t h e r a c e w i n d o w s o m e w h a t .
*
* See e r r a t u m P C I 2 3 , t h o u g h t h e p r o b l e m i s n o t l i m i t e d
* to P C I .
* /
lwz r3 , 0 x0 b04 ( r8 )
andi. r3 , r3 , 1
bne- m p c83 x x _ d e e p _ r e s u m e
/ * Move I M M R b a c k t o t h e d e f a u l t l o c a t i o n , f o l l o w i n g t h e
* procedure s p e c i f i e d i n t h e M P C 8 3 1 3 m a n u a l .
* /
lwz r4 , I M M R B A R _ B A S E ( r8 )
isync
lis r4 , D E F A U L T _ I M M R _ V A L U E @h
stw r4 , I M M R B A R _ B A S E ( r8 )
lis r4 , K E R N E L B A S E @h
lwz r4 , 0 ( r4 )
isync
lwz r4 , I M M R B A R _ B A S E ( r9 )
mr r8 , r9
isync
/ * Check t h e R e s e t C o n f i g u r a t i o n W o r d t o s e e w h e t h e r f l a s h n e e d s
* to b e m a p p e d a t a l o w a d d r e s s o r a h i g h a d d r e s s .
* /
lwz r4 , 0 x09 0 4 ( r8 )
andis. r4 , r4 , 0 x04 0 0
li r4 , 0
beq b o o t _ l o w
lis r4 , 0 x f f80
boot_low :
stw r4 , 0 x00 2 0 ( r8 )
lis r7 , 0 x80 0 0
ori r7 , r7 , 0 x00 1 6
mfspr r5 , S P R N _ H I D 0
rlwinm r5 , r5 , 0 , ~ ( H I D 0 _ D O Z E | H I D 0 _ N A P )
oris r5 , r5 , H I D 0 _ S L E E P @h
mtspr S P R N _ H I D 0 , r5
isync
mfmsr r5
oris r5 , r5 , M S R _ P O W @h
/ * Enable t h e f l a s h m a p p i n g a t t h e a p p r o p r i a t e a d d r e s s . T h i s
* mapping w i l l o v e r r i d e t h e R A M m a p p i n g i f b o o t i n g l o w , s o t h e r e ' s
* no n e e d t o d i s a b l e t h e l a t t e r . T h i s m u s t b e d o n e i n s i d e t h e s a m e
* cache l i n e a s s e t t i n g M S R _ P O W , s o t h a t n o i n s t r u c t i o n f e t c h e s
* from R A M h a p p e n a f t e r t h e f l a s h m a p p i n g i s t u r n e d o n .
* /
.align 5
stw r7 , 0 x00 2 4 ( r8 )
sync
isync
mtmsr r5
isync
1 : b 1 b
mpc83xx_deep_resume :
lis r4 , 1 f @h
ori r4 , r4 , 1 f @l
tophys( r4 , r4 )
mtsrr0 r4
mfmsr r4
rlwinm r4 , r4 , 0 , ~ ( M S R _ I R | M S R _ D R )
mtsrr1 r4
rfi
1 : tlbia
bl _ _ i n v a l _ e n a b l e _ L 1
lis r3 , m p c83 x x _ s l e e p _ s a v e _ a r e a @h
ori r3 , r3 , m p c83 x x _ s l e e p _ s a v e _ a r e a @l
tophys( r3 , r3 )
lwz r5 , S S _ M E M S A V E + 0 ( r3 )
lwz r6 , S S _ M E M S A V E + 4 ( r3 )
stw r5 , 0 ( 0 )
stw r6 , 4 ( 0 )
lwz r5 , S S _ H I D + 0 ( r3 )
lwz r6 , S S _ H I D + 4 ( r3 )
lwz r7 , S S _ H I D + 8 ( r3 )
mtspr S P R N _ H I D 0 , r5
mtspr S P R N _ H I D 1 , r6
mtspr S P R N _ H I D 2 , r7
lwz r4 , S S _ I A B R + 0 ( r3 )
lwz r5 , S S _ I A B R + 4 ( r3 )
lwz r6 , S S _ I B C R ( r3 )
lwz r7 , S S _ D A B R + 0 ( r3 )
lwz r8 , S S _ D A B R + 4 ( r3 )
lwz r9 , S S _ D B C R ( r3 )
mtspr S P R N _ I A B R , r4
mtspr S P R N _ I A B R 2 , r5
mtspr S P R N _ I B C R , r6
mtspr S P R N _ D A B R , r7
mtspr S P R N _ D A B R 2 , r8
mtspr S P R N _ D B C R , r9
li r4 , 0
addi r6 , r3 , S S _ S R - 4
1 : lwzu r5 , 4 ( r6 )
mtsrin r5 , r4
addis r4 , r4 , 0 x10 0 0
cmpwi r4 , 0
bne 1 b
lwz r4 , S S _ D B A T + 0 x00 ( r3 )
lwz r5 , S S _ D B A T + 0 x04 ( r3 )
lwz r6 , S S _ D B A T + 0 x08 ( r3 )
lwz r7 , S S _ D B A T + 0 x0 c ( r3 )
mtspr S P R N _ D B A T 0 U , r4
mtspr S P R N _ D B A T 0 L , r5
mtspr S P R N _ D B A T 1 U , r6
mtspr S P R N _ D B A T 1 L , r7
lwz r4 , S S _ D B A T + 0 x10 ( r3 )
lwz r5 , S S _ D B A T + 0 x14 ( r3 )
lwz r6 , S S _ D B A T + 0 x18 ( r3 )
lwz r7 , S S _ D B A T + 0 x1 c ( r3 )
mtspr S P R N _ D B A T 2 U , r4
mtspr S P R N _ D B A T 2 L , r5
mtspr S P R N _ D B A T 3 U , r6
mtspr S P R N _ D B A T 3 L , r7
lwz r4 , S S _ D B A T + 0 x20 ( r3 )
lwz r5 , S S _ D B A T + 0 x24 ( r3 )
lwz r6 , S S _ D B A T + 0 x28 ( r3 )
lwz r7 , S S _ D B A T + 0 x2 c ( r3 )
mtspr S P R N _ D B A T 4 U , r4
mtspr S P R N _ D B A T 4 L , r5
mtspr S P R N _ D B A T 5 U , r6
mtspr S P R N _ D B A T 5 L , r7
lwz r4 , S S _ D B A T + 0 x30 ( r3 )
lwz r5 , S S _ D B A T + 0 x34 ( r3 )
lwz r6 , S S _ D B A T + 0 x38 ( r3 )
lwz r7 , S S _ D B A T + 0 x3 c ( r3 )
mtspr S P R N _ D B A T 6 U , r4
mtspr S P R N _ D B A T 6 L , r5
mtspr S P R N _ D B A T 7 U , r6
mtspr S P R N _ D B A T 7 L , r7
lwz r4 , S S _ I B A T + 0 x00 ( r3 )
lwz r5 , S S _ I B A T + 0 x04 ( r3 )
lwz r6 , S S _ I B A T + 0 x08 ( r3 )
lwz r7 , S S _ I B A T + 0 x0 c ( r3 )
mtspr S P R N _ I B A T 0 U , r4
mtspr S P R N _ I B A T 0 L , r5
mtspr S P R N _ I B A T 1 U , r6
mtspr S P R N _ I B A T 1 L , r7
lwz r4 , S S _ I B A T + 0 x10 ( r3 )
lwz r5 , S S _ I B A T + 0 x14 ( r3 )
lwz r6 , S S _ I B A T + 0 x18 ( r3 )
lwz r7 , S S _ I B A T + 0 x1 c ( r3 )
mtspr S P R N _ I B A T 2 U , r4
mtspr S P R N _ I B A T 2 L , r5
mtspr S P R N _ I B A T 3 U , r6
mtspr S P R N _ I B A T 3 L , r7
lwz r4 , S S _ I B A T + 0 x20 ( r3 )
lwz r5 , S S _ I B A T + 0 x24 ( r3 )
lwz r6 , S S _ I B A T + 0 x28 ( r3 )
lwz r7 , S S _ I B A T + 0 x2 c ( r3 )
mtspr S P R N _ I B A T 4 U , r4
mtspr S P R N _ I B A T 4 L , r5
mtspr S P R N _ I B A T 5 U , r6
mtspr S P R N _ I B A T 5 L , r7
lwz r4 , S S _ I B A T + 0 x30 ( r3 )
lwz r5 , S S _ I B A T + 0 x34 ( r3 )
lwz r6 , S S _ I B A T + 0 x38 ( r3 )
lwz r7 , S S _ I B A T + 0 x3 c ( r3 )
mtspr S P R N _ I B A T 6 U , r4
mtspr S P R N _ I B A T 6 L , r5
mtspr S P R N _ I B A T 7 U , r6
mtspr S P R N _ I B A T 7 L , r7
lwz r4 , S S _ S P R G + 0 ( r3 )
lwz r5 , S S _ S P R G + 4 ( r3 )
lwz r6 , S S _ S P R G + 8 ( r3 )
lwz r7 , S S _ S P R G + 1 2 ( r3 )
lwz r8 , S S _ S D R 1 ( r3 )
mtspr S P R N _ S P R G 0 , r4
mtspr S P R N _ S P R G 1 , r5
mtspr S P R N _ S P R G 2 , r6
mtspr S P R N _ S P R G 3 , r7
mtsdr1 r8
lwz r4 , S S _ M S R ( r3 )
lwz r5 , S S _ L R ( r3 )
lwz r6 , S S _ C R ( r3 )
lwz r1 , S S _ S P ( r3 )
lwz r2 , S S _ R 2 ( r3 )
mtsrr1 r4
mtsrr0 r5
mtcr r6
li r4 , 0
mtspr S P R N _ T B W L , r4
lwz r4 , S S _ T B + 0 ( r3 )
lwz r5 , S S _ T B + 4 ( r3 )
mtspr S P R N _ T B W U , r4
mtspr S P R N _ T B W L , r5
lmw r12 , S S _ G P R E G ( r3 )
/* Kick decrementer */
li r0 , 1
mtdec r0
rfi
