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/ *
* Copyright ( C ) 2 0 0 7 L e n n e r t B u y t e n h e k < b u y t e n h @wantstofly.org>
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* Copyright 2 0 0 4 - 2 0 0 9 F r e e s c a l e S e m i c o n d u c t o r , I n c . A l l R i g h t s R e s e r v e d .
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* /
/ *
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify
* it u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e v e r s i o n 2 a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n .
* /
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# include < m a c h / h a r d w a r e . h >
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# define A V I C _ N I M A S K 0 x04
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@ this macro disables fast irq (not implemented)
.macro disable_fiq
.endm
.macro _ i r q n r _ p r e a m b l e , b a s e , t m p
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# ifndef C O N F I G _ M X C _ T Z I C
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ldr \ b a s e , =avic_base
ldr \ b a s e , [ \ b a s e ]
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# ifdef C O N F I G _ M X C _ I R Q _ P R I O R
ldr r4 , [ \ b a s e , #A V I C _ N I M A S K ]
# endif
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# elif d e f i n e d C O N F I G _ M X C _ T Z I C
ldr \ b a s e , =tzic_base
ldr \ b a s e , [ \ b a s e ]
# endif / * C O N F I G _ M X C _ T Z I C * /
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.endm
.macro _ r e t _ t o _ u s e r , t m p1 , t m p2
.endm
@ this macro checks which interrupt occured
@ and returns its number in irqnr
@ and returns if an interrupt occured in irqstat
.macro _ i r q n r _ a n d _ b a s e , i r q n r , i r q s t a t , b a s e , t m p
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# ifndef C O N F I G _ M X C _ T Z I C
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@ Load offset & priority of the highest priority
@ interrupt pending from AVIC_NIVECSR
ldr \ i r q s t a t , [ \ b a s e , #0x40 ]
@ Shift to get the decoded IRQ number, using ASR so
@ 'no interrupt pending' becomes 0xffffffff
mov \ i r q n r , \ i r q s t a t , a s r #16
@ set zero flag if IRQ + 1 == 0
adds \ t m p , \ i r q n r , #1
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# ifdef C O N F I G _ M X C _ I R Q _ P R I O R
bicne \ t m p , \ i r q s t a t , #0xFFFFFFE0
strne \ t m p , [ \ b a s e , #A V I C _ N I M A S K ]
streq r4 , [ \ b a s e , #A V I C _ N I M A S K ]
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# endif
# elif d e f i n e d C O N F I G _ M X C _ T Z I C
@ Load offset & priority of the highest priority
@ interrupt pending.
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@ 0x080 is INTSEC0 register
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@ 0xD80 is HIPND0 register
mov \ i r q n r , #0
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1000 : add \ i r q s t a t , \ b a s e , \ i r q n r , l s r #3
ldr \ t m p , [ \ i r q s t a t , #0xd80 ]
ldr \ i r q s t a t , [ \ i r q s t a t , #0x080 ]
ands \ t m p , \ t m p , \ i r q s t a t
bne 1 0 0 1 f
add \ i r q n r , \ i r q n r , #32
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cmp \ i r q n r , #128
blo 1 0 0 0 b
b 2 0 0 1 f
1001 : mov \ i r q s t a t , #1
1002 : tst \ t m p , \ i r q s t a t
bne 2 0 0 2 f
movs \ t m p , \ t m p , l s r #1
addne \ i r q n r , \ i r q n r , #1
bne 1 0 0 2 b
2001 :
mov \ i r q n r , #0
2002 :
movs \ i r q n r , \ i r q n r
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# endif
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.endm
@ irq priority table (not used)
.macro irq_prio_table
.endm
