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/ *
* arch/ a r m / m a c h - t e g r a / i n c l u d e / m a c h / d e b u g - m a c r o . S
*
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* Copyright ( C ) 2 0 1 0 ,2 0 1 1 G o o g l e , I n c .
* Copyright ( C ) 2 0 1 1 - 2 0 1 2 N V I D I A C O R P O R A T I O N . A l l R i g h t s R e s e r v e d .
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*
* Author :
* Colin C r o s s < c c r o s s @google.com>
* Erik G i l l i n g < k o n k e r s @google.com>
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* Doug A n d e r s o n < d i a n d e r s @chromium.org>
* Stephen W a r r e n < s w a r r e n @nvidia.com>
*
* Portions b a s e d o n m a c h - o m a p2 ' s d e b u g - m a c r o . S
* Copyright ( C ) 1 9 9 4 - 1 9 9 9 R u s s e l l K i n g
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*
* This s o f t w a r e i s l i c e n s e d u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c
* License v e r s i o n 2 , a s p u b l i s h e d b y t h e F r e e S o f t w a r e F o u n d a t i o n , a n d
* may b e c o p i e d , d i s t r i b u t e d , a n d m o d i f i e d u n d e r t h o s e t e r m s .
*
* This p r o g r a m i s d i s t r i b u t e d i n t h e h o p e t h a t i t w i l l b e u s e f u l ,
* but W I T H O U T A N Y W A R R A N T Y ; without even the implied warranty of
* MERCHANTABILITY o r F I T N E S S F O R A P A R T I C U L A R P U R P O S E . S e e t h e
* GNU G e n e r a l P u b l i c L i c e n s e f o r m o r e d e t a i l s .
*
* /
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# include < l i n u x / s e r i a l _ r e g . h >
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# include < m a c h / i o . h >
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# include < m a c h / i o m a p . h >
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# include < m a c h / i r a m m a p . h >
.macro r p , r v , t m p
adr \ r p , 9 9 f @ actual addr of 99f
ldr \ r v , [ \ r p ] @ linked addr is stored there
sub \ r v , \ r v , \ r p @ offset between the two
ldr \ r p , [ \ r p , #4 ] @ linked tegra_uart_config
sub \ t m p , \ r p , \ r v @ actual tegra_uart_config
ldr \ r p , [ \ t m p ] @ Load tegra_uart_config
cmp \ r p , #1 @ needs intitialization?
bne 1 0 0 f @ no; go load the addresses
mov \ r v , #0 @ yes; record init is done
str \ r v , [ \ t m p ]
mov \ r p , #T E G R A _ I R A M _ B A S E @ S e e i f c o o k i e i s i n I R A M
ldr \ r v , [ \ r p , #T E G R A _ I R A M _ D E B U G _ U A R T _ O F F S E T ]
movw \ r p , #T E G R A _ I R A M _ D E B U G _ U A R T _ C O O K I E & 0xffff
movt \ r p , #T E G R A _ I R A M _ D E B U G _ U A R T _ C O O K I E > > 16
cmp \ r v , \ r p @ Cookie present?
bne 1 0 0 f @ No, use default UART
mov \ r p , #T E G R A _ I R A M _ B A S E @ L o a d U A R T a d d r e s s f r o m I R A M
ldr \ r v , [ \ r p , #T E G R A _ I R A M _ D E B U G _ U A R T _ O F F S E T + 4 ]
str \ r v , [ \ t m p , #4 ] @ Store in tegra_uart_phys
sub \ r v , \ r v , #I O _ A P B _ P H Y S @ C a l c u l a t e v i r t a d d r e s s
add \ r v , \ r v , #I O _ A P B _ V I R T
str \ r v , [ \ t m p , #8 ] @ Store in tegra_uart_virt
b 1 0 0 f
.align
99 : .word .
.word tegra_uart_config
.ltorg
100 : ldr \ r p , [ \ t m p , #4 ] @ Load tegra_uart_phys
ldr \ r v , [ \ t m p , #8 ] @ Load tegra_uart_virt
.endm
# define U A R T _ S H I F T 2
/ *
* Code b e l o w i s s w i p e d f r o m < a s m / h a r d w a r e / d e b u g - 8 2 5 0 . S > , b u t a d d a n e x t r a
* check t o m a k e s u r e t h a t w e a r e n ' t i n t h e C O N F I G _ T E G R A _ D E B U G _ U A R T _ N O N E c a s e .
* We u s e t h e f a c t t h a t a l l 5 v a l i d U A R T a d d r e s s e s a l l h a v e s o m e t h i n g i n t h e
* 2 nd- t o - l o w e s t b y t e .
* /
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.macro r d , r x
tst \ r x , #0x0000ff00
strneb \ r d , [ \ r x , #U A R T _ T X < < U A R T _ S H I F T ]
1001 :
.endm
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.macro r d , r x
tst \ r x , #0x0000ff00
beq 1 0 0 2 f
1001 : ldrb \ r d , [ \ r x , #U A R T _ L S R < < U A R T _ S H I F T ]
and \ r d , \ r d , #U A R T _ L S R _ T E M T | U A R T _ L S R _ T H R E
teq \ r d , #U A R T _ L S R _ T E M T | U A R T _ L S R _ T H R E
bne 1 0 0 1 b
1002 :
.endm
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.macro r d , r x
# ifdef F L O W _ C O N T R O L
tst \ r x , #0x0000ff00
beq 1 0 0 2 f
1001 : ldrb \ r d , [ \ r x , #U A R T _ M S R < < U A R T _ S H I F T ]
tst \ r d , #U A R T _ M S R _ C T S
beq 1 0 0 1 b
1002 :
# endif
.endm
