License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 15:07:57 +01:00
# SPDX-License-Identifier: GPL-2.0
2009-10-16 18:31:48 -05:00
menuconfig FSL_SOC_BOOKE
bool "Freescale Book-E Machine Type"
depends on PPC_85xx || PPC_BOOK3E
select FSL_SOC
2008-01-28 10:24:30 -06:00
select PPC_UDBG_16550
select MPIC
2018-11-15 20:05:32 +01:00
select HAVE_PCI
2008-01-28 10:24:30 -06:00
select FSL_PCI if PCI
2012-01-19 20:23:20 -05:00
select SERIAL_8250_EXTENDED if SERIAL_8250
2008-01-28 10:24:30 -06:00
select SERIAL_8250_SHARE_IRQ if SERIAL_8250
2015-11-20 17:13:59 +08:00
select FSL_CORENET_RCPM if PPC_E500MC
2008-01-28 10:24:30 -06:00
default y
2009-10-16 18:31:48 -05:00
if FSL_SOC_BOOKE
2005-09-26 16:04:21 +10:00
2010-10-08 08:32:11 -05:00
if PPC32
2012-01-31 12:15:20 +02:00
config FSL_85XX_CACHE_SRAM
bool
select PPC_LIB_RHEAP
help
When selected, this option enables cache-sram support
for memory allocation on P1/P2 QorIQ platforms.
cache-sram-size and cache-sram-offset kernel boot
parameters should be passed when this option is enabled.
powerpc/85xx: Add BSC9131 RDB Support
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The
BSC9131 is integrated SoC that targets Femto base station market. It
combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte
shared L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel
Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE
UP/DL Channel processing, and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix
Inversion operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit
with ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network
acceleration including IEEE 1588. v2 hardware support and
virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single
port) and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD
support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
BSC9131RDB Overview
----------------------
BSC9131 SoC
1Gbyte DDR3 (on board DDR)
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
USB-ULPI
eTSEC1: Connected to RGMII PHY
eTSEC2: Connected to RGMII PHY
DUART interface: supports one UARTs up to 115200 bps for console display
Linux runs on e500v2 core and access some DSP peripherals like AIC
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-22 10:24:15 +05:30
config BSC9131_RDB
bool "Freescale BSC9131RDB"
select DEFAULT_UIMAGE
help
This option enables support for the Freescale BSC9131RDB board.
The BSC9131 is a heterogeneous SoC containing an e500v2 powerpc and a
StarCore SC3850 DSP
Manufacturer : Freescale Semiconductor, Inc
2013-08-02 14:39:11 +08:00
config C293_PCIE
bool "Freescale C293PCIE"
select DEFAULT_UIMAGE
help
This option enables support for the C293PCIE board
2014-05-15 13:15:33 +05:30
config BSC9132_QDS
bool "Freescale BSC9132QDS"
select DEFAULT_UIMAGE
help
This option enables support for the Freescale BSC9132 QDS board.
BSC9132 is a heterogeneous SoC containing dual e500v2 powerpc cores
and dual StarCore SC3850 DSP cores.
Manufacturer : Freescale Semiconductor, Inc
2005-09-26 16:04:21 +10:00
config MPC8540_ADS
bool "Freescale MPC8540 ADS"
2006-03-27 23:44:37 -06:00
select DEFAULT_UIMAGE
2005-09-26 16:04:21 +10:00
help
2006-01-14 16:57:39 -06:00
This option enables support for the MPC 8540 ADS board
2005-09-26 16:04:21 +10:00
2006-09-21 22:31:26 +04:00
config MPC8560_ADS
bool "Freescale MPC8560 ADS"
select DEFAULT_UIMAGE
2008-01-24 18:41:25 -05:00
select CPM2
2006-09-21 22:31:26 +04:00
help
This option enables support for the MPC 8560 ADS board
2006-04-02 17:42:40 -05:00
config MPC85xx_CDS
bool "Freescale MPC85xx CDS"
select DEFAULT_UIMAGE
2007-06-06 16:26:15 -07:00
select PPC_I8259
2018-11-15 20:05:36 +01:00
select HAVE_RAPIDIO
2006-04-02 17:42:40 -05:00
help
This option enables support for the MPC85xx CDS board
2007-02-17 16:29:36 -06:00
config MPC85xx_MDS
bool "Freescale MPC85xx MDS"
2007-02-09 17:28:31 -06:00
select DEFAULT_UIMAGE
2016-07-25 21:30:09 -07:00
select PHYLIB if NETDEVICES
2018-11-15 20:05:36 +01:00
select HAVE_RAPIDIO
2009-05-15 00:37:35 -05:00
select SWIOTLB
2007-02-09 17:28:31 -06:00
help
2007-02-17 16:29:36 -06:00
This option enables support for the MPC85xx MDS board
2007-02-09 17:28:31 -06:00
2008-07-02 01:36:15 -05:00
config MPC8536_DS
bool "Freescale MPC8536 DS"
select DEFAULT_UIMAGE
2009-05-15 00:37:35 -05:00
select SWIOTLB
2008-07-02 01:36:15 -05:00
help
This option enables support for the MPC8536 DS board
2007-08-17 09:22:09 -05:00
config MPC85xx_DS
bool "Freescale MPC85xx DS"
2007-07-13 18:05:08 +08:00
select PPC_I8259
2007-03-20 11:19:10 -05:00
select DEFAULT_UIMAGE
2010-04-16 23:07:24 +04:00
select FSL_ULI1575 if PCI
2009-05-15 00:37:35 -05:00
select SWIOTLB
2007-03-20 11:19:10 -05:00
help
2007-08-17 09:22:09 -05:00
This option enables support for the MPC85xx DS (MPC8544 DS) board
2007-03-20 11:19:10 -05:00
2009-08-07 21:05:16 +05:30
config MPC85xx_RDB
bool "Freescale MPC85xx RDB"
select PPC_I8259
select DEFAULT_UIMAGE
2010-04-16 23:07:24 +04:00
select FSL_ULI1575 if PCI
2009-08-07 21:05:16 +05:30
select SWIOTLB
help
This option enables support for the MPC85xx RDB (P2020 RDB) board
2011-06-02 20:28:08 +00:00
config P1010_RDB
bool "Freescale P1010RDB"
select DEFAULT_UIMAGE
help
This option enables support for the MPC85xx RDB (P1010 RDB) board
P1010RDB contains P1010Si, which provides CPU performance up to 800
MHz and 1600 DMIPS, additional functionality and faster interfaces
(DDR3/3L, SATA II, and PCI Express).
2010-07-02 17:25:03 -05:00
config P1022_DS
bool "Freescale P1022 DS"
select DEFAULT_UIMAGE
select SWIOTLB
help
This option enables support for the Freescale P1022DS reference board.
2012-07-23 18:12:29 -05:00
config P1022_RDK
bool "Freescale / iVeia P1022 RDK"
select DEFAULT_UIMAGE
help
This option enables support for the Freescale / iVeia P1022RDK
reference board.
2014-05-05 13:23:15 -05:00
config P1023_RDB
bool "Freescale P1023 RDB"
2011-05-19 20:20:13 -05:00
select DEFAULT_UIMAGE
help
2014-05-05 13:23:15 -05:00
This option enables support for the P1023 RDB board.
2011-05-19 20:20:13 -05:00
2013-11-06 17:08:03 +08:00
config TWR_P102x
bool "Freescale TWR-P102x"
select DEFAULT_UIMAGE
help
This option enables support for the TWR-P1025 board.
powerpc/85xx: Add support for the "socrates" board (MPC8544).
Supported are Ethernet, serial console, I2C, I2C-based RTC and
temperature sensors, NOR and NAND flash, PCI, USB, CAN and Lime
display controller.
The multiplexing of FPGA interrupts onto PowerPC interrupt lines is
supported through our own fpga_pic interrupt controller driver.
For example the SJA1000 controller is level low sensitive connected to
fpga_pic line 2 and is routed to the second (of three) irq lines to
the CPU:
can@3,100 {
compatible = "philips,sja1000";
reg = <3 0x100 0x80>;
interrupts = <2 2>;
interrupts = <2 8 1>; // number, type, routing
interrupt-parent = <&fpga_pic>;
};
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-22 14:58:43 +01:00
config SOCRATES
bool "Socrates"
select DEFAULT_UIMAGE
help
This option enables support for the Socrates board.
2008-03-06 18:17:16 +03:00
config KSI8560
bool "Emerson KSI8560"
select DEFAULT_UIMAGE
help
This option enables support for the Emerson KSI8560 board
2009-06-11 14:42:58 -05:00
config XES_MPC85xx
bool "X-ES single-board computer"
select DEFAULT_UIMAGE
help
This option enables support for the various single-board
computers from Extreme Engineering Solutions (X-ES) based on
Freescale MPC85xx processors.
Manufacturer: Extreme Engineering Solutions, Inc.
URL: <http://www.xes-inc.com/>
2008-01-23 23:42:44 -06:00
config STX_GP3
bool "Silicon Turnkey Express GP3"
help
This option enables support for the Silicon Turnkey Express GP3
board.
2008-01-24 18:41:25 -05:00
select CPM2
2008-01-23 23:42:44 -06:00
select DEFAULT_UIMAGE
2008-01-24 23:53:03 -06:00
config TQM8540
bool "TQ Components TQM8540"
help
This option enables support for the TQ Components TQM8540 board.
select DEFAULT_UIMAGE
select TQM85xx
config TQM8541
bool "TQ Components TQM8541"
help
This option enables support for the TQ Components TQM8541 board.
select DEFAULT_UIMAGE
select TQM85xx
select CPM2
2008-06-06 13:50:04 +02:00
config TQM8548
bool "TQ Components TQM8548"
help
This option enables support for the TQ Components TQM8548 board.
select DEFAULT_UIMAGE
select TQM85xx
2008-01-24 23:53:03 -06:00
config TQM8555
bool "TQ Components TQM8555"
help
This option enables support for the TQ Components TQM8555 board.
select DEFAULT_UIMAGE
select TQM85xx
select CPM2
config TQM8560
bool "TQ Components TQM8560"
help
This option enables support for the TQ Components TQM8560 board.
select DEFAULT_UIMAGE
select TQM85xx
select CPM2
2008-01-24 18:41:27 -05:00
config SBC8548
bool "Wind River SBC8548"
select DEFAULT_UIMAGE
help
This option enables support for the Wind River SBC8548 board
2013-02-13 15:09:00 +01:00
config PPA8548
bool "Prodrive PPA8548"
help
This option enables support for the Prodrive PPA8548 board.
select DEFAULT_UIMAGE
2018-11-15 20:05:36 +01:00
select HAVE_RAPIDIO
2013-02-13 15:09:00 +01:00
2012-03-12 17:13:00 +00:00
config GE_IMP3A
bool "GE Intelligent Platforms IMP3A"
select DEFAULT_UIMAGE
select SWIOTLB
select MMIO_NVRAM
2016-04-19 13:21:02 +02:00
select GPIOLIB
2012-03-12 17:13:00 +00:00
select GE_FPGA
help
This option enables support for the GE Intelligent Platforms IMP3A
board.
This board is a 3U CompactPCI Single Board Computer with a Freescale
P2020 processor.
powerpc: Add support for CTS-1000 GPIO controlled system poweroff
CTS-1000 is based on P4080. GPIO 27 is used to signal the FPGA to
switch off power, and also associates IRQ 8 with front-panel button
press (which we use to call orderly_poweroff()).
The relevant device-tree looks like this:
gpio0: gpio@130000 {
compatible = "fsl,qoriq-gpio";
reg = <0x130000 0x1000>;
interrupts = <55 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
/* Allows powering off the system via GPIO signal. */
gpio-halt@27 {
compatible = "sgy,gpio-halt";
gpios = <&gpio0 27 0>;
interrupts = <8 1 0 0>;
};
};
Because the driver cannot match on sgy,gpio-halt (because the node is never
processed through of_platform), it matches on fsl,qoriq-gpio and then
checks child nodes for the matching sgy,gpio-halt. This also ensures that
the GPIO controller is detected prior to sgy_cts1000's probe callback,
since that node wont match via of_platform until the controller is
registered.
Also, because the GPIO handler for triggering system poweroff might sleep,
the IRQ uses a workqueue to call orderly_poweroff().
As a final note, this driver may be expanded for other features specific to
the CTS-1000.
Signed-off-by: Ben Collins <ben.c@servergy.com>
Cc: Jack Smith <jack.s@servergy.com>
Cc: Vihar Rai <vihar.r@servergy.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-12-17 04:19:28 +00:00
config SGY_CTS1000
tristate "Servergy CTS-1000 support"
select GPIOLIB
select OF_GPIO
2013-09-26 09:42:28 +08:00
depends on CORENET_GENERIC
powerpc: Add support for CTS-1000 GPIO controlled system poweroff
CTS-1000 is based on P4080. GPIO 27 is used to signal the FPGA to
switch off power, and also associates IRQ 8 with front-panel button
press (which we use to call orderly_poweroff()).
The relevant device-tree looks like this:
gpio0: gpio@130000 {
compatible = "fsl,qoriq-gpio";
reg = <0x130000 0x1000>;
interrupts = <55 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
/* Allows powering off the system via GPIO signal. */
gpio-halt@27 {
compatible = "sgy,gpio-halt";
gpios = <&gpio0 27 0>;
interrupts = <8 1 0 0>;
};
};
Because the driver cannot match on sgy,gpio-halt (because the node is never
processed through of_platform), it matches on fsl,qoriq-gpio and then
checks child nodes for the matching sgy,gpio-halt. This also ensures that
the GPIO controller is detected prior to sgy_cts1000's probe callback,
since that node wont match via of_platform until the controller is
registered.
Also, because the GPIO handler for triggering system poweroff might sleep,
the IRQ uses a workqueue to call orderly_poweroff().
As a final note, this driver may be expanded for other features specific to
the CTS-1000.
Signed-off-by: Ben Collins <ben.c@servergy.com>
Cc: Jack Smith <jack.s@servergy.com>
Cc: Vihar Rai <vihar.r@servergy.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-12-17 04:19:28 +00:00
help
Enable this to support functionality in Servergy's CTS-1000 systems.
2014-12-11 09:56:45 +01:00
config MVME2500
bool "Artesyn MVME2500"
select DEFAULT_UIMAGE
help
This option enables support for the Emerson/Artesyn MVME2500 board.
2010-10-08 08:32:11 -05:00
endif # PPC32
2012-07-10 19:26:48 -05:00
config PPC_QEMU_E500
bool "QEMU generic e500 platform"
select DEFAULT_UIMAGE
2016-11-15 09:24:27 +01:00
select E500
select PPC_E500MC if PPC64
2012-07-10 19:26:48 -05:00
help
This option enables support for running as a QEMU guest using
QEMU's generic e500 machine. This is not required if you're
using a QEMU machine that targets a specific board, such as
mpc8544ds.
Unlike most e500 boards that target a specific CPU, this
platform works with any e500-family CPU that QEMU supports.
Thus, you'll need to make sure CONFIG_PPC_E500MC is set or
unset based on the emulated CPU (or actual host CPU in the case
of KVM).
2013-09-26 09:42:28 +08:00
config CORENET_GENERIC
bool "Freescale CoreNet Generic"
2012-01-05 11:09:04 -06:00
select DEFAULT_UIMAGE
select E500
select PPC_E500MC
select PHYS_64BIT
select SWIOTLB
2016-04-19 13:21:02 +02:00
select GPIOLIB
2012-01-05 11:09:04 -06:00
select GPIO_MPC8XXX
2018-11-15 20:05:36 +01:00
select HAVE_RAPIDIO
2012-01-05 11:09:04 -06:00
select PPC_EPAPR_HV_PIC
help
2013-09-26 09:42:28 +08:00
This option enables support for the FSL CoreNet based boards.
For 32bit kernel, the following boards are supported:
2014-04-15 19:51:46 +02:00
P2041 RDB, P3041 DS, P4080 DS, kmcoge4, and OCA4080
2013-09-26 09:42:28 +08:00
For 64bit kernel, the following boards are supported:
2014-07-08 14:52:33 +08:00
T208x QDS/RDB, T4240 QDS/RDB and B4 QDS
2013-09-26 09:42:28 +08:00
The following boards are supported for both 32bit and 64bit kernel:
2015-04-09 16:07:44 +08:00
P5020 DS, P5040 DS, T102x QDS/RDB, T104x QDS/RDB
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endif # FSL_SOC_BOOKE
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config TQM85xx
bool