2018-05-23 15:01:47 +08:00
/ *
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify
* it u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e , v e r s i o n 2 , a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n .
*
* This p r o g r a m i s d i s t r i b u t e d i n t h e h o p e t h a t i t w i l l b e u s e f u l ,
* but W I T H O U T A N Y W A R R A N T Y ; without even the implied warranty of
* MERCHANTABILITY o r F I T N E S S F O R A P A R T I C U L A R P U R P O S E . S e e t h e
* GNU G e n e r a l P u b l i c L i c e n s e f o r m o r e d e t a i l s .
*
* Derived f r o m b o o k 3 s _ h v _ r m h a n d l e r s . S , w h i c h i s :
*
* Copyright 2 0 1 1 P a u l M a c k e r r a s , I B M C o r p . < p a u l u s @au1.ibm.com>
*
* /
# include < a s m / r e g . h >
# include < a s m / p p c _ a s m . h >
# include < a s m / a s m - o f f s e t s . h >
# include < a s m / e x p o r t . h >
# include < a s m / t m . h >
# include < a s m / c p u t a b l e . h >
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
# define V C P U _ G P R S _ T M ( r e g ) ( ( ( r e g ) * U L O N G _ S I Z E ) + V C P U _ G P R _ T M )
/ *
* Save t r a n s a c t i o n a l s t a t e a n d T M - r e l a t e d r e g i s t e r s .
2018-05-23 15:01:48 +08:00
* Called w i t h :
* - r3 p o i n t i n g t o t h e v c p u s t r u c t
* - r4 p o i n t s t o t h e M S R w i t h c u r r e n t T S b i t s :
* ( For H V K V M , i t i s V C P U _ M S R ; For PR KVM, it is host MSR).
2018-05-23 15:01:47 +08:00
* This c a n m o d i f y a l l c h e c k p o i n t e d r e g i s t e r s , b u t
2018-05-23 15:01:48 +08:00
* restores r1 , r2 b e f o r e e x i t .
2018-05-23 15:01:47 +08:00
* /
_ GLOBAL( k v m p p c _ s a v e _ t m )
mflr r0
std r0 , P P C _ L R _ S T K O F F ( r1 )
/* Turn on TM. */
mfmsr r8
li r0 , 1
rldimi r8 , r0 , M S R _ T M _ L G , 6 3 - M S R _ T M _ L G
mtmsrd r8
2018-05-23 15:01:48 +08:00
rldicl. r4 , r4 , 6 4 - M S R _ T S _ S _ L G , 6 2
2018-05-23 15:01:47 +08:00
beq 1 f / * T M n o t a c t i v e i n g u e s t . * /
2018-05-23 15:01:48 +08:00
std r1 , H S T A T E _ S C R A T C H 2 ( r13 )
std r3 , H S T A T E _ S C R A T C H 1 ( r13 )
2018-05-23 15:01:47 +08:00
# ifdef C O N F I G _ K V M _ B O O K 3 S _ H V _ P O S S I B L E
BEGIN_ F T R _ S E C T I O N
/* Emulation of the treclaim instruction needs TEXASR before treclaim */
mfspr r6 , S P R N _ T E X A S R
2018-05-23 15:01:48 +08:00
std r6 , V C P U _ O R I G _ T E X A S R ( r3 )
2018-05-23 15:01:47 +08:00
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ P 9 _ T M _ H V _ A S S I S T )
# endif
/* Clear the MSR RI since r1, r13 are all going to be foobar. */
li r5 , 0
mtmsrd r5 , 1
2018-05-23 15:01:48 +08:00
li r3 , T M _ C A U S E _ K V M _ R E S C H E D
2018-05-23 15:01:47 +08:00
/* All GPRs are volatile at this point. */
TRECLAIM( R 3 )
/* Temporarily store r13 and r9 so we have some regs to play with */
SET_ S C R A T C H 0 ( r13 )
GET_ P A C A ( r13 )
std r9 , P A C A T M S C R A T C H ( r13 )
2018-05-23 15:01:48 +08:00
ld r9 , H S T A T E _ S C R A T C H 1 ( r13 )
2018-05-23 15:01:47 +08:00
/* Get a few more GPRs free. */
std r29 , V C P U _ G P R S _ T M ( 2 9 ) ( r9 )
std r30 , V C P U _ G P R S _ T M ( 3 0 ) ( r9 )
std r31 , V C P U _ G P R S _ T M ( 3 1 ) ( r9 )
/* Save away PPR and DSCR soon so don't run with user values. */
mfspr r31 , S P R N _ P P R
HMT_ M E D I U M
mfspr r30 , S P R N _ D S C R
# ifdef C O N F I G _ K V M _ B O O K 3 S _ H V _ P O S S I B L E
ld r29 , H S T A T E _ D S C R ( r13 )
mtspr S P R N _ D S C R , r29
# endif
/* Save all but r9, r13 & r29-r31 */
reg = 0
.rept 29
.if ( reg ! = 9 ) & & ( r e g ! = 1 3 )
std r e g , V C P U _ G P R S _ T M ( r e g ) ( r9 )
.endif
reg = r e g + 1
.endr
/* ... now save r13 */
GET_ S C R A T C H 0 ( r4 )
std r4 , V C P U _ G P R S _ T M ( 1 3 ) ( r9 )
/* ... and save r9 */
ld r4 , P A C A T M S C R A T C H ( r13 )
std r4 , V C P U _ G P R S _ T M ( 9 ) ( r9 )
/* Reload stack pointer and TOC. */
2018-05-23 15:01:48 +08:00
ld r1 , H S T A T E _ S C R A T C H 2 ( r13 )
2018-05-23 15:01:47 +08:00
ld r2 , P A C A T O C ( r13 )
/* Set MSR RI now we have r1 and r13 back. */
li r5 , M S R _ R I
mtmsrd r5 , 1
/* Save away checkpinted SPRs. */
std r31 , V C P U _ P P R _ T M ( r9 )
std r30 , V C P U _ D S C R _ T M ( r9 )
mflr r5
mfcr r6
mfctr r7
mfspr r8 , S P R N _ A M R
mfspr r10 , S P R N _ T A R
mfxer r11
std r5 , V C P U _ L R _ T M ( r9 )
stw r6 , V C P U _ C R _ T M ( r9 )
std r7 , V C P U _ C T R _ T M ( r9 )
std r8 , V C P U _ A M R _ T M ( r9 )
std r10 , V C P U _ T A R _ T M ( r9 )
std r11 , V C P U _ X E R _ T M ( r9 )
/* Restore r12 as trap number. */
lwz r12 , V C P U _ T R A P ( r9 )
/* Save FP/VSX. */
addi r3 , r9 , V C P U _ F P R S _ T M
bl s t o r e _ f p _ s t a t e
addi r3 , r9 , V C P U _ V R S _ T M
bl s t o r e _ v r _ s t a t e
mfspr r6 , S P R N _ V R S A V E
stw r6 , V C P U _ V R S A V E _ T M ( r9 )
1 :
/ *
* We n e e d t o s a v e t h e s e S P R s a f t e r t h e t r e c l a i m s o t h a t t h e s o f t w a r e
* error c o d e i s r e c o r d e d c o r r e c t l y i n t h e T E X A S R . A l s o t h e u s e r m a y
* change t h e s e o u t s i d e o f a t r a n s a c t i o n , s o t h e y m u s t a l w a y s b e
* context s w i t c h e d .
* /
mfspr r7 , S P R N _ T E X A S R
std r7 , V C P U _ T E X A S R ( r9 )
11 :
mfspr r5 , S P R N _ T F H A R
mfspr r6 , S P R N _ T F I A R
std r5 , V C P U _ T F H A R ( r9 )
std r6 , V C P U _ T F I A R ( r9 )
ld r0 , P P C _ L R _ S T K O F F ( r1 )
mtlr r0
blr
/ *
* Restore t r a n s a c t i o n a l s t a t e a n d T M - r e l a t e d r e g i s t e r s .
2018-05-23 15:01:48 +08:00
* Called w i t h :
* - r3 p o i n t i n g t o t h e v c p u s t r u c t .
* - r4 i s t h e g u e s t M S R w i t h d e s i r e d T S b i t s :
* For H V K V M , i t i s V C P U _ M S R
* For P R K V M , i t i s p r o v i d e d b y c a l l e r
2018-05-23 15:01:47 +08:00
* This p o t e n t i a l l y m o d i f i e s a l l c h e c k p o i n t e d r e g i s t e r s .
2018-05-23 15:01:48 +08:00
* It r e s t o r e s r1 , r2 f r o m t h e P A C A .
2018-05-23 15:01:47 +08:00
* /
_ GLOBAL( k v m p p c _ r e s t o r e _ t m )
mflr r0
std r0 , P P C _ L R _ S T K O F F ( r1 )
/* Turn on TM/FP/VSX/VMX so we can restore them. */
mfmsr r5
li r6 , M S R _ T M > > 3 2
sldi r6 , r6 , 3 2
or r5 , r5 , r6
ori r5 , r5 , M S R _ F P
oris r5 , r5 , ( M S R _ V E C | M S R _ V S X ) @h
mtmsrd r5
/ *
* The u s e r m a y c h a n g e t h e s e o u t s i d e o f a t r a n s a c t i o n , s o t h e y m u s t
* always b e c o n t e x t s w i t c h e d .
* /
2018-05-23 15:01:48 +08:00
ld r5 , V C P U _ T F H A R ( r3 )
ld r6 , V C P U _ T F I A R ( r3 )
ld r7 , V C P U _ T E X A S R ( r3 )
2018-05-23 15:01:47 +08:00
mtspr S P R N _ T F H A R , r5
mtspr S P R N _ T F I A R , r6
mtspr S P R N _ T E X A S R , r7
2018-05-23 15:01:48 +08:00
mr r5 , r4
2018-05-23 15:01:47 +08:00
rldicl. r5 , r5 , 6 4 - M S R _ T S _ S _ L G , 6 2
beqlr / * T M n o t a c t i v e i n g u e s t * /
2018-05-23 15:01:48 +08:00
std r1 , H S T A T E _ S C R A T C H 2 ( r13 )
2018-05-23 15:01:47 +08:00
/ * Make s u r e t h e f a i l u r e s u m m a r y i s s e t , o t h e r w i s e w e ' l l p r o g r a m c h e c k
* when w e t r e c h k p t . I t ' s p o s s i b l e t h a t t h i s m i g h t h a v e b e e n n o t s e t
* on a k v m p p c _ s e t _ o n e _ r e g ( ) c a l l b u t w e s h o u l d n ' t l e t t h i s c r a s h t h e
* host.
* /
oris r7 , r7 , ( T E X A S R _ F S ) @h
mtspr S P R N _ T E X A S R , r7
/ *
* We n e e d t o l o a d u p t h e c h e c k p o i n t e d s t a t e f o r t h e g u e s t .
* We n e e d t o d o t h i s e a r l y a s i t w i l l b l o w a w a y a n y G P R s , V S R s a n d
* some S P R s .
* /
2018-05-23 15:01:48 +08:00
mr r31 , r3
2018-05-23 15:01:47 +08:00
addi r3 , r31 , V C P U _ F P R S _ T M
bl l o a d _ f p _ s t a t e
addi r3 , r31 , V C P U _ V R S _ T M
bl l o a d _ v r _ s t a t e
2018-05-23 15:01:48 +08:00
mr r3 , r31
lwz r7 , V C P U _ V R S A V E _ T M ( r3 )
2018-05-23 15:01:47 +08:00
mtspr S P R N _ V R S A V E , r7
2018-05-23 15:01:48 +08:00
ld r5 , V C P U _ L R _ T M ( r3 )
lwz r6 , V C P U _ C R _ T M ( r3 )
ld r7 , V C P U _ C T R _ T M ( r3 )
ld r8 , V C P U _ A M R _ T M ( r3 )
ld r9 , V C P U _ T A R _ T M ( r3 )
ld r10 , V C P U _ X E R _ T M ( r3 )
2018-05-23 15:01:47 +08:00
mtlr r5
mtcr r6
mtctr r7
mtspr S P R N _ A M R , r8
mtspr S P R N _ T A R , r9
mtxer r10
/ *
* Load u p P P R a n d D S C R v a l u e s b u t d o n ' t p u t t h e m i n t h e a c t u a l S P R s
* till t h e l a s t m o m e n t t o a v o i d r u n n i n g w i t h u s e r s p a c e P P R a n d D S C R f o r
* too l o n g .
* /
2018-05-23 15:01:48 +08:00
ld r29 , V C P U _ D S C R _ T M ( r3 )
ld r30 , V C P U _ P P R _ T M ( r3 )
2018-05-23 15:01:47 +08:00
std r2 , P A C A T M S C R A T C H ( r13 ) / * S a v e T O C * /
/* Clear the MSR RI since r1, r13 are all going to be foobar. */
li r5 , 0
mtmsrd r5 , 1
/* Load GPRs r0-r28 */
reg = 0
.rept 29
ld r e g , V C P U _ G P R S _ T M ( r e g ) ( r31 )
reg = r e g + 1
.endr
mtspr S P R N _ D S C R , r29
mtspr S P R N _ P P R , r30
/* Load final GPRs */
ld 2 9 , V C P U _ G P R S _ T M ( 2 9 ) ( r31 )
ld 3 0 , V C P U _ G P R S _ T M ( 3 0 ) ( r31 )
ld 3 1 , V C P U _ G P R S _ T M ( 3 1 ) ( r31 )
/* TM checkpointed state is now setup. All GPRs are now volatile. */
TRECHKPT
/* Now let's get back the state we need. */
HMT_ M E D I U M
GET_ P A C A ( r13 )
# ifdef C O N F I G _ K V M _ B O O K 3 S _ H V _ P O S S I B L E
ld r29 , H S T A T E _ D S C R ( r13 )
mtspr S P R N _ D S C R , r29
# endif
2018-05-23 15:01:48 +08:00
ld r1 , H S T A T E _ S C R A T C H 2 ( r13 )
2018-05-23 15:01:47 +08:00
ld r2 , P A C A T M S C R A T C H ( r13 )
/* Set the MSR RI since we have our registers back. */
li r5 , M S R _ R I
mtmsrd r5 , 1
ld r0 , P P C _ L R _ S T K O F F ( r1 )
mtlr r0
blr
# endif / * C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M * /
