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/*
* Copyright 2014 Advanced Micro Devices , Inc .
*
* Permission is hereby granted , free of charge , to any person obtaining a
* copy of this software and associated documentation files ( the " Software " ) ,
* to deal in the Software without restriction , including without limitation
* the rights to use , copy , modify , merge , publish , distribute , sublicense ,
* and / or sell copies of the Software , and to permit persons to whom the
* Software is furnished to do so , subject to the following conditions :
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software .
*
* THE SOFTWARE IS PROVIDED " AS IS " , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR
* IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY ,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL
* THE COPYRIGHT HOLDER ( S ) OR AUTHOR ( S ) BE LIABLE FOR ANY CLAIM , DAMAGES OR
* OTHER LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE ,
* ARISING FROM , OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE .
*
*/
# ifndef VI_H
# define VI_H
# define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
# define SDMA1_REGISTER_OFFSET 0x200 /* not a register */
# define SDMA_MAX_INSTANCE 2
/* crtc instance offsets */
# define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c)
# define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c)
# define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c)
# define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c)
# define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c)
# define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c)
# define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c)
/* dig instance offsets */
# define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00)
# define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00)
# define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00)
# define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00)
# define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00)
# define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00)
# define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00)
# define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00)
# define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00)
/* audio endpt instance offsets */
# define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8)
# define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8)
# define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8)
# define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8)
# define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8)
# define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8)
# define AUD6_REGISTER_OFFSET (0x17c4 - 0x17a8)
/* hpd instance offsets */
# define HPD0_REGISTER_OFFSET (0x1898 - 0x1898)
# define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898)
# define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898)
# define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898)
# define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
# define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
# define AMDGPU_NUM_OF_VMIDS 8
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# define PIPEID(x) ((x) << 0)
# define MEID(x) ((x) << 2)
# define VMID(x) ((x) << 4)
# define QUEUEID(x) ((x) << 8)
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# define RB_BITMAP_WIDTH_PER_SH 2
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# define MC_SEQ_MISC0__MT__MASK 0xf0000000
# define MC_SEQ_MISC0__MT__GDDR1 0x10000000
# define MC_SEQ_MISC0__MT__DDR2 0x20000000
# define MC_SEQ_MISC0__MT__GDDR3 0x30000000
# define MC_SEQ_MISC0__MT__GDDR4 0x40000000
# define MC_SEQ_MISC0__MT__GDDR5 0x50000000
# define MC_SEQ_MISC0__MT__HBM 0x60000000
# define MC_SEQ_MISC0__MT__DDR3 0xB0000000
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/*
* PM4
*/
# define PACKET_TYPE0 0
# define PACKET_TYPE1 1
# define PACKET_TYPE2 2
# define PACKET_TYPE3 3
# define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
# define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
# define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
# define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
# define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
( ( reg ) & 0xFFFF ) | \
( ( n ) & 0x3FFF ) < < 16 )
# define CP_PACKET2 0x80000000
# define PACKET2_PAD_SHIFT 0
# define PACKET2_PAD_MASK (0x3fffffff << 0)
# define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
# define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
( ( ( op ) & 0xFF ) < < 8 ) | \
( ( n ) & 0x3FFF ) < < 16 )
# define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
/* Packet 3 types */
# define PACKET3_NOP 0x10
# define PACKET3_SET_BASE 0x11
# define PACKET3_BASE_INDEX(x) ((x) << 0)
# define CE_PARTITION_BASE 3
# define PACKET3_CLEAR_STATE 0x12
# define PACKET3_INDEX_BUFFER_SIZE 0x13
# define PACKET3_DISPATCH_DIRECT 0x15
# define PACKET3_DISPATCH_INDIRECT 0x16
# define PACKET3_ATOMIC_GDS 0x1D
# define PACKET3_ATOMIC_MEM 0x1E
# define PACKET3_OCCLUSION_QUERY 0x1F
# define PACKET3_SET_PREDICATION 0x20
# define PACKET3_REG_RMW 0x21
# define PACKET3_COND_EXEC 0x22
# define PACKET3_PRED_EXEC 0x23
# define PACKET3_DRAW_INDIRECT 0x24
# define PACKET3_DRAW_INDEX_INDIRECT 0x25
# define PACKET3_INDEX_BASE 0x26
# define PACKET3_DRAW_INDEX_2 0x27
# define PACKET3_CONTEXT_CONTROL 0x28
# define PACKET3_INDEX_TYPE 0x2A
# define PACKET3_DRAW_INDIRECT_MULTI 0x2C
# define PACKET3_DRAW_INDEX_AUTO 0x2D
# define PACKET3_NUM_INSTANCES 0x2F
# define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
# define PACKET3_INDIRECT_BUFFER_CONST 0x33
# define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
# define PACKET3_DRAW_INDEX_OFFSET_2 0x35
# define PACKET3_DRAW_PREAMBLE 0x36
# define PACKET3_WRITE_DATA 0x37
# define WRITE_DATA_DST_SEL(x) ((x) << 8)
/* 0 - register
* 1 - memory ( sync - via GRBM )
* 2 - gl2
* 3 - gds
* 4 - reserved
* 5 - memory ( async - direct )
*/
# define WR_ONE_ADDR (1 << 16)
# define WR_CONFIRM (1 << 20)
# define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
/* 0 - LRU
* 1 - Stream
*/
# define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
/* 0 - me
* 1 - pfp
* 2 - ce
*/
# define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
# define PACKET3_MEM_SEMAPHORE 0x39
# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
# define PACKET3_WAIT_REG_MEM 0x3C
# define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
/* 0 - always
* 1 - <
* 2 - < =
* 3 - = =
* 4 - ! =
* 5 - > =
* 6 - >
*/
# define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
/* 0 - reg
* 1 - mem
*/
# define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
/* 0 - wait_reg_mem
* 1 - wr_wait_wr_reg
*/
# define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
/* 0 - me
* 1 - pfp
*/
# define PACKET3_INDIRECT_BUFFER 0x3F
# define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
# define INDIRECT_BUFFER_VALID (1 << 23)
# define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
/* 0 - LRU
* 1 - Stream
* 2 - Bypass
*/
# define PACKET3_COPY_DATA 0x40
# define PACKET3_PFP_SYNC_ME 0x42
# define PACKET3_SURFACE_SYNC 0x43
# define PACKET3_DEST_BASE_0_ENA (1 << 0)
# define PACKET3_DEST_BASE_1_ENA (1 << 1)
# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
# define PACKET3_DEST_BASE_2_ENA (1 << 19)
# define PACKET3_DEST_BASE_3_ENA (1 << 21)
# define PACKET3_TCL1_ACTION_ENA (1 << 22)
# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
# define PACKET3_CB_ACTION_ENA (1 << 25)
# define PACKET3_DB_ACTION_ENA (1 << 26)
# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
# define PACKET3_COND_WRITE 0x45
# define PACKET3_EVENT_WRITE 0x46
# define EVENT_TYPE(x) ((x) << 0)
# define EVENT_INDEX(x) ((x) << 8)
/* 0 - any non-TS event
* 1 - ZPASS_DONE , PIXEL_PIPE_STAT_ *
* 2 - SAMPLE_PIPELINESTAT
* 3 - SAMPLE_STREAMOUTSTAT *
* 4 - * S_PARTIAL_FLUSH
* 5 - EOP events
* 6 - EOS events
*/
# define PACKET3_EVENT_WRITE_EOP 0x47
# define EOP_TCL1_VOL_ACTION_EN (1 << 12)
# define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
# define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
# define EOP_TCL1_ACTION_EN (1 << 16)
# define EOP_TC_ACTION_EN (1 << 17) /* L2 */
# define EOP_TCL2_VOLATILE (1 << 24)
# define EOP_CACHE_POLICY(x) ((x) << 25)
/* 0 - LRU
* 1 - Stream
* 2 - Bypass
*/
# define DATA_SEL(x) ((x) << 29)
/* 0 - discard
* 1 - send low 32 bit data
* 2 - send 64 bit data
* 3 - send 64 bit GPU counter value
* 4 - send 64 bit sys counter value
*/
# define INT_SEL(x) ((x) << 24)
/* 0 - none
* 1 - interrupt only ( DATA_SEL = 0 )
* 2 - interrupt when data write is confirmed
*/
# define DST_SEL(x) ((x) << 16)
/* 0 - MC
* 1 - TC / L2
*/
# define PACKET3_EVENT_WRITE_EOS 0x48
# define PACKET3_RELEASE_MEM 0x49
# define PACKET3_PREAMBLE_CNTL 0x4A
# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
# define PACKET3_DMA_DATA 0x50
/* 1. header
* 2. CONTROL
* 3. SRC_ADDR_LO or DATA [ 31 : 0 ]
* 4. SRC_ADDR_HI [ 31 : 0 ]
* 5. DST_ADDR_LO [ 31 : 0 ]
* 6. DST_ADDR_HI [ 7 : 0 ]
* 7. COMMAND [ 30 : 21 ] | BYTE_COUNT [ 20 : 0 ]
*/
/* CONTROL */
# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
/* 0 - ME
* 1 - PFP
*/
# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
/* 0 - LRU
* 1 - Stream
* 2 - Bypass
*/
# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
/* 0 - DST_ADDR using DAS
* 1 - GDS
* 3 - DST_ADDR using L2
*/
# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
/* 0 - LRU
* 1 - Stream
* 2 - Bypass
*/
# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
/* 0 - SRC_ADDR using SAS
* 1 - GDS
* 2 - DATA
* 3 - SRC_ADDR using L2
*/
# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
/* COMMAND */
# define PACKET3_DMA_DATA_DIS_WC (1 << 21)
# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
/* 0 - none
* 1 - 8 in 16
* 2 - 8 in 32
* 3 - 8 in 64
*/
# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
/* 0 - none
* 1 - 8 in 16
* 2 - 8 in 32
* 3 - 8 in 64
*/
# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
/* 0 - memory
* 1 - register
*/
# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
/* 0 - memory
* 1 - register
*/
# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
# define PACKET3_AQUIRE_MEM 0x58
# define PACKET3_REWIND 0x59
# define PACKET3_LOAD_UCONFIG_REG 0x5E
# define PACKET3_LOAD_SH_REG 0x5F
# define PACKET3_LOAD_CONFIG_REG 0x60
# define PACKET3_LOAD_CONTEXT_REG 0x61
# define PACKET3_SET_CONFIG_REG 0x68
# define PACKET3_SET_CONFIG_REG_START 0x00002000
# define PACKET3_SET_CONFIG_REG_END 0x00002c00
# define PACKET3_SET_CONTEXT_REG 0x69
# define PACKET3_SET_CONTEXT_REG_START 0x0000a000
# define PACKET3_SET_CONTEXT_REG_END 0x0000a400
# define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
# define PACKET3_SET_SH_REG 0x76
# define PACKET3_SET_SH_REG_START 0x00002c00
# define PACKET3_SET_SH_REG_END 0x00003000
# define PACKET3_SET_SH_REG_OFFSET 0x77
# define PACKET3_SET_QUEUE_REG 0x78
# define PACKET3_SET_UCONFIG_REG 0x79
# define PACKET3_SET_UCONFIG_REG_START 0x0000c000
# define PACKET3_SET_UCONFIG_REG_END 0x0000c400
# define PACKET3_SCRATCH_RAM_WRITE 0x7D
# define PACKET3_SCRATCH_RAM_READ 0x7E
# define PACKET3_LOAD_CONST_RAM 0x80
# define PACKET3_WRITE_CONST_RAM 0x81
# define PACKET3_DUMP_CONST_RAM 0x83
# define PACKET3_INCREMENT_CE_COUNTER 0x84
# define PACKET3_INCREMENT_DE_COUNTER 0x85
# define PACKET3_WAIT_ON_CE_COUNTER 0x86
# define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
# define PACKET3_SWITCH_BUFFER 0x8B
# define VCE_CMD_NO_OP 0x00000000
# define VCE_CMD_END 0x00000001
# define VCE_CMD_IB 0x00000002
# define VCE_CMD_FENCE 0x00000003
# define VCE_CMD_TRAP 0x00000004
# define VCE_CMD_IB_AUTO 0x00000005
# define VCE_CMD_SEMAPHORE 0x00000006
# endif
