2005-04-16 15:20:36 -07:00
/ * break. S : B r e a k i n t e r r u p t h a n d l i n g ( k e p t s e p a r a t e f r o m e n t r y . S )
*
* Copyright ( C ) 2 0 0 3 R e d H a t , I n c . A l l R i g h t s R e s e r v e d .
* Written b y D a v i d H o w e l l s ( d h o w e l l s @redhat.com)
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or
* modify i t u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* as p u b l i s h e d b y t h e F r e e S o f t w a r e F o u n d a t i o n ; either version
* 2 of t h e L i c e n s e , o r ( a t y o u r o p t i o n ) a n y l a t e r v e r s i o n .
* /
# include < l i n u x / l i n k a g e . h >
# include < a s m / s e t u p . h >
# include < a s m / s e g m e n t . h >
# include < a s m / p t r a c e . h >
2006-07-10 04:44:55 -07:00
# include < a s m / t h r e a d _ i n f o . h >
2005-04-16 15:20:36 -07:00
# include < a s m / s p r - r e g s . h >
# include < a s m / e r r n o . h >
#
# the b r e a k h a n d l e r h a s i t s o w n s t a c k
#
2010-02-20 01:03:39 +01:00
.section .bss . .stack
2005-04-16 15:20:36 -07:00
.globl __break_user_context
2006-07-10 04:44:55 -07:00
.balign THREAD_SIZE
2005-04-16 15:20:36 -07:00
__break_stack :
2006-07-10 04:44:55 -07:00
.space THREAD_SIZE - FRV_ F R A M E 0 _ S I Z E
__break_frame_0 :
.space FRV_FRAME0_SIZE
2005-04-16 15:20:36 -07:00
#
# miscellaneous v a r i a b l e s
#
.section .bss
# ifdef C O N F I G _ M M U
.globl __break_tlb_miss_real_return_info
__break_tlb_miss_real_return_info :
.balign 8
.space 2 * 4 /* saved PCSR, PSR for TLB-miss handler fixup */
# endif
__break_trace_through_exceptions :
.space 4
# define C S 2 _ E C S 1 0 x e 1 2 0 0 0 0 0
# define C S 2 _ U S E R L E D 0 x4
.macro LEDS val,r e g
# sethi. p % h i ( C S 2 _ E C S 1 + C S 2 _ U S E R L E D ) ,g r30
# setlo % l o ( C S 2 _ E C S 1 + C S 2 _ U S E R L E D ) ,g r30
# setlos #~ \ v a l , \ r e g
# st \ r e g ,@(gr30,gr0)
# setlos #0x5555 ,\ r e g
# sethi. p % h i ( 0 x f f c00 1 0 0 ) ,g r30
# setlo % l o ( 0 x f f c00 1 0 0 ) ,g r30
# sth \ r e g ,@(gr30,gr0)
# membar
.endm
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# entry p o i n t f o r B r e a k E x c e p t i o n s / I n t e r r u p t s
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
2010-02-20 01:03:56 +01:00
.section .text . .break
2005-04-16 15:20:36 -07:00
.balign 4
.globl __entry_break
__entry_break :
# ifdef C O N F I G _ M M U
movgs g r31 ,s c r3
# endif
LEDS 0 x10 0 1 ,g r31
2006-07-10 04:44:55 -07:00
sethi. p % h i ( _ _ b r e a k _ f r a m e _ 0 ) ,g r31
setlo % l o ( _ _ b r e a k _ f r a m e _ 0 ) ,g r31
2005-04-16 15:20:36 -07:00
stdi g r2 ,@(gr31,#REG_GR(2))
movsg c c r ,g r3
sti g r3 ,@(gr31,#REG_CCR)
# catch t h e r e t u r n f r o m a T L B - m i s s h a n d l e r t h a t h a d s i n g l e - s t e p d i s a b l e d
# traps w i l l b e e n a b l e d , s o w e h a v e t o d o t h i s n o w
# ifdef C O N F I G _ M M U
movsg b p c s r ,g r3
sethi. p % h i ( _ _ b r e a k _ t l b _ m i s s _ r e t u r n _ b r e a k s _ h e r e ) ,g r2
setlo % l o ( _ _ b r e a k _ t l b _ m i s s _ r e t u r n _ b r e a k s _ h e r e ) ,g r2
subcc g r2 ,g r3 ,g r0 ,i c c0
beq i c c0 ,#2 ,_ _ b r e a k _ r e t u r n _ s i n g l e s t e p _ t l b m i s s
# endif
# determine w h e t h e r w e h a v e s t e p p e d t h r o u g h i n t o a n e x c e p t i o n
# - we n e e d t o t a k e s p e c i a l a c t i o n t o s u s p e n d h / w s i n g l e s t e p p i n g i f w e ' v e d o n e
# that, s o t h a t t h e g d b s t u b d o e s n ' t g e t b o g g e d d o w n e n d l e s s l y s t e p p i n g t h r o u g h
# external i n t e r r u p t h a n d l i n g
movsg b p s r ,g r3
andicc g r3 ,#B P S R _ B E T , g r 0 ,i c c0
bne i c c0 ,#2 ,_ _ b r e a k _ m a y b e _ u s e r s p a c e / * j u m p i f P S R . E T w a s 1 * /
LEDS 0 x10 0 3 ,g r2
movsg b r r ,g r3
andicc g r3 ,#B R R _ S T , g r 0 ,i c c0
andicc. p g r3 ,#B R R _ S B , g r 0 ,i c c1
bne i c c0 ,#2 ,_ _ b r e a k _ s t e p / * j u m p i f s i n g l e - s t e p c a u s e d b r e a k * /
beq i c c1 ,#2 ,_ _ b r e a k _ c o n t i n u e / * j u m p i f B R E A K d i d n ' t c a u s e b r e a k * /
LEDS 0 x10 0 7 ,g r2
# handle s p e c i a l b r e a k s
movsg b p c s r ,g r3
sethi. p % h i ( _ _ e n t r y _ r e t u r n _ s i n g l e s t e p _ b r e a k s _ h e r e ) ,g r2
setlo % l o ( _ _ e n t r y _ r e t u r n _ s i n g l e s t e p _ b r e a k s _ h e r e ) ,g r2
subcc g r2 ,g r3 ,g r0 ,i c c0
beq i c c0 ,#2 ,_ _ b r e a k _ r e t u r n _ s i n g l e s t e p
bra _ _ b r e a k _ c o n t i n u e
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# handle B R E A K i n s t r u c t i o n i n k e r n e l - m o d e e x c e p t i o n e p i l o g u e
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
__break_return_singlestep :
LEDS 0 x10 0 f ,g r2
# special b r e a k i n s n r e q u e s t s s i n g l e - s t e p p i n g t o b e t u r n e d b a c k o n
# HERE R E T T
# PSR. E T 0 0
# PSR. P S o l d P S R . S ?
# PSR. S 1 1
# BPSR. E T 0 1 ( c a n ' t h a v e c a u s e d o r i g e x c e p o t h e r w i s e )
# BPSR. B S 1 o l d P S R . S
movsg d c r ,g r2
sethi. p % h i ( D C R _ S E ) ,g r3
setlo % l o ( D C R _ S E ) ,g r3
or g r2 ,g r3 ,g r2
movgs g r2 ,d c r
movsg p s r ,g r2
andi g r2 ,#P S R _ P S , g r 2
slli g r2 ,#11 ,g r2 / * P S R . P S - > B P S R . B S * /
ori g r2 ,#B P S R _ B E T , g r 2 / * 1 - > B P S R . B E T * /
movgs g r2 ,b p s r
# return t o t h e i n v o k e r o f t h e o r i g i n a l k e r n e l e x c e p t i o n
movsg p c s r ,g r2
movgs g r2 ,b p c s r
LEDS 0 x10 1 f ,g r2
ldi @(gr31,#REG_CCR),gr3
movgs g r3 ,c c r
lddi. p @(gr31,#REG_GR(2)),gr2
xor g r31 ,g r31 ,g r31
movgs g r0 ,b r r
# ifdef C O N F I G _ M M U
movsg s c r3 ,g r31
# endif
rett #1
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# handle B R E A K i n s t r u c t i o n i n T L B - m i s s h a n d l e r r e t u r n p a t h
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
# ifdef C O N F I G _ M M U
__break_return_singlestep_tlbmiss :
LEDS 0 x11 0 0 ,g r2
sethi. p % h i ( _ _ b r e a k _ t l b _ m i s s _ r e a l _ r e t u r n _ i n f o ) ,g r3
setlo % l o ( _ _ b r e a k _ t l b _ m i s s _ r e a l _ r e t u r n _ i n f o ) ,g r3
lddi @(gr3,#0),gr2
movgs g r2 ,p c s r
movgs g r3 ,p s r
bra _ _ b r e a k _ r e t u r n _ s i n g l e s t e p
# endif
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# handle s i n g l e s t e p p i n g i n t o a n e x c e p t i o n p r o l o g u e f r o m k e r n e l m o d e
# - we t r y a n d c a t c h i t w h i l s t i t i s s t i l l i n t h e m a i n v e c t o r t a b l e
# - if w e c a t c h i t t h e r e , w e h a v e t o j u m p t o t h e f i x u p h a n d l e r
# - there i s a f i x u p t a b l e t h a t h a s a p o i n t e r f o r e v e r y 1 6 b s l o t i n t h e t r a p
# table
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
__break_step :
LEDS 0 x20 0 3 ,g r2
# external i n t e r r u p t s s e e m t o e s c a p e f r o m t h e t r a p t a b l e b e f o r e s i n g l e
# step c a t c h e s u p w i t h t h e m
movsg b p c s r ,g r2
sethi. p % h i ( _ _ e n t r y _ k e r n e l _ e x t e r n a l _ i n t e r r u p t ) ,g r3
setlo % l o ( _ _ e n t r y _ k e r n e l _ e x t e r n a l _ i n t e r r u p t ) ,g r3
[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-14 13:53:20 -08:00
subcc. p g r2 ,g r3 ,g r0 ,i c c0
sethi % h i ( _ _ e n t r y _ u s p a c e _ e x t e r n a l _ i n t e r r u p t ) ,g r3
setlo. p % l o ( _ _ e n t r y _ u s p a c e _ e x t e r n a l _ i n t e r r u p t ) ,g r3
2005-04-16 15:20:36 -07:00
beq i c c0 ,#2 ,_ _ b r e a k _ s t e p _ k e r n e l _ e x t e r n a l _ i n t e r r u p t
[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-14 13:53:20 -08:00
subcc. p g r2 ,g r3 ,g r0 ,i c c0
sethi % h i ( _ _ e n t r y _ k e r n e l _ e x t e r n a l _ i n t e r r u p t _ v i r t u a l l y _ d i s a b l e d ) ,g r3
setlo. p % l o ( _ _ e n t r y _ k e r n e l _ e x t e r n a l _ i n t e r r u p t _ v i r t u a l l y _ d i s a b l e d ) ,g r3
2005-04-16 15:20:36 -07:00
beq i c c0 ,#2 ,_ _ b r e a k _ s t e p _ u s p a c e _ e x t e r n a l _ i n t e r r u p t
[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-14 13:53:20 -08:00
subcc. p g r2 ,g r3 ,g r0 ,i c c0
sethi % h i ( _ _ e n t r y _ k e r n e l _ e x t e r n a l _ i n t e r r u p t _ v i r t u a l _ r e e n a b l e ) ,g r3
setlo. p % l o ( _ _ e n t r y _ k e r n e l _ e x t e r n a l _ i n t e r r u p t _ v i r t u a l _ r e e n a b l e ) ,g r3
beq i c c0 ,#2 ,_ _ b r e a k _ s t e p _ k e r n e l _ e x t e r n a l _ i n t e r r u p t _ v i r t u a l l y _ d i s a b l e d
subcc g r2 ,g r3 ,g r0 ,i c c0
beq i c c0 ,#2 ,_ _ b r e a k _ s t e p _ k e r n e l _ e x t e r n a l _ i n t e r r u p t _ v i r t u a l _ r e e n a b l e
2005-04-16 15:20:36 -07:00
LEDS 0 x20 0 7 ,g r2
# the t w o m a i n v e c t o r t a b l e s a r e a d j a c e n t o n o n e 8 K b s l a b
movsg b p c s r ,g r2
setlos #0xffffe000 ,g r3
and g r2 ,g r3 ,g r2
sethi. p % h i ( _ _ t r a p _ t a b l e s ) ,g r3
setlo % l o ( _ _ t r a p _ t a b l e s ) ,g r3
subcc g r2 ,g r3 ,g r0 ,i c c0
bne i c c0 ,#2 ,_ _ b r e a k _ c o n t i n u e
LEDS 0 x20 0 f ,g r2
# skip w o r k a r o u n d i f s o r e q u e s t e d b y G D B
sethi. p % h i ( _ _ b r e a k _ t r a c e _ t h r o u g h _ e x c e p t i o n s ) ,g r3
setlo % l o ( _ _ b r e a k _ t r a c e _ t h r o u g h _ e x c e p t i o n s ) ,g r3
ld @(gr3,gr0),gr3
subcc g r3 ,g r0 ,g r0 ,i c c0
bne i c c0 ,#0 ,_ _ b r e a k _ c o n t i n u e
LEDS 0 x20 1 f ,g r2
# access t h e f i x u p t a b l e - t h e r e ' s a 1 : 1 m a p p i n g b e t w e e n t h e s l o t s i n t h e t r a p t a b l e s a n d
# the s l o t s i n t h e t r a p f i x u p t a b l e s a l l o w i n g u s t o s i m p l y d i v i d e t h e o f f s e t i n t o t h e
# former b y 4 t o a c c e s s t h e l a t t e r
sethi. p % h i ( _ _ t r a p _ t a b l e s ) ,g r3
setlo % l o ( _ _ t r a p _ t a b l e s ) ,g r3
movsg b p c s r ,g r2
sub g r2 ,g r3 ,g r2
srli. p g r2 ,#2 ,g r2
sethi % h i ( _ _ t r a p _ f i x u p _ t a b l e s ) ,g r3
setlo. p % l o ( _ _ t r a p _ f i x u p _ t a b l e s ) ,g r3
andi g r2 ,#~ 3 ,g r2
ld @(gr2,gr3),gr2
jmpil @(gr2,#0)
# step t h r o u g h a n i n t e r n a l e x c e p t i o n f r o m k e r n e l m o d e
.globl __break_step_kernel_softprog_interrupt
__break_step_kernel_softprog_interrupt :
sethi. p % h i ( _ _ e n t r y _ k e r n e l _ s o f t p r o g _ i n t e r r u p t _ r e e n t r y ) ,g r3
setlo % l o ( _ _ e n t r y _ k e r n e l _ s o f t p r o g _ i n t e r r u p t _ r e e n t r y ) ,g r3
bra _ _ b r e a k _ r e t u r n _ a s _ k e r n e l _ p r o l o g u e
# step t h r o u g h a n e x t e r n a l i n t e r r u p t f r o m k e r n e l m o d e
.globl __break_step_kernel_external_interrupt
__break_step_kernel_external_interrupt :
[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-14 13:53:20 -08:00
# deal w i t h v i r t u a l i n t e r r u p t d i s a b l e m e n t
beq i c c2 ,#0 ,_ _ b r e a k _ s t e p _ k e r n e l _ e x t e r n a l _ i n t e r r u p t _ v i r t u a l l y _ d i s a b l e d
2005-04-16 15:20:36 -07:00
sethi. p % h i ( _ _ e n t r y _ k e r n e l _ e x t e r n a l _ i n t e r r u p t _ r e e n t r y ) ,g r3
setlo % l o ( _ _ e n t r y _ k e r n e l _ e x t e r n a l _ i n t e r r u p t _ r e e n t r y ) ,g r3
__break_return_as_kernel_prologue :
LEDS 0 x20 3 f ,g r2
movgs g r3 ,b p c s r
# do t h e b i t w e h a d t o s k i p
# ifdef C O N F I G _ M M U
movsg e a r0 ,g r2 / * E A R 0 c a n g e t c l o b b e r e d b y g d b - s t u b ( I C I / I C E I ) * /
movgs g r2 ,s c r2
# endif
or. p s p ,g r0 ,g r2 / * s e t u p t h e s t a c k p o i n t e r * /
subi s p ,#R E G _ _ E N D , s p
sti. p g r2 ,@(sp,#REG_SP)
setlos #R E G _ _ S T A T U S _ S T E P , g r 2
sti g r2 ,@(sp,#REG__STATUS) /* record single step status */
# cancel s i n g l e - s t e p p i n g m o d e
movsg d c r ,g r2
sethi. p % h i ( ~ D C R _ S E ) ,g r3
setlo % l o ( ~ D C R _ S E ) ,g r3
and g r2 ,g r3 ,g r2
movgs g r2 ,d c r
LEDS 0 x20 7 f ,g r2
ldi @(gr31,#REG_CCR),gr3
movgs g r3 ,c c r
lddi. p @(gr31,#REG_GR(2)),gr2
xor g r31 ,g r31 ,g r31
movgs g r0 ,b r r
# ifdef C O N F I G _ M M U
movsg s c r3 ,g r31
# endif
rett #1
[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-14 13:53:20 -08:00
# we s i n g l e - s t e p p e d i n t o a n i n t e r r u p t h a n d l e r w h i l s t i n t e r r u p t s w e r e m e r e l y v i r t u a l l y d i s a b l e d
# need t o r e a l l y d i s a b l e i n t e r r u p t s , s e t f l a g , f i x u p a n d r e t u r n
__break_step_kernel_external_interrupt_virtually_disabled :
movsg p s r ,g r2
andi g r2 ,#~ P S R _ P I L , g r 2
ori g r2 ,#P S R _ P I L _ 14 ,g r2 / * d e b u g g i n g i n t e r r u p t s o n l y * /
movgs g r2 ,p s r
ldi @(gr31,#REG_CCR),gr3
movgs g r3 ,c c r
subcc. p g r0 ,g r0 ,g r0 ,i c c2 / * l e a v e Z s e t , c l e a r C * /
# exceptions m u s t ' v e b e e n e n a b l e d a n d w e m u s t ' v e b e e n i n s u p e r v i s o r m o d e
setlos B P S R _ B E T | B P S R _ B S ,g r3
movgs g r3 ,b p s r
# return t o w h e r e t h e i n t e r r u p t h a p p e n e d
movsg p c s r ,g r2
movgs g r2 ,b p c s r
lddi. p @(gr31,#REG_GR(2)),gr2
xor g r31 ,g r31 ,g r31
movgs g r0 ,b r r
# ifdef C O N F I G _ M M U
movsg s c r3 ,g r31
# endif
rett #1
# we s t e p p e d t h r o u g h i n t o t h e v i r t u a l i n t e r r u p t r e e n a b l e m e n t t r a p
#
# we a l s o w a n t t o s i n g l e s t e p a n y w a y , b u t a f t e r f i x i n g u p s o t h a t w e g e t a n e v e n t o n t h e
# instruction a f t e r t h e b r o k e n - i n t o e x c e p t i o n r e t u r n s
.globl __break_step_kernel_external_interrupt_virtual_reenable
__break_step_kernel_external_interrupt_virtual_reenable :
movsg p s r ,g r2
andi g r2 ,#~ P S R _ P I L , g r 2
movgs g r2 ,p s r
ldi @(gr31,#REG_CCR),gr3
movgs g r3 ,c c r
subicc g r0 ,#1 ,g r0 ,i c c2 / * c l e a r Z , s e t C * /
# save t h e a d j u s t e d I C C 2
movsg c c r ,g r3
sti g r3 ,@(gr31,#REG_CCR)
# exceptions m u s t ' v e b e e n e n a b l e d a n d w e m u s t ' v e b e e n i n s u p e r v i s o r m o d e
setlos B P S R _ B E T | B P S R _ B S ,g r3
movgs g r3 ,b p s r
# return t o w h e r e t h e t r a p h a p p e n e d
movsg p c s r ,g r2
movgs g r2 ,b p c s r
# and t h e n p r o c e s s t h e s i n g l e s t e p
bra _ _ b r e a k _ c o n t i n u e
2005-04-16 15:20:36 -07:00
# step t h r o u g h a n i n t e r n a l e x c e p t i o n f r o m u s p a c e m o d e
.globl __break_step_uspace_softprog_interrupt
__break_step_uspace_softprog_interrupt :
sethi. p % h i ( _ _ e n t r y _ u s p a c e _ s o f t p r o g _ i n t e r r u p t _ r e e n t r y ) ,g r3
setlo % l o ( _ _ e n t r y _ u s p a c e _ s o f t p r o g _ i n t e r r u p t _ r e e n t r y ) ,g r3
bra _ _ b r e a k _ r e t u r n _ a s _ u s p a c e _ p r o l o g u e
# step t h r o u g h a n e x t e r n a l i n t e r r u p t f r o m k e r n e l m o d e
.globl __break_step_uspace_external_interrupt
__break_step_uspace_external_interrupt :
sethi. p % h i ( _ _ e n t r y _ u s p a c e _ e x t e r n a l _ i n t e r r u p t _ r e e n t r y ) ,g r3
setlo % l o ( _ _ e n t r y _ u s p a c e _ e x t e r n a l _ i n t e r r u p t _ r e e n t r y ) ,g r3
__break_return_as_uspace_prologue :
LEDS 0 x20 f f ,g r2
movgs g r3 ,b p c s r
# do t h e b i t w e h a d t o s k i p
sethi. p % h i ( _ _ k e r n e l _ f r a m e 0 _ p t r ) ,g r28
setlo % l o ( _ _ k e r n e l _ f r a m e 0 _ p t r ) ,g r28
ldi. p @(gr28,#0),gr28
setlos #R E G _ _ S T A T U S _ S T E P , g r 2
sti g r2 ,@(gr28,#REG__STATUS) /* record single step status */
# cancel s i n g l e - s t e p p i n g m o d e
movsg d c r ,g r2
sethi. p % h i ( ~ D C R _ S E ) ,g r3
setlo % l o ( ~ D C R _ S E ) ,g r3
and g r2 ,g r3 ,g r2
movgs g r2 ,d c r
LEDS 0 x20 f e ,g r2
ldi @(gr31,#REG_CCR),gr3
movgs g r3 ,c c r
lddi. p @(gr31,#REG_GR(2)),gr2
xor g r31 ,g r31 ,g r31
movgs g r0 ,b r r
# ifdef C O N F I G _ M M U
movsg s c r3 ,g r31
# endif
rett #1
# ifdef C O N F I G _ M M U
# step t h r o u g h a n I T L B - m i s s h a n d l e r f r o m u s e r m o d e
.globl __break_user_insn_tlb_miss
__break_user_insn_tlb_miss :
# we' l l w a n t t o t r y t h e t r a p s t u b a g a i n
sethi. p % h i ( _ _ t r a p _ u s e r _ i n s n _ t l b _ m i s s ) ,g r2
setlo % l o ( _ _ t r a p _ u s e r _ i n s n _ t l b _ m i s s ) ,g r2
movgs g r2 ,b p c s r
__break_tlb_miss_common :
LEDS 0 x21 0 1 ,g r2
# cancel s i n g l e - s t e p p i n g m o d e
movsg d c r ,g r2
sethi. p % h i ( ~ D C R _ S E ) ,g r3
setlo % l o ( ~ D C R _ S E ) ,g r3
and g r2 ,g r3 ,g r2
movgs g r2 ,d c r
# we' l l s w a p t h e r e a l r e t u r n a d d r e s s f o r o n e w i t h a B R E A K i n s n s o t h a t w e c a n r e - e n a b l e
# single s t e p p i n g o n r e t u r n
movsg p c s r ,g r2
sethi. p % h i ( _ _ b r e a k _ t l b _ m i s s _ r e a l _ r e t u r n _ i n f o ) ,g r3
setlo % l o ( _ _ b r e a k _ t l b _ m i s s _ r e a l _ r e t u r n _ i n f o ) ,g r3
sti g r2 ,@(gr3,#0)
sethi. p % h i ( _ _ b r e a k _ t l b _ m i s s _ r e t u r n _ b r e a k ) ,g r2
setlo % l o ( _ _ b r e a k _ t l b _ m i s s _ r e t u r n _ b r e a k ) ,g r2
movgs g r2 ,p c s r
# we a l s o h a v e t o f u d g e P S R b e c a u s e t h e r e t u r n B R E A K i s i n k e r n e l s p a c e a n d w e w a n t
# to g e t a B R E A K f a u l t n o t a n a c c e s s v i o l a t i o n s h o u l d t h e r e t u r n b e t o u s e r s p a c e
movsg p s r ,g r2
sti. p g r2 ,@(gr3,#4)
ori g r2 ,#P S R _ P S , g r 2
movgs g r2 ,p s r
LEDS 0 x21 0 2 ,g r2
ldi @(gr31,#REG_CCR),gr3
movgs g r3 ,c c r
lddi @(gr31,#REG_GR(2)),gr2
movsg s c r3 ,g r31
movgs g r0 ,b r r
rett #1
# step t h r o u g h a D T L B - m i s s h a n d l e r f r o m u s e r m o d e
.globl __break_user_data_tlb_miss
__break_user_data_tlb_miss :
# we' l l w a n t t o t r y t h e t r a p s t u b a g a i n
sethi. p % h i ( _ _ t r a p _ u s e r _ d a t a _ t l b _ m i s s ) ,g r2
setlo % l o ( _ _ t r a p _ u s e r _ d a t a _ t l b _ m i s s ) ,g r2
movgs g r2 ,b p c s r
bra _ _ b r e a k _ t l b _ m i s s _ c o m m o n
# step t h r o u g h a n I T L B - m i s s h a n d l e r f r o m k e r n e l m o d e
.globl __break_kernel_insn_tlb_miss
__break_kernel_insn_tlb_miss :
# we' l l w a n t t o t r y t h e t r a p s t u b a g a i n
sethi. p % h i ( _ _ t r a p _ k e r n e l _ i n s n _ t l b _ m i s s ) ,g r2
setlo % l o ( _ _ t r a p _ k e r n e l _ i n s n _ t l b _ m i s s ) ,g r2
movgs g r2 ,b p c s r
bra _ _ b r e a k _ t l b _ m i s s _ c o m m o n
# step t h r o u g h a D T L B - m i s s h a n d l e r f r o m k e r n e l m o d e
.globl __break_kernel_data_tlb_miss
__break_kernel_data_tlb_miss :
# we' l l w a n t t o t r y t h e t r a p s t u b a g a i n
sethi. p % h i ( _ _ t r a p _ k e r n e l _ d a t a _ t l b _ m i s s ) ,g r2
setlo % l o ( _ _ t r a p _ k e r n e l _ d a t a _ t l b _ m i s s ) ,g r2
movgs g r2 ,b p c s r
bra _ _ b r e a k _ t l b _ m i s s _ c o m m o n
# endif
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# handle d e b u g e v e n t s o r i g i n a t i n g w i t h u s e r s p a c e
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
__break_maybe_userspace :
LEDS 0 x30 0 3 ,g r2
setlos #B P S R _ B S , g r 2
andcc g r3 ,g r2 ,g r0 ,i c c0
bne i c c0 ,#0 ,_ _ b r e a k _ c o n t i n u e / * s k i p i f P S R . S w a s 1 * /
movsg b r r ,g r2
andicc g r2 ,#B R R _ S T | B R R _ S B , g r 0 ,i c c0
beq i c c0 ,#0 ,_ _ b r e a k _ c o n t i n u e / * j u m p i f n o t B R E A K o r s i n g l e - s t e p * /
LEDS 0 x30 0 7 ,g r2
# do t h e f i r s t p a r t o f t h e e x c e p t i o n p r o l o g u e h e r e
sethi. p % h i ( _ _ k e r n e l _ f r a m e 0 _ p t r ) ,g r28
setlo % l o ( _ _ k e r n e l _ f r a m e 0 _ p t r ) ,g r28
ldi @(gr28,#0),gr28
andi g r28 ,#~ 7 ,g r28
# set u p t h e k e r n e l s t a c k p o i n t e r
sti s p ,@(gr28,#REG_SP)
ori g r28 ,0 ,s p
sti g r0 ,@(gr28,#REG_GR(28))
stdi g r20 ,@(gr28,#REG_GR(20))
stdi g r22 ,@(gr28,#REG_GR(22))
movsg t b r ,g r20
movsg b p c s r ,g r21
movsg p s r ,g r22
# determine t h e e x c e p t i o n t y p e a n d c a n c e l s i n g l e - s t e p p i n g m o d e
or g r0 ,g r0 ,g r23
movsg d c r ,g r2
sethi. p % h i ( D C R _ S E ) ,g r3
setlo % l o ( D C R _ S E ) ,g r3
andcc g r2 ,g r3 ,g r0 ,i c c0
beq i c c0 ,#0 ,_ _ b r e a k _ n o _ u s e r _ s s t e p / * m u s t h a v e b e e n a B R E A K i n s n * /
not g r3 ,g r3
and g r2 ,g r3 ,g r2
movgs g r2 ,d c r
ori g r23 ,#R E G _ _ S T A T U S _ S T E P , g r 23
__break_no_user_sstep :
LEDS 0 x30 0 f ,g r2
movsg b r r ,g r2
andi g r2 ,#B R R _ S T | B R R _ S B , g r 2
slli g r2 ,#1 ,g r2
or g r23 ,g r2 ,g r23
sti. p g r23 ,@(gr28,#REG__STATUS) /* record single step status */
# adjust t h e v a l u e a c q u i r e d f r o m T B R - t h i s i n d i c a t e s t h e e x c e p t i o n
setlos #~ T B R _ T T , g r 2
and. p g r20 ,g r2 ,g r20
setlos #T B R _ T T _ B R E A K , g r 2
or. p g r20 ,g r2 ,g r20
# fudge P S R . P S a n d B P S R . B S t o r e t u r n t o k e r n e l m o d e t h r o u g h t h e t r a p
# table a s t r a p 1 2 6
andi g r22 ,#~ P S R _ P S , g r 22 / * P S R . P S s h o u l d b e 0 * /
movgs g r22 ,p s r
setlos #B P S R _ B S , g r 2 / * B P S R . B S s h o u l d b e 1 a n d B P S R . B E T 0 * /
movgs g r2 ,b p s r
# return t h r o u g h r e m a i n d e r o f t h e e x c e p t i o n p r o l o g u e
# - need t o l o a d g r23 w i t h r e t u r n h a n d l e r a d d r e s s
sethi. p % h i ( _ _ e n t r y _ r e t u r n _ f r o m _ u s e r _ e x c e p t i o n ) ,g r23
setlo % l o ( _ _ e n t r y _ r e t u r n _ f r o m _ u s e r _ e x c e p t i o n ) ,g r23
sethi. p % h i ( _ _ e n t r y _ c o m m o n ) ,g r3
setlo % l o ( _ _ e n t r y _ c o m m o n ) ,g r3
movgs g r3 ,b p c s r
LEDS 0 x30 1 f ,g r2
ldi @(gr31,#REG_CCR),gr3
movgs g r3 ,c c r
lddi. p @(gr31,#REG_GR(2)),gr2
xor g r31 ,g r31 ,g r31
movgs g r0 ,b r r
# ifdef C O N F I G _ M M U
movsg s c r3 ,g r31
# endif
rett #1
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# resume n o r m a l d e b u g - m o d e e n t r y
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
__break_continue :
LEDS 0 x40 0 3 ,g r2
# set u p t h e k e r n e l s t a c k p o i n t e r
sti s p ,@(gr31,#REG_SP)
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sethi. p % h i ( _ _ b r e a k _ f r a m e _ 0 ) ,s p
setlo % l o ( _ _ b r e a k _ f r a m e _ 0 ) ,s p
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# finish b u i l d i n g t h e e x c e p t i o n f r a m e
stdi g r4 ,@(gr31,#REG_GR(4))
stdi g r6 ,@(gr31,#REG_GR(6))
stdi g r8 ,@(gr31,#REG_GR(8))
stdi g r10 ,@(gr31,#REG_GR(10))
stdi g r12 ,@(gr31,#REG_GR(12))
stdi g r14 ,@(gr31,#REG_GR(14))
stdi g r16 ,@(gr31,#REG_GR(16))
stdi g r18 ,@(gr31,#REG_GR(18))
stdi g r20 ,@(gr31,#REG_GR(20))
stdi g r22 ,@(gr31,#REG_GR(22))
stdi g r24 ,@(gr31,#REG_GR(24))
stdi g r26 ,@(gr31,#REG_GR(26))
sti g r0 ,@(gr31,#REG_GR(28)) /* NULL frame pointer */
sti g r29 ,@(gr31,#REG_GR(29))
sti g r30 ,@(gr31,#REG_GR(30))
sti g r8 ,@(gr31,#REG_ORIG_GR8)
# ifdef C O N F I G _ M M U
movsg s c r3 ,g r19
sti g r19 ,@(gr31,#REG_GR(31))
# endif
movsg b p s r ,g r19
movsg t b r ,g r20
movsg b p c s r ,g r21
movsg p s r ,g r22
movsg i s r ,g r23
movsg c c c r ,g r25
movsg l r ,g r26
movsg l c r ,g r27
andi. p g r22 ,#~ ( P S R _ S | P S R _ E T ) , g r 5 / * r e b u i l d P S R * /
andi g r19 ,#P S R _ E T , g r 4
or. p g r4 ,g r5 ,g r5
srli g r19 ,#10 ,g r4
andi g r4 ,#P S R _ S , g r 4
or. p g r4 ,g r5 ,g r5
setlos #- 1 ,g r6
sti g r20 ,@(gr31,#REG_TBR)
sti g r21 ,@(gr31,#REG_PC)
sti g r5 ,@(gr31,#REG_PSR)
sti g r23 ,@(gr31,#REG_ISR)
sti g r25 ,@(gr31,#REG_CCCR)
stdi g r26 ,@(gr31,#REG_LR)
sti g r6 ,@(gr31,#REG_SYSCALLNO)
# store C P U - s p e c i f i c r e g s
movsg i a c c0 h ,g r4
movsg i a c c0 l ,g r5
stdi g r4 ,@(gr31,#REG_IACC0)
movsg g n e r0 ,g r4
movsg g n e r1 ,g r5
stdi g r4 ,@(gr31,#REG_GNER0)
# build t h e d e b u g r e g i s t e r f r a m e
movsg b r r ,g r4
movgs g r0 ,b r r
movsg n m a r ,g r5
movsg d c r ,g r6
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sethi. p % h i ( _ _ d e b u g _ s t a t u s ) ,g r7
setlo % l o ( _ _ d e b u g _ s t a t u s ) ,g r7
stdi g r4 ,@(gr7,#DEBUG_BRR)
sti g r19 ,@(gr7,#DEBUG_BPSR)
sti. p g r6 ,@(gr7,#DEBUG_DCR)
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# trap e x c e p t i o n s d u r i n g b r e a k h a n d l i n g a n d d i s a b l e h / w b r e a k p o i n t s / w a t c h p o i n t s
sethi % h i ( D C R _ E B E ) ,g r5
setlo. p % l o ( D C R _ E B E ) ,g r5
sethi % h i ( _ _ e n t r y _ b r e a k t r a p _ t a b l e ) ,g r4
setlo % l o ( _ _ e n t r y _ b r e a k t r a p _ t a b l e ) ,g r4
movgs g r5 ,d c r
movgs g r4 ,t b r
# set u p k e r n e l g l o b a l r e g i s t e r s
sethi. p % h i ( _ _ k e r n e l _ c u r r e n t _ t a s k ) ,g r5
setlo % l o ( _ _ k e r n e l _ c u r r e n t _ t a s k ) ,g r5
ld @(gr5,gr0),gr29
ldi. p @(gr29,#4),gr15 ; __current_thread_info = current->thread_info
sethi % h i ( _ g p ) ,g r16
setlo. p % l o ( _ g p ) ,g r16
# make s u r e w e ( t h e k e r n e l ) g e t d i v - z e r o a n d m i s a l i g n m e n t e x c e p t i o n s
setlos #I S R _ E D E | I S R _ D T T _ D I V B Y Z E R O | I S R _ E M A M _ E X C E P T I O N , g r 5
movgs g r5 ,i s r
# enter t h e G D B s t u b
LEDS 0 x40 0 7 ,g r2
or. p g r0 ,g r0 ,f p
call d e b u g _ s t u b
LEDS 0 x40 3 f ,g r2
# return f r o m b r e a k
lddi @(gr31,#REG_IACC0),gr4
movgs g r4 ,i a c c0 h
movgs g r5 ,i a c c0 l
lddi @(gr31,#REG_GNER0),gr4
movgs g r4 ,g n e r0
movgs g r5 ,g n e r1
lddi @(gr31,#REG_LR) ,gr26
lddi @(gr31,#REG_CCR) ,gr24
lddi @(gr31,#REG_PSR) ,gr22
ldi @(gr31,#REG_PC) ,gr21
ldi @(gr31,#REG_TBR) ,gr20
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sethi. p % h i ( _ _ d e b u g _ s t a t u s ) ,g r6
setlo % l o ( _ _ d e b u g _ s t a t u s ) ,g r6
ldi. p @(gr6,#DEBUG_DCR) ,gr6
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andi g r22 ,#P S R _ S , g r 19 / * r e b u i l d B P S R * /
andi. p g r22 ,#P S R _ E T , g r 5
slli g r19 ,#10 ,g r19
or g r5 ,g r19 ,g r19
movgs g r6 ,d c r
movgs g r19 ,b p s r
movgs g r20 ,t b r
movgs g r21 ,b p c s r
movgs g r23 ,i s r
movgs g r24 ,c c r
movgs g r25 ,c c c r
movgs g r26 ,l r
movgs g r27 ,l c r
LEDS 0 x40 7 f ,g r2
# ifdef C O N F I G _ M M U
ldi @(gr31,#REG_GR(31)),gr2
movgs g r2 ,s c r3
# endif
ldi @(gr31,#REG_GR(30)),gr30
ldi @(gr31,#REG_GR(29)),gr29
lddi @(gr31,#REG_GR(26)),gr26
lddi @(gr31,#REG_GR(24)),gr24
lddi @(gr31,#REG_GR(22)),gr22
lddi @(gr31,#REG_GR(20)),gr20
lddi @(gr31,#REG_GR(18)),gr18
lddi @(gr31,#REG_GR(16)),gr16
lddi @(gr31,#REG_GR(14)),gr14
lddi @(gr31,#REG_GR(12)),gr12
lddi @(gr31,#REG_GR(10)),gr10
lddi @(gr31,#REG_GR(8)) ,gr8
lddi @(gr31,#REG_GR(6)) ,gr6
lddi @(gr31,#REG_GR(4)) ,gr4
lddi @(gr31,#REG_GR(2)) ,gr2
ldi. p @(gr31,#REG_SP) ,sp
xor g r31 ,g r31 ,g r31
movgs g r0 ,b r r
# ifdef C O N F I G _ M M U
movsg s c r3 ,g r31
# endif
rett #1
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# GDB s t u b " s y s t e m c a l l s "
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
# ifdef C O N F I G _ G D B S T U B
# void g d b s t u b _ c o n s o l e _ w r i t e ( s t r u c t c o n s o l e * c o n , c o n s t c h a r * p , u n s i g n e d n )
.globl gdbstub_console_write
gdbstub_console_write :
break
bralr
# endif
# GDB s t u b B U G ( ) t r a p
# GR8 i s t h e p r o p o s e d s i g n a l n u m b e r
.globl __debug_bug_trap
__debug_bug_trap :
break
bralr
# transfer k e r n e l e x e c e p t i o n t o G D B f o r h a n d l i n g
.globl __break_hijack_kernel_event
__break_hijack_kernel_event :
break
.globl __break_hijack_kernel_event_breaks_here
__break_hijack_kernel_event_breaks_here :
nop
# ifdef C O N F I G _ M M U
# handle a r e t u r n f r o m T L B - m i s s t h a t r e q u i r e s s i n g l e - s t e p r e a c t i v a t i o n
.globl __break_tlb_miss_return_break
__break_tlb_miss_return_break :
break
__break_tlb_miss_return_breaks_here :
nop
# endif
# guard t h e f i r s t . t e x t l a b e l i n t h e n e x t f i l e f r o m c o n f u s i o n
nop
